xref: /aosp_15_r20/external/arm-trusted-firmware/plat/rockchip/common/bl31_plat_setup.c (revision 54fd6939e177f8ff529b10183254802c76df6d08)
1 /*
2  * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 
9 #include <platform_def.h>
10 
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <drivers/console.h>
14 #include <drivers/generic_delay_timer.h>
15 #include <drivers/ti/uart/uart_16550.h>
16 #include <lib/mmio.h>
17 #include <plat_private.h>
18 #include <plat/common/platform.h>
19 
20 static entry_point_info_t bl32_ep_info;
21 static entry_point_info_t bl33_ep_info;
22 
23 /*******************************************************************************
24  * Return a pointer to the 'entry_point_info' structure of the next image for
25  * the security state specified. BL33 corresponds to the non-secure image type
26  * while BL32 corresponds to the secure image type. A NULL pointer is returned
27  * if the image does not exist.
28  ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)29 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
30 {
31 	entry_point_info_t *next_image_info;
32 
33 	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
34 
35 	/* None of the images on this platform can have 0x0 as the entrypoint */
36 	if (next_image_info->pc)
37 		return next_image_info;
38 	else
39 		return NULL;
40 }
41 
42 #pragma weak params_early_setup
params_early_setup(u_register_t plat_param_from_bl2)43 void params_early_setup(u_register_t plat_param_from_bl2)
44 {
45 }
46 
47 /*******************************************************************************
48  * Perform any BL3-1 early platform setup. Here is an opportunity to copy
49  * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
50  * are lost (potentially). This needs to be done before the MMU is initialized
51  * so that the memory layout can be used while creating page tables.
52  * BL2 has flushed this information to memory, so we are guaranteed to pick up
53  * good data.
54  ******************************************************************************/
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)55 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
56 				u_register_t arg2, u_register_t arg3)
57 {
58 	static console_t console;
59 	struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0;
60 
61 	params_early_setup(arg1);
62 
63 	if (rockchip_get_uart_base() != 0)
64 		console_16550_register(rockchip_get_uart_base(),
65 				       rockchip_get_uart_clock(),
66 				       rockchip_get_uart_baudrate(), &console);
67 
68 	VERBOSE("bl31_setup\n");
69 
70 	/* Passing a NULL context is a critical programming error */
71 	assert(arg_from_bl2);
72 
73 	assert(arg_from_bl2->h.type == PARAM_BL31);
74 	assert(arg_from_bl2->h.version >= VERSION_1);
75 
76 	bl32_ep_info = *arg_from_bl2->bl32_ep_info;
77 	bl33_ep_info = *arg_from_bl2->bl33_ep_info;
78 }
79 
80 /*******************************************************************************
81  * Perform any BL3-1 platform setup code
82  ******************************************************************************/
bl31_platform_setup(void)83 void bl31_platform_setup(void)
84 {
85 	generic_delay_timer_init();
86 	plat_rockchip_soc_init();
87 
88 	/* Initialize the gic cpu and distributor interfaces */
89 	plat_rockchip_gic_driver_init();
90 	plat_rockchip_gic_init();
91 	plat_rockchip_pmu_init();
92 }
93 
94 /*******************************************************************************
95  * Perform the very early platform specific architectural setup here. At the
96  * moment this is only intializes the mmu in a quick and dirty way.
97  ******************************************************************************/
bl31_plat_arch_setup(void)98 void bl31_plat_arch_setup(void)
99 {
100 	plat_cci_init();
101 	plat_cci_enable();
102 	plat_configure_mmu_el3(BL_CODE_BASE,
103 			       BL_COHERENT_RAM_END - BL_CODE_BASE,
104 			       BL_CODE_BASE,
105 			       BL_CODE_END,
106 			       BL_COHERENT_RAM_BASE,
107 			       BL_COHERENT_RAM_END);
108 }
109