1 /*
2 * Double-precision vector sinh(x) function.
3 *
4 * Copyright (c) 2022-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6 */
7
8 #include "v_math.h"
9 #include "poly_advsimd_f64.h"
10 #include "pl_sig.h"
11 #include "pl_test.h"
12
13 static const struct data
14 {
15 float64x2_t poly[11], inv_ln2;
16 double m_ln2[2];
17 float64x2_t shift;
18 uint64x2_t halff;
19 int64x2_t onef;
20 #if WANT_SIMD_EXCEPT
21 uint64x2_t tiny_bound, thresh;
22 #else
23 uint64x2_t large_bound;
24 #endif
25 } data = {
26 /* Generated using Remez, deg=12 in [-log(2)/2, log(2)/2]. */
27 .poly = { V2 (0x1p-1), V2 (0x1.5555555555559p-3), V2 (0x1.555555555554bp-5),
28 V2 (0x1.111111110f663p-7), V2 (0x1.6c16c16c1b5f3p-10),
29 V2 (0x1.a01a01affa35dp-13), V2 (0x1.a01a018b4ecbbp-16),
30 V2 (0x1.71ddf82db5bb4p-19), V2 (0x1.27e517fc0d54bp-22),
31 V2 (0x1.af5eedae67435p-26), V2 (0x1.1f143d060a28ap-29), },
32
33 .inv_ln2 = V2 (0x1.71547652b82fep0),
34 .m_ln2 = {-0x1.62e42fefa39efp-1, -0x1.abc9e3b39803fp-56},
35 .shift = V2 (0x1.8p52),
36
37 .halff = V2 (0x3fe0000000000000),
38 .onef = V2 (0x3ff0000000000000),
39 #if WANT_SIMD_EXCEPT
40 /* 2^-26, below which sinh(x) rounds to x. */
41 .tiny_bound = V2 (0x3e50000000000000),
42 /* asuint(large_bound) - asuint(tiny_bound). */
43 .thresh = V2 (0x0230000000000000),
44 #else
45 /* 2^9. expm1 helper overflows for large input. */
46 .large_bound = V2 (0x4080000000000000),
47 #endif
48 };
49
50 static inline float64x2_t
expm1_inline(float64x2_t x)51 expm1_inline (float64x2_t x)
52 {
53 const struct data *d = ptr_barrier (&data);
54
55 /* Reduce argument:
56 exp(x) - 1 = 2^i * (expm1(f) + 1) - 1
57 where i = round(x / ln2)
58 and f = x - i * ln2 (f in [-ln2/2, ln2/2]). */
59 float64x2_t j = vsubq_f64 (vfmaq_f64 (d->shift, d->inv_ln2, x), d->shift);
60 int64x2_t i = vcvtq_s64_f64 (j);
61
62 float64x2_t m_ln2 = vld1q_f64 (d->m_ln2);
63 float64x2_t f = vfmaq_laneq_f64 (x, j, m_ln2, 0);
64 f = vfmaq_laneq_f64 (f, j, m_ln2, 1);
65 /* Approximate expm1(f) using polynomial. */
66 float64x2_t f2 = vmulq_f64 (f, f);
67 float64x2_t f4 = vmulq_f64 (f2, f2);
68 float64x2_t f8 = vmulq_f64 (f4, f4);
69 float64x2_t p = vfmaq_f64 (f, f2, v_estrin_10_f64 (f, f2, f4, f8, d->poly));
70 /* t = 2^i. */
71 float64x2_t t = vreinterpretq_f64_u64 (
72 vreinterpretq_u64_s64 (vaddq_s64 (vshlq_n_s64 (i, 52), d->onef)));
73 /* expm1(x) ~= p * t + (t - 1). */
74 return vfmaq_f64 (vsubq_f64 (t, v_f64 (1.0)), p, t);
75 }
76
77 static float64x2_t NOINLINE VPCS_ATTR
special_case(float64x2_t x)78 special_case (float64x2_t x)
79 {
80 return v_call_f64 (sinh, x, x, v_u64 (-1));
81 }
82
83 /* Approximation for vector double-precision sinh(x) using expm1.
84 sinh(x) = (exp(x) - exp(-x)) / 2.
85 The greatest observed error is 2.57 ULP:
86 _ZGVnN2v_sinh (0x1.9fb1d49d1d58bp-2) got 0x1.ab34e59d678dcp-2
87 want 0x1.ab34e59d678d9p-2. */
V_NAME_D1(sinh)88 float64x2_t VPCS_ATTR V_NAME_D1 (sinh) (float64x2_t x)
89 {
90 const struct data *d = ptr_barrier (&data);
91
92 float64x2_t ax = vabsq_f64 (x);
93 uint64x2_t sign
94 = veorq_u64 (vreinterpretq_u64_f64 (x), vreinterpretq_u64_f64 (ax));
95 float64x2_t halfsign = vreinterpretq_f64_u64 (vorrq_u64 (sign, d->halff));
96
97 #if WANT_SIMD_EXCEPT
98 uint64x2_t special = vcgeq_u64 (
99 vsubq_u64 (vreinterpretq_u64_f64 (ax), d->tiny_bound), d->thresh);
100 #else
101 uint64x2_t special = vcgeq_u64 (vreinterpretq_u64_f64 (ax), d->large_bound);
102 #endif
103
104 /* Fall back to scalar variant for all lanes if any of them are special. */
105 if (unlikely (v_any_u64 (special)))
106 return special_case (x);
107
108 /* Up to the point that expm1 overflows, we can use it to calculate sinh
109 using a slight rearrangement of the definition of sinh. This allows us to
110 retain acceptable accuracy for very small inputs. */
111 float64x2_t t = expm1_inline (ax);
112 t = vaddq_f64 (t, vdivq_f64 (t, vaddq_f64 (t, v_f64 (1.0))));
113 return vmulq_f64 (t, halfsign);
114 }
115
116 PL_SIG (V, D, 1, sinh, -10.0, 10.0)
117 PL_TEST_ULP (V_NAME_D1 (sinh), 2.08)
118 PL_TEST_EXPECT_FENV (V_NAME_D1 (sinh), WANT_SIMD_EXCEPT)
119 PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinh), 0, 0x1p-26, 1000)
120 PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinh), 0x1p-26, 0x1p9, 500000)
121 PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinh), 0x1p9, inf, 1000)
122