1 /*
2 * Double-precision vector asinh(x) function.
3 *
4 * Copyright (c) 2022-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6 */
7
8 #include "v_math.h"
9 #include "poly_advsimd_f64.h"
10 #include "pl_sig.h"
11 #include "pl_test.h"
12
13 #define A(i) v_f64 (__v_log_data.poly[i])
14 #define N (1 << V_LOG_TABLE_BITS)
15 #define IndexMask (N - 1)
16
17 const static struct data
18 {
19 float64x2_t poly[18];
20 uint64x2_t off, huge_bound, abs_mask;
21 float64x2_t ln2, tiny_bound;
22 } data = {
23 .off = V2 (0x3fe6900900000000),
24 .ln2 = V2 (0x1.62e42fefa39efp-1),
25 .huge_bound = V2 (0x5fe0000000000000),
26 .tiny_bound = V2 (0x1p-26),
27 .abs_mask = V2 (0x7fffffffffffffff),
28 /* Even terms of polynomial s.t. asinh(x) is approximated by
29 asinh(x) ~= x + x^3 * (C0 + C1 * x + C2 * x^2 + C3 * x^3 + ...).
30 Generated using Remez, f = (asinh(sqrt(x)) - sqrt(x))/x^(3/2). */
31 .poly = { V2 (-0x1.55555555554a7p-3), V2 (0x1.3333333326c7p-4),
32 V2 (-0x1.6db6db68332e6p-5), V2 (0x1.f1c71b26fb40dp-6),
33 V2 (-0x1.6e8b8b654a621p-6), V2 (0x1.1c4daa9e67871p-6),
34 V2 (-0x1.c9871d10885afp-7), V2 (0x1.7a16e8d9d2ecfp-7),
35 V2 (-0x1.3ddca533e9f54p-7), V2 (0x1.0becef748dafcp-7),
36 V2 (-0x1.b90c7099dd397p-8), V2 (0x1.541f2bb1ffe51p-8),
37 V2 (-0x1.d217026a669ecp-9), V2 (0x1.0b5c7977aaf7p-9),
38 V2 (-0x1.e0f37daef9127p-11), V2 (0x1.388b5fe542a6p-12),
39 V2 (-0x1.021a48685e287p-14), V2 (0x1.93d4ba83d34dap-18) },
40 };
41
42 static float64x2_t NOINLINE VPCS_ATTR
special_case(float64x2_t x,float64x2_t y,uint64x2_t special)43 special_case (float64x2_t x, float64x2_t y, uint64x2_t special)
44 {
45 return v_call_f64 (asinh, x, y, special);
46 }
47
48 struct entry
49 {
50 float64x2_t invc;
51 float64x2_t logc;
52 };
53
54 static inline struct entry
lookup(uint64x2_t i)55 lookup (uint64x2_t i)
56 {
57 /* Since N is a power of 2, n % N = n & (N - 1). */
58 struct entry e;
59 uint64_t i0 = (vgetq_lane_u64 (i, 0) >> (52 - V_LOG_TABLE_BITS)) & IndexMask;
60 uint64_t i1 = (vgetq_lane_u64 (i, 1) >> (52 - V_LOG_TABLE_BITS)) & IndexMask;
61 float64x2_t e0 = vld1q_f64 (&__v_log_data.table[i0].invc);
62 float64x2_t e1 = vld1q_f64 (&__v_log_data.table[i1].invc);
63 e.invc = vuzp1q_f64 (e0, e1);
64 e.logc = vuzp2q_f64 (e0, e1);
65 return e;
66 }
67
68 static inline float64x2_t
log_inline(float64x2_t x,const struct data * d)69 log_inline (float64x2_t x, const struct data *d)
70 {
71 /* Double-precision vector log, copied from ordinary vector log with some
72 cosmetic modification and special-cases removed. */
73 uint64x2_t ix = vreinterpretq_u64_f64 (x);
74 uint64x2_t tmp = vsubq_u64 (ix, d->off);
75 int64x2_t k = vshrq_n_s64 (vreinterpretq_s64_u64 (tmp), 52);
76 uint64x2_t iz
77 = vsubq_u64 (ix, vandq_u64 (tmp, vdupq_n_u64 (0xfffULL << 52)));
78 float64x2_t z = vreinterpretq_f64_u64 (iz);
79 struct entry e = lookup (tmp);
80 float64x2_t r = vfmaq_f64 (v_f64 (-1.0), z, e.invc);
81 float64x2_t kd = vcvtq_f64_s64 (k);
82 float64x2_t hi = vfmaq_f64 (vaddq_f64 (e.logc, r), kd, d->ln2);
83 float64x2_t r2 = vmulq_f64 (r, r);
84 float64x2_t y = vfmaq_f64 (A (2), A (3), r);
85 float64x2_t p = vfmaq_f64 (A (0), A (1), r);
86 y = vfmaq_f64 (y, A (4), r2);
87 y = vfmaq_f64 (p, y, r2);
88 y = vfmaq_f64 (hi, y, r2);
89 return y;
90 }
91
92 /* Double-precision implementation of vector asinh(x).
93 asinh is very sensitive around 1, so it is impractical to devise a single
94 low-cost algorithm which is sufficiently accurate on a wide range of input.
95 Instead we use two different algorithms:
96 asinh(x) = sign(x) * log(|x| + sqrt(x^2 + 1) if |x| >= 1
97 = sign(x) * (|x| + |x|^3 * P(x^2)) otherwise
98 where log(x) is an optimized log approximation, and P(x) is a polynomial
99 shared with the scalar routine. The greatest observed error 3.29 ULP, in
100 |x| >= 1:
101 __v_asinh(0x1.2cd9d717e2c9bp+0) got 0x1.ffffcfd0e234fp-1
102 want 0x1.ffffcfd0e2352p-1. */
V_NAME_D1(asinh)103 VPCS_ATTR float64x2_t V_NAME_D1 (asinh) (float64x2_t x)
104 {
105 const struct data *d = ptr_barrier (&data);
106
107 float64x2_t ax = vabsq_f64 (x);
108 uint64x2_t iax = vreinterpretq_u64_f64 (ax);
109
110 uint64x2_t gt1 = vcgeq_f64 (ax, v_f64 (1));
111 uint64x2_t special = vcgeq_u64 (iax, d->huge_bound);
112
113 #if WANT_SIMD_EXCEPT
114 uint64x2_t tiny = vcltq_f64 (ax, d->tiny_bound);
115 special = vorrq_u64 (special, tiny);
116 #endif
117
118 /* Option 1: |x| >= 1.
119 Compute asinh(x) according by asinh(x) = log(x + sqrt(x^2 + 1)).
120 If WANT_SIMD_EXCEPT is enabled, sidestep special values, which will
121 overflow, by setting special lanes to 1. These will be fixed later. */
122 float64x2_t option_1 = v_f64 (0);
123 if (likely (v_any_u64 (gt1)))
124 {
125 #if WANT_SIMD_EXCEPT
126 float64x2_t xm = v_zerofy_f64 (ax, special);
127 #else
128 float64x2_t xm = ax;
129 #endif
130 option_1 = log_inline (
131 vaddq_f64 (xm, vsqrtq_f64 (vfmaq_f64 (v_f64 (1), xm, xm))), d);
132 }
133
134 /* Option 2: |x| < 1.
135 Compute asinh(x) using a polynomial.
136 If WANT_SIMD_EXCEPT is enabled, sidestep special lanes, which will
137 overflow, and tiny lanes, which will underflow, by setting them to 0. They
138 will be fixed later, either by selecting x or falling back to the scalar
139 special-case. The largest observed error in this region is 1.47 ULPs:
140 __v_asinh(0x1.fdfcd00cc1e6ap-1) got 0x1.c1d6bf874019bp-1
141 want 0x1.c1d6bf874019cp-1. */
142 float64x2_t option_2 = v_f64 (0);
143 if (likely (v_any_u64 (vceqzq_u64 (gt1))))
144 {
145 #if WANT_SIMD_EXCEPT
146 ax = v_zerofy_f64 (ax, vorrq_u64 (tiny, gt1));
147 #endif
148 float64x2_t x2 = vmulq_f64 (ax, ax), x3 = vmulq_f64 (ax, x2),
149 z2 = vmulq_f64 (x2, x2), z4 = vmulq_f64 (z2, z2),
150 z8 = vmulq_f64 (z4, z4), z16 = vmulq_f64 (z8, z8);
151 float64x2_t p = v_estrin_17_f64 (x2, z2, z4, z8, z16, d->poly);
152 option_2 = vfmaq_f64 (ax, p, x3);
153 #if WANT_SIMD_EXCEPT
154 option_2 = vbslq_f64 (tiny, x, option_2);
155 #endif
156 }
157
158 /* Choose the right option for each lane. */
159 float64x2_t y = vbslq_f64 (gt1, option_1, option_2);
160 /* Copy sign. */
161 y = vbslq_f64 (d->abs_mask, y, x);
162
163 if (unlikely (v_any_u64 (special)))
164 return special_case (x, y, special);
165 return y;
166 }
167
168 PL_SIG (V, D, 1, asinh, -10.0, 10.0)
169 PL_TEST_ULP (V_NAME_D1 (asinh), 2.80)
170 PL_TEST_EXPECT_FENV (V_NAME_D1 (asinh), WANT_SIMD_EXCEPT)
171 /* Test vector asinh 3 times, with control lane < 1, > 1 and special.
172 Ensures the v_sel is choosing the right option in all cases. */
173 #define V_ASINH_INTERVAL(lo, hi, n) \
174 PL_TEST_SYM_INTERVAL_C (V_NAME_D1 (asinh), lo, hi, n, 0.5) \
175 PL_TEST_SYM_INTERVAL_C (V_NAME_D1 (asinh), lo, hi, n, 2) \
176 PL_TEST_SYM_INTERVAL_C (V_NAME_D1 (asinh), lo, hi, n, 0x1p600)
177 V_ASINH_INTERVAL (0, 0x1p-26, 50000)
178 V_ASINH_INTERVAL (0x1p-26, 1, 50000)
179 V_ASINH_INTERVAL (1, 0x1p511, 50000)
180 V_ASINH_INTERVAL (0x1p511, inf, 40000)
181