xref: /aosp_15_r20/external/XNNPACK/src/qu8-gavgpool/gen/7x-minmax-rndnu-neon-c8.c (revision 4bdc94577ba0e567308109d787f7fec7b531ce36)
1 // Auto-generated file. Do not edit!
2 //   Template: src/qs8-gavgpool/unipass-neon.c.in
3 //   Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9 
10 #include <assert.h>
11 
12 #include <arm_neon.h>
13 
14 #include <xnnpack/gavgpool.h>
15 
16 
xnn_qu8_gavgpool_minmax_rndnu_ukernel_7x__neon_c8(size_t rows,size_t channels,const uint8_t * input,size_t input_stride,const uint8_t * zero,uint8_t * output,const union xnn_qu8_avgpool_minmax_params params[restrict XNN_MIN_ELEMENTS (1)])17 void xnn_qu8_gavgpool_minmax_rndnu_ukernel_7x__neon_c8(
18     size_t rows,
19     size_t channels,
20     const uint8_t* input,
21     size_t input_stride,
22     const uint8_t* zero,
23     uint8_t* output,
24     const union xnn_qu8_avgpool_minmax_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
25 {
26   assert(rows != 0);
27   assert(rows <= 7);
28   assert(channels != 0);
29 
30   const uint8_t* i0 = input;
31   const uint8_t* i1 = (const uint8_t*) ((uintptr_t) i0 + input_stride);
32   if XNN_UNPREDICTABLE(rows < 2) {
33     i1 = zero;
34   }
35   const uint8_t* i2 = (const uint8_t*) ((uintptr_t) i1 + input_stride);
36   if XNN_UNPREDICTABLE(rows <= 2) {
37     i2 = zero;
38   }
39   const uint8_t* i3 = (const uint8_t*) ((uintptr_t) i2 + input_stride);
40   if XNN_UNPREDICTABLE(rows < 4) {
41     i3 = zero;
42   }
43   const uint8_t* i4 = (const uint8_t*) ((uintptr_t) i3 + input_stride);
44   if XNN_UNPREDICTABLE(rows <= 4) {
45     i4 = zero;
46   }
47   const uint8_t* i5 = (const uint8_t*) ((uintptr_t) i4 + input_stride);
48   if XNN_UNPREDICTABLE(rows < 6) {
49     i5 = zero;
50   }
51   const uint8_t* i6 = (const uint8_t*) ((uintptr_t) i5 + input_stride);
52   if XNN_UNPREDICTABLE(rows <= 6) {
53     i6 = zero;
54   }
55 
56   const int32x4_t vinit_bias = vld1q_dup_s32(&params->rndnu_neon.init_bias);
57   const int32x4_t vleft_pre_shift = vld1q_dup_s32(&params->rndnu_neon.left_pre_shift);
58   const int32x4_t vmultiplier = vld1q_dup_s32(&params->rndnu_neon.multiplier);
59   const int32x4_t vleft_post_shift = vld1q_dup_s32(&params->rndnu_neon.left_post_shift);
60   const int16x8_t voutput_zero_point = vld1q_dup_s16(&params->rndnu_neon.output_zero_point);
61   const uint8x8_t voutput_min = vld1_dup_u8(&params->rndnu_neon.output_min);
62   const uint8x8_t voutput_max = vld1_dup_u8(&params->rndnu_neon.output_max);
63   for (; channels >= 8; channels -= 8) {
64     const uint8x8_t vi0x01234567 = vld1_u8(i0); i0 += 8;
65     const uint8x8_t vi1x01234567 = vld1_u8(i1); i1 += 8;
66 
67     const uint8x8_t vi2x01234567 = vld1_u8(i2); i2 += 8;
68     uint16x8_t vsum01234567 = vaddl_u8(vi0x01234567, vi1x01234567);
69 
70     const uint8x8_t vi3x01234567 = vld1_u8(i3); i3 += 8;
71     vsum01234567 = vaddw_u8(vsum01234567, vi2x01234567);
72     const uint8x8_t vi4x01234567 = vld1_u8(i4); i4 += 8;
73     vsum01234567 = vaddw_u8(vsum01234567, vi3x01234567);
74     const uint8x8_t vi5x01234567 = vld1_u8(i5); i5 += 8;
75     vsum01234567 = vaddw_u8(vsum01234567, vi4x01234567);
76     const uint8x8_t vi6x01234567 = vld1_u8(i6); i6 += 8;
77     vsum01234567 = vaddw_u8(vsum01234567, vi5x01234567);
78     vsum01234567 = vaddw_u8(vsum01234567, vi6x01234567);
79 
80     int32x4_t vacc0123 = vreinterpretq_s32_u32(vaddw_u16(vreinterpretq_u32_s32(vinit_bias), vget_low_u16(vsum01234567)));
81     int32x4_t vacc4567 = vreinterpretq_s32_u32(vaddw_u16(vreinterpretq_u32_s32(vinit_bias), vget_high_u16(vsum01234567)));
82 
83     vacc0123 = vqshlq_s32(vacc0123, vleft_pre_shift);
84     vacc4567 = vqshlq_s32(vacc4567, vleft_pre_shift);
85 
86     vacc0123 = vqdmulhq_s32(vacc0123, vmultiplier);
87     vacc4567 = vqdmulhq_s32(vacc4567, vmultiplier);
88 
89     vacc0123 = vrshlq_s32(vacc0123, vleft_post_shift);
90     vacc4567 = vrshlq_s32(vacc4567, vleft_post_shift);
91 
92     #if XNN_ARCH_ARM64
93       int16x8_t vacc01234567 = vqmovn_high_s32(vqmovn_s32(vacc0123), vacc4567);
94     #else  // !XNN_ARCH_ARM64
95       int16x8_t vacc01234567 = vcombine_s16(vqmovn_s32(vacc0123), vqmovn_s32(vacc4567));
96     #endif  // !XNN_ARCH_ARM64
97 
98     vacc01234567 = vqaddq_s16(vacc01234567, voutput_zero_point);
99 
100     #if XNN_ARCH_ARM64
101       uint8x8_t vout01234567 = vqmovun_s16(vacc01234567);
102     #else  // !XNN_ARCH_ARM64
103       uint8x8_t vout01234567 = vqmovun_s16(vacc01234567);
104     #endif  // !XNN_ARCH_ARM64
105 
106     vout01234567 = vmax_u8(vout01234567, voutput_min);
107 
108     vout01234567 = vmin_u8(vout01234567, voutput_max);
109 
110     vst1_u8(output, vout01234567); output += 8;
111   }
112   if XNN_UNLIKELY(channels != 0) {
113     {
114       const uint8x8_t vi0x01234567 = vld1_u8(i0); i0 += 8;
115       const uint8x8_t vi1x01234567 = vld1_u8(i1); i1 += 8;
116       const uint8x8_t vi2x01234567 = vld1_u8(i2); i2 += 8;
117       uint16x8_t vsum01234567 = vaddl_u8(vi0x01234567, vi1x01234567);
118 
119       const uint8x8_t vi3x01234567 = vld1_u8(i3); i3 += 8;
120       vsum01234567 = vaddw_u8(vsum01234567, vi2x01234567);
121       const uint8x8_t vi4x01234567 = vld1_u8(i4); i4 += 8;
122       vsum01234567 = vaddw_u8(vsum01234567, vi3x01234567);
123       const uint8x8_t vi5x01234567 = vld1_u8(i5); i5 += 8;
124       vsum01234567 = vaddw_u8(vsum01234567, vi4x01234567);
125       const uint8x8_t vi6x01234567 = vld1_u8(i6); i6 += 8;
126       vsum01234567 = vaddw_u8(vsum01234567, vi5x01234567);
127       vsum01234567 = vaddw_u8(vsum01234567, vi6x01234567);
128 
129       int32x4_t vacc0123 = vreinterpretq_s32_u32(vaddw_u16(vreinterpretq_u32_s32(vinit_bias), vget_low_u16(vsum01234567)));
130       int32x4_t vacc4567 = vreinterpretq_s32_u32(vaddw_u16(vreinterpretq_u32_s32(vinit_bias), vget_high_u16(vsum01234567)));
131 
132       vacc0123 = vqshlq_s32(vacc0123, vleft_pre_shift);
133       vacc4567 = vqshlq_s32(vacc4567, vleft_pre_shift);
134 
135       vacc0123 = vqdmulhq_s32(vacc0123, vmultiplier);
136       vacc4567 = vqdmulhq_s32(vacc4567, vmultiplier);
137 
138       vacc0123 = vrshlq_s32(vacc0123, vleft_post_shift);
139       vacc4567 = vrshlq_s32(vacc4567, vleft_post_shift);
140 
141       #if XNN_ARCH_ARM64
142         int16x8_t vacc01234567 = vqmovn_high_s32(vqmovn_s32(vacc0123), vacc4567);
143       #else
144         int16x8_t vacc01234567 = vcombine_s16(vqmovn_s32(vacc0123), vqmovn_s32(vacc4567));
145       #endif
146       vacc01234567 = vqaddq_s16(vacc01234567, voutput_zero_point);
147 
148       uint8x8_t vout01234567 = vqmovun_s16(vacc01234567);
149       vout01234567 = vmax_u8(vout01234567, voutput_min);
150       vout01234567 = vmin_u8(vout01234567, voutput_max);
151 
152       if (channels & 4) {
153         vst1_lane_u32((void*) output, vreinterpret_u32_u8(vout01234567), 0); output += 4;
154         vout01234567 = vext_u8(vout01234567, vout01234567, 4);
155       }
156       if (channels & 2) {
157         vst1_lane_u16((void*) output, vreinterpret_u16_u8(vout01234567), 0); output += 2;
158         vout01234567 = vext_u8(vout01234567, vout01234567, 2);
159       }
160       if (channels & 1) {
161         vst1_lane_u8(output, vout01234567, 0);
162       }
163     }
164   }
165 }
166