xref: /aosp_15_r20/external/XNNPACK/src/qs8-igemm/gen/3x8c4s2-minmax-rndnu-neon-mull.c (revision 4bdc94577ba0e567308109d787f7fec7b531ce36)
1 // Auto-generated file. Do not edit!
2 //   Template: src/qs8-igemm/c4-neon-mull-shuffle.c.in
3 //   Generator: tools/xngen
4 //
5 // Copyright 2021 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9 
10 #include <assert.h>
11 
12 #include <arm_neon.h>
13 
14 #include <xnnpack/gemm.h>
15 #include <xnnpack/math.h>
16 
17 
xnn_qs8_igemm_minmax_rndnu_ukernel_3x8c4s2__neon_mull(size_t mr,size_t nc,size_t kc,size_t ks,const int8_t ** restrict a,const void * restrict w,int8_t * restrict c,size_t cm_stride,size_t cn_stride,size_t a_offset,const int8_t * zero,const union xnn_qs8_conv_minmax_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_qs8_igemm_minmax_rndnu_ukernel_3x8c4s2__neon_mull(
19     size_t mr,
20     size_t nc,
21     size_t kc,
22     size_t ks,
23     const int8_t** restrict a,
24     const void* restrict w,
25     int8_t* restrict c,
26     size_t cm_stride,
27     size_t cn_stride,
28     size_t a_offset,
29     const int8_t* zero,
30     const union xnn_qs8_conv_minmax_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
31 {
32   assert(mr != 0);
33   assert(mr <= 3);
34   assert(nc != 0);
35   assert(kc != 0);
36   assert(ks != 0);
37   assert(ks % (3 * sizeof(void*)) == 0);
38   assert(a_offset % sizeof(int8_t) == 0);
39   assert(a != NULL);
40   assert(w != NULL);
41   assert(c != NULL);
42 
43   int8_t* c0 = c;
44   int8_t* c1 = (int8_t*) ((uintptr_t) c0 + cm_stride);
45   if XNN_UNPREDICTABLE(mr < 2) {
46     c1 = c0;
47   }
48   int8_t* c2 = (int8_t*) ((uintptr_t) c1 + cm_stride);
49   if XNN_UNPREDICTABLE(mr <= 2) {
50     c2 = c1;
51   }
52 
53   kc = round_up_po2(kc, 8 * sizeof(int8_t));
54   do {
55     int32x4_t vacc0x01 = vreinterpretq_s32_u64(vmovl_u32(vld1_u32(w))); w = (const int32_t*) w + 2;
56     int32x4_t vacc0x23 = vreinterpretq_s32_u64(vmovl_u32(vld1_u32(w))); w = (const int32_t*) w + 2;
57     int32x4_t vacc0x45 = vreinterpretq_s32_u64(vmovl_u32(vld1_u32(w))); w = (const int32_t*) w + 2;
58     int32x4_t vacc0x67 = vreinterpretq_s32_u64(vmovl_u32(vld1_u32(w))); w = (const int32_t*) w + 2;
59     int32x4_t vacc1x01 = vacc0x01;
60     int32x4_t vacc1x23 = vacc0x23;
61     int32x4_t vacc1x45 = vacc0x45;
62     int32x4_t vacc1x67 = vacc0x67;
63     int32x4_t vacc2x01 = vacc0x01;
64     int32x4_t vacc2x23 = vacc0x23;
65     int32x4_t vacc2x45 = vacc0x45;
66     int32x4_t vacc2x67 = vacc0x67;
67 
68     size_t p = ks;
69     do {
70       const int8_t* restrict a0 = a[0];
71       if XNN_UNPREDICTABLE(a0 != zero) {
72         a0 = (const int8_t*) ((uintptr_t) a0 + a_offset);
73       }
74       const int8_t* restrict a1 = a[1];
75       if XNN_UNPREDICTABLE(a1 != zero) {
76         a1 = (const int8_t*) ((uintptr_t) a1 + a_offset);
77       }
78       const int8_t* restrict a2 = a[2];
79       if XNN_UNPREDICTABLE(a2 != zero) {
80         a2 = (const int8_t*) ((uintptr_t) a2 + a_offset);
81       }
82       a += 3;
83 
84       size_t k = kc;
85       do {
86         int8x8_t va0x0 = vld1_s8(a0); a0 += 8;
87         int8x8_t va1x0 = vld1_s8(a1); a1 += 8;
88         int8x8_t va2x0 = vld1_s8(a2); a2 += 8;
89 
90         const int8x8_t vb01c0x0 = vld1_s8(w); w = (const int8_t*) w + 8;
91         const int8x8_t vb23c0x0 = vld1_s8(w); w = (const int8_t*) w + 8;
92         const int8x8_t vb45c0x0 = vld1_s8(w); w = (const int8_t*) w + 8;
93         const int8x8_t vb67c0x0 = vld1_s8(w); w = (const int8_t*) w + 8;
94         const int8x8_t vb01c1x0 = vld1_s8(w); w = (const int8_t*) w + 8;
95         const int8x8_t vb23c1x0 = vld1_s8(w); w = (const int8_t*) w + 8;
96         const int8x8_t vb45c1x0 = vld1_s8(w); w = (const int8_t*) w + 8;
97         const int8x8_t vb67c1x0 = vld1_s8(w); w = (const int8_t*) w + 8;
98 
99         int16x8_t vprod0x01c0 = vmull_s8(vb01c0x0, va0x0);
100         int16x8_t vprod1x01c0 = vmull_s8(vb01c0x0, va1x0);
101         int16x8_t vprod2x01c0 = vmull_s8(vb01c0x0, va2x0);
102         vacc0x01 = vpadalq_s16(vacc0x01, vprod0x01c0);
103         vacc1x01 = vpadalq_s16(vacc1x01, vprod1x01c0);
104         vacc2x01 = vpadalq_s16(vacc2x01, vprod2x01c0);
105         int16x8_t vprod0x23c0 = vmull_s8(vb23c0x0, va0x0);
106         int16x8_t vprod1x23c0 = vmull_s8(vb23c0x0, va1x0);
107         int16x8_t vprod2x23c0 = vmull_s8(vb23c0x0, va2x0);
108         vacc0x23 = vpadalq_s16(vacc0x23, vprod0x23c0);
109         vacc1x23 = vpadalq_s16(vacc1x23, vprod1x23c0);
110         vacc2x23 = vpadalq_s16(vacc2x23, vprod2x23c0);
111         int16x8_t vprod0x45c0 = vmull_s8(vb45c0x0, va0x0);
112         int16x8_t vprod1x45c0 = vmull_s8(vb45c0x0, va1x0);
113         int16x8_t vprod2x45c0 = vmull_s8(vb45c0x0, va2x0);
114         vacc0x45 = vpadalq_s16(vacc0x45, vprod0x45c0);
115         vacc1x45 = vpadalq_s16(vacc1x45, vprod1x45c0);
116         vacc2x45 = vpadalq_s16(vacc2x45, vprod2x45c0);
117         int16x8_t vprod0x67c0 = vmull_s8(vb67c0x0, va0x0);
118         int16x8_t vprod1x67c0 = vmull_s8(vb67c0x0, va1x0);
119         int16x8_t vprod2x67c0 = vmull_s8(vb67c0x0, va2x0);
120         vacc0x67 = vpadalq_s16(vacc0x67, vprod0x67c0);
121         vacc1x67 = vpadalq_s16(vacc1x67, vprod1x67c0);
122         vacc2x67 = vpadalq_s16(vacc2x67, vprod2x67c0);
123         va0x0 = vext_s8(va0x0, va0x0, 4);
124         va1x0 = vext_s8(va1x0, va1x0, 4);
125         va2x0 = vext_s8(va2x0, va2x0, 4);
126         int16x8_t vprod0x01c1 = vmull_s8(vb01c1x0, va0x0);
127         int16x8_t vprod1x01c1 = vmull_s8(vb01c1x0, va1x0);
128         int16x8_t vprod2x01c1 = vmull_s8(vb01c1x0, va2x0);
129         vacc0x01 = vpadalq_s16(vacc0x01, vprod0x01c1);
130         vacc1x01 = vpadalq_s16(vacc1x01, vprod1x01c1);
131         vacc2x01 = vpadalq_s16(vacc2x01, vprod2x01c1);
132         int16x8_t vprod0x23c1 = vmull_s8(vb23c1x0, va0x0);
133         int16x8_t vprod1x23c1 = vmull_s8(vb23c1x0, va1x0);
134         int16x8_t vprod2x23c1 = vmull_s8(vb23c1x0, va2x0);
135         vacc0x23 = vpadalq_s16(vacc0x23, vprod0x23c1);
136         vacc1x23 = vpadalq_s16(vacc1x23, vprod1x23c1);
137         vacc2x23 = vpadalq_s16(vacc2x23, vprod2x23c1);
138         int16x8_t vprod0x45c1 = vmull_s8(vb45c1x0, va0x0);
139         int16x8_t vprod1x45c1 = vmull_s8(vb45c1x0, va1x0);
140         int16x8_t vprod2x45c1 = vmull_s8(vb45c1x0, va2x0);
141         vacc0x45 = vpadalq_s16(vacc0x45, vprod0x45c1);
142         vacc1x45 = vpadalq_s16(vacc1x45, vprod1x45c1);
143         vacc2x45 = vpadalq_s16(vacc2x45, vprod2x45c1);
144         int16x8_t vprod0x67c1 = vmull_s8(vb67c1x0, va0x0);
145         int16x8_t vprod1x67c1 = vmull_s8(vb67c1x0, va1x0);
146         int16x8_t vprod2x67c1 = vmull_s8(vb67c1x0, va2x0);
147         vacc0x67 = vpadalq_s16(vacc0x67, vprod0x67c1);
148         vacc1x67 = vpadalq_s16(vacc1x67, vprod1x67c1);
149         vacc2x67 = vpadalq_s16(vacc2x67, vprod2x67c1);
150 
151         k -= 8 * sizeof(int8_t);
152       } while (k != 0);
153 
154       p -= 3 * sizeof(void*);
155     } while (p != 0);
156 
157 #if XNN_ARCH_ARM64
158     int32x4_t vacc0x0123 = vpaddq_s32(vacc0x01, vacc0x23);
159     int32x4_t vacc0x4567 = vpaddq_s32(vacc0x45, vacc0x67);
160     int32x4_t vacc1x0123 = vpaddq_s32(vacc1x01, vacc1x23);
161     int32x4_t vacc1x4567 = vpaddq_s32(vacc1x45, vacc1x67);
162     int32x4_t vacc2x0123 = vpaddq_s32(vacc2x01, vacc2x23);
163     int32x4_t vacc2x4567 = vpaddq_s32(vacc2x45, vacc2x67);
164 #else
165     const int32x2_t vsum0x01 = vpadd_s32(vget_low_s32(vacc0x01), vget_high_s32(vacc0x01));
166     const int32x2_t vsum0x23 = vpadd_s32(vget_low_s32(vacc0x23), vget_high_s32(vacc0x23));
167     int32x4_t vacc0x0123 = vcombine_s32(vsum0x01, vsum0x23);
168     const int32x2_t vsum0x45 = vpadd_s32(vget_low_s32(vacc0x45), vget_high_s32(vacc0x45));
169     const int32x2_t vsum0x67 = vpadd_s32(vget_low_s32(vacc0x67), vget_high_s32(vacc0x67));
170     int32x4_t vacc0x4567 = vcombine_s32(vsum0x45, vsum0x67);
171     const int32x2_t vsum1x01 = vpadd_s32(vget_low_s32(vacc1x01), vget_high_s32(vacc1x01));
172     const int32x2_t vsum1x23 = vpadd_s32(vget_low_s32(vacc1x23), vget_high_s32(vacc1x23));
173     int32x4_t vacc1x0123 = vcombine_s32(vsum1x01, vsum1x23);
174     const int32x2_t vsum1x45 = vpadd_s32(vget_low_s32(vacc1x45), vget_high_s32(vacc1x45));
175     const int32x2_t vsum1x67 = vpadd_s32(vget_low_s32(vacc1x67), vget_high_s32(vacc1x67));
176     int32x4_t vacc1x4567 = vcombine_s32(vsum1x45, vsum1x67);
177     const int32x2_t vsum2x01 = vpadd_s32(vget_low_s32(vacc2x01), vget_high_s32(vacc2x01));
178     const int32x2_t vsum2x23 = vpadd_s32(vget_low_s32(vacc2x23), vget_high_s32(vacc2x23));
179     int32x4_t vacc2x0123 = vcombine_s32(vsum2x01, vsum2x23);
180     const int32x2_t vsum2x45 = vpadd_s32(vget_low_s32(vacc2x45), vget_high_s32(vacc2x45));
181     const int32x2_t vsum2x67 = vpadd_s32(vget_low_s32(vacc2x67), vget_high_s32(vacc2x67));
182     int32x4_t vacc2x4567 = vcombine_s32(vsum2x45, vsum2x67);
183 #endif
184 
185     const int32x4_t vright_pre_shift = vld1q_dup_s32(&params->rndnu_neon.right_pre_shift);
186     const int32x4_t vmultiplier = vld1q_dup_s32(&params->rndnu_neon.multiplier);
187     const int32x4_t vright_post_shift = vld1q_dup_s32(&params->rndnu_neon.right_post_shift);
188 
189     vacc0x0123 = vqshlq_s32(vacc0x0123, vright_pre_shift);
190     vacc0x4567 = vqshlq_s32(vacc0x4567, vright_pre_shift);
191     vacc1x0123 = vqshlq_s32(vacc1x0123, vright_pre_shift);
192     vacc1x4567 = vqshlq_s32(vacc1x4567, vright_pre_shift);
193     vacc2x0123 = vqshlq_s32(vacc2x0123, vright_pre_shift);
194     vacc2x4567 = vqshlq_s32(vacc2x4567, vright_pre_shift);
195 
196     vacc0x0123 = vqdmulhq_s32(vacc0x0123, vmultiplier);
197     vacc0x4567 = vqdmulhq_s32(vacc0x4567, vmultiplier);
198     vacc1x0123 = vqdmulhq_s32(vacc1x0123, vmultiplier);
199     vacc1x4567 = vqdmulhq_s32(vacc1x4567, vmultiplier);
200     vacc2x0123 = vqdmulhq_s32(vacc2x0123, vmultiplier);
201     vacc2x4567 = vqdmulhq_s32(vacc2x4567, vmultiplier);
202 
203     vacc0x0123 = vrshlq_s32(vacc0x0123, vright_post_shift);
204     vacc0x4567 = vrshlq_s32(vacc0x4567, vright_post_shift);
205     vacc1x0123 = vrshlq_s32(vacc1x0123, vright_post_shift);
206     vacc1x4567 = vrshlq_s32(vacc1x4567, vright_post_shift);
207     vacc2x0123 = vrshlq_s32(vacc2x0123, vright_post_shift);
208     vacc2x4567 = vrshlq_s32(vacc2x4567, vright_post_shift);
209 
210     const int16x8_t voutput_zero_point = vld1q_dup_s16(&params->rndnu_neon.output_zero_point);
211 #if XNN_ARCH_ARM64
212     int16x8_t vacc0x01234567 = vqmovn_high_s32(vqmovn_s32(vacc0x0123), vacc0x4567);
213     int16x8_t vacc1x01234567 = vqmovn_high_s32(vqmovn_s32(vacc1x0123), vacc1x4567);
214     int16x8_t vacc2x01234567 = vqmovn_high_s32(vqmovn_s32(vacc2x0123), vacc2x4567);
215 
216     vacc0x01234567 = vqaddq_s16(vacc0x01234567, voutput_zero_point);
217     vacc1x01234567 = vqaddq_s16(vacc1x01234567, voutput_zero_point);
218     vacc2x01234567 = vqaddq_s16(vacc2x01234567, voutput_zero_point);
219 
220     int8x16_t vout0x01234567_1x01234567 = vqmovn_high_s16(vqmovn_s16(vacc0x01234567), vacc1x01234567);
221     int8x8_t vout2x01234567 = vqmovn_s16(vacc2x01234567);
222 #else
223     int16x8_t vacc0x01234567 = vcombine_s16(vqmovn_s32(vacc0x0123), vqmovn_s32(vacc0x4567));
224     int16x8_t vacc1x01234567 = vcombine_s16(vqmovn_s32(vacc1x0123), vqmovn_s32(vacc1x4567));
225     int16x8_t vacc2x01234567 = vcombine_s16(vqmovn_s32(vacc2x0123), vqmovn_s32(vacc2x4567));
226 
227     vacc0x01234567 = vqaddq_s16(vacc0x01234567, voutput_zero_point);
228     vacc1x01234567 = vqaddq_s16(vacc1x01234567, voutput_zero_point);
229     vacc2x01234567 = vqaddq_s16(vacc2x01234567, voutput_zero_point);
230 
231     int8x16_t vout0x01234567_1x01234567 = vcombine_s8(vqmovn_s16(vacc0x01234567), vqmovn_s16(vacc1x01234567));
232     int8x8_t vout2x01234567 = vqmovn_s16(vacc2x01234567);
233 #endif
234 
235     const int8x16_t voutput_min = vld1q_dup_s8(&params->rndnu_neon.output_min);
236     vout0x01234567_1x01234567 = vmaxq_s8(vout0x01234567_1x01234567, voutput_min);
237     vout2x01234567 = vmax_s8(vout2x01234567, vget_low_s8(voutput_min));
238 
239     const int8x16_t voutput_max = vld1q_dup_s8(&params->rndnu_neon.output_max);
240     vout0x01234567_1x01234567 = vminq_s8(vout0x01234567_1x01234567, voutput_max);
241     vout2x01234567 = vmin_s8(vout2x01234567, vget_low_s8(voutput_max));
242 
243     if (nc >= 8) {
244       vst1_s8(c2 + 0, vout2x01234567);
245       vst1_s8(c1 + 0, vget_high_s8(vout0x01234567_1x01234567));
246       vst1_s8(c0 + 0, vget_low_s8(vout0x01234567_1x01234567));
247 
248       c2 = (int8_t*) ((uintptr_t) c2 + cn_stride);
249       c1 = (int8_t*) ((uintptr_t) c1 + cn_stride);
250       c0 = (int8_t*) ((uintptr_t) c0 + cn_stride);
251 
252       a = (const int8_t**restrict) ((uintptr_t) a - ks);
253 
254       nc -= 8;
255     } else {
256       if (nc & 4) {
257         vst1_lane_u32((void*) c2, vreinterpret_u32_s8(vout2x01234567), 0); c2 += 4;
258         vst1q_lane_u32((void*) c1, vreinterpretq_u32_s8(vout0x01234567_1x01234567), 2); c1 += 4;
259         vst1q_lane_u32((void*) c0, vreinterpretq_u32_s8(vout0x01234567_1x01234567), 0); c0 += 4;
260         vout2x01234567 = vext_s8(vout2x01234567, vout2x01234567, 4);
261         vout0x01234567_1x01234567 = vextq_s8(vout0x01234567_1x01234567, vout0x01234567_1x01234567, 4);
262       }
263       if (nc & 2) {
264         vst1_lane_u16((void*) c2, vreinterpret_u16_s8(vout2x01234567), 0); c2 += 2;
265         vst1q_lane_u16((void*) c1, vreinterpretq_u16_s8(vout0x01234567_1x01234567), 4); c1 += 2;
266         vst1q_lane_u16((void*) c0, vreinterpretq_u16_s8(vout0x01234567_1x01234567), 0); c0 += 2;
267         vout2x01234567 = vext_s8(vout2x01234567, vout2x01234567, 2);
268         vout0x01234567_1x01234567 = vextq_s8(vout0x01234567_1x01234567, vout0x01234567_1x01234567, 2);
269       }
270       if (nc & 1) {
271         vst1_lane_s8(c2, vout2x01234567, 0);
272         vst1q_lane_s8(c1, vout0x01234567_1x01234567, 8);
273         vst1q_lane_s8(c0, vout0x01234567_1x01234567, 0);
274       }
275 
276       nc = 0;
277     }
278   } while (nc != 0);
279 }
280