1 /* 2 * Copyright (c) 2021 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_CL_DIRECT_CONV3D_KERNEL_H 25 #define ARM_COMPUTE_CL_DIRECT_CONV3D_KERNEL_H 26 27 #include "src/gpu/cl/IClKernel.h" 28 29 namespace arm_compute 30 { 31 class CLCompileContext; 32 struct Conv3dInfo; 33 34 namespace opencl 35 { 36 namespace kernels 37 { 38 /** Interface for the direct convolution 3d kernel. */ 39 class ClDirectConv3dKernel : public IClKernel 40 { 41 public: 42 /** Construtor */ 43 ClDirectConv3dKernel(); 44 /** Prevent instances of this class from being copied (As this class contains pointers) */ 45 ClDirectConv3dKernel(const ClDirectConv3dKernel &) = delete; 46 /** Prevent instances of this class from being copied (As this class contains pointers) */ 47 ClDirectConv3dKernel &operator=(const ClDirectConv3dKernel &) = delete; 48 /** Default move constructor */ 49 ClDirectConv3dKernel(ClDirectConv3dKernel &&) = default; 50 /** Default move assignment operator */ 51 ClDirectConv3dKernel &operator=(ClDirectConv3dKernel &&) = default; 52 /** Set the src, weights, biases and dst tensors info. 53 * 54 * Valid data layouts: 55 * - NDHWC 56 * 57 * Valid data type configurations: 58 * |src0 |src1 |src2 |dst | 59 * |:--------------|:--------------|:------|:--------------| 60 * |F16 |F16 |F16 |F16 | 61 * |F32 |F32 |F32 |F32 | 62 * |QASYMM8 |QASYMM8 |S32 |QASYMM8 | 63 * |QASYMM8_SIGNED |QASYMM8_SIGNED |S32 |QASYMM8_SIGNED | 64 * 65 * @param[in] compile_context The compile context to be used. 66 * @param[in] src0 Source tensor. 4 lower dimensions represent a single src [IFM, width, height, depth], 67 * while every optional dimension from 5 and above represent a batch of srcs. 68 * @param[in] src1 Weights tensor. Weights are 5D tensor with dimensions [OFM, IFM, kernel_w, kernel_h, kernel_d]. 69 * @param[in] src2 Biases tensor. Shared biases supported. Biases are 1D tensor with dimensions [OFM]. 70 * @param[out] dst Destination tensor. 4 lower dimensions represent a single dst [OFM, width, height, depth], while the rest represent batch of dsts. 71 * @param[in] conv3d_info Contains strides, padding, rounding, activation, dilation and fast math information. Activation and fast math are currently unused. 72 */ 73 void configure(const CLCompileContext &compile_context, const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, ITensorInfo *dst, const Conv3dInfo &conv3d_info); 74 /** Static function to check if given info will lead to a valid configuration 75 * 76 * Similar to ClDirectConv3dKernel::configure() 77 * 78 * @return a status 79 */ 80 static Status validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, const ITensorInfo *dst, const Conv3dInfo &conv3d_info); 81 82 // Inherited methods overridden: 83 void run_op(ITensorPack &tensors, const Window &window, cl::CommandQueue &queue) override; 84 }; 85 } // namespace kernels 86 } // namespace opencl 87 } // namespace arm_compute 88 #endif /* ARM_COMPUTE_CL_DIRECT_CONV3D_KERNEL_H */ 89