1 /* 2 * Copyright (c) 2021 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_CPU_GEMM_DIRECT_CONV_2D_H 25 #define ARM_COMPUTE_CPU_GEMM_DIRECT_CONV_2D_H 26 27 #include "arm_compute/core/TensorInfo.h" 28 #include "src/core/common/Macros.h" 29 #include "src/cpu/ICpuOperator.h" 30 #include "src/cpu/operators/CpuActivation.h" 31 #include "src/cpu/operators/CpuPermute.h" 32 #include "src/cpu/operators/internal/CpuGemmAssemblyDispatch.h" 33 34 namespace arm_compute 35 { 36 // Forward declarations 37 class ITensor; 38 struct Conv2dInfo; 39 namespace cpu 40 { 41 class CpuGemmDirectConv2d : public ICpuOperator 42 { 43 public: 44 CpuGemmDirectConv2d(); 45 ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuGemmDirectConv2d); 46 ~CpuGemmDirectConv2d(); 47 /** Set the input and output tensors. 48 * 49 * Valid data layouts: 50 * - All 51 * 52 * Valid data type configurations: 53 * |src0 |src1 |src2 |dst | 54 * |:--------------|:--------------|:--------------|:--------------| 55 * |QASYMM8 |QASYMM8 |S32 |QASYMM8 | 56 * |QASYMM8_SIGNED |QASYMM8_SIGNED |S32 |QASYMM8_SIGNED | 57 * |F16 |F16 |F16 |F16 | 58 * |F32 |F32 |F32 |F32 | 59 * |BFLOAT16 |BFLOAT16 |BFLOAT16 |BFLOAT16 | 60 * 61 * @param[in] src Source tensor info. 3 lower dimensions represent a single input [width, height, IFM], 62 * while every optional dimension from 4 and above represent a batch of inputs. 63 * Data types supported: QASYMM8/QASYMM8_SIGNED/BFLOAT16/F16/F32. 64 * @param[in] weights Weights tensor info. Weights are 4D tensor with dimensions [kernel_x, kernel_y, IFM, OFM]. 65 * Data type supported: QASYMM8/QASYMM8_SIGNED/QSYMM8_PER_CHANNEL/BFLOAT16/F16/F32. 66 * @param[in] biases Biases tensor info. Shared biases supported. Biases are 1D tensor with dimensions [OFM]. 67 * Data type supported: Should match @p input data type, except for input of QASYMM8/QASYMM8_SIGNED type where biases should be of S32 type. 68 * @param[in] dst Destination tensor info. 3 lower dimensions represent a single output [width, height, OFM], while the rest represent batch of outputs. 69 * Data types supported: Same as @p input. 70 * @param[in] info Contains padding and stride information described in @ref PadStrideInfo. 71 */ 72 void configure(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, ITensorInfo *dst, const Conv2dInfo &info); 73 /** Static function to check if given info will lead to a valid configuration of @ref CpuGemmDirectConv2d 74 * 75 * Similar to CpuGemmDirectConv2d::configure() 76 * 77 * @return a status 78 */ 79 static Status validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst, const Conv2dInfo &info); 80 81 // Inherited methods overridden: 82 void run(ITensorPack &tensors) override; 83 void prepare(ITensorPack &constants) override; 84 experimental::MemoryRequirements workspace() const override; 85 86 private: 87 enum AuxTensorIdx 88 { 89 AsmGemmWorkspace = 0, 90 Pretranspose, 91 PermutedWeights, 92 Count 93 }; 94 95 std::unique_ptr<CpuGemmAssemblyDispatch> _gemm_asm_func; 96 std::unique_ptr<CpuActivation> _activation_func; 97 std::unique_ptr<CpuPermute> _weights_permute_func; 98 experimental::MemoryRequirements _aux_mem; 99 TensorInfo _perm_weights; 100 bool _run_activation; 101 bool _is_prepared; 102 }; 103 } // namespace cpu 104 } // namespace arm_compute 105 106 #endif /* ARM_COMPUTE_CPU_GEMM_DIRECT_CONV_2D_H */ 107