1 /* 2 * Copyright (c) 2021-2022 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_CPU_CONCATENATE_H 25 #define ARM_COMPUTE_CPU_CONCATENATE_H 26 27 #include "src/cpu/ICpuKernel.h" 28 #include "src/cpu/ICpuOperator.h" 29 30 #include <vector> 31 32 namespace arm_compute 33 { 34 namespace cpu 35 { 36 /** Basic function to execute concatenate tensors along a given axis. This function calls the following kernels: 37 * 38 * -# @ref kernels::CpuConcatenateWidthKernel (if underlying concatenation axis is 0). 39 * -# @ref kernels::CpuConcatenateHeightKernel (if underlying concatenation axis is 1). 40 * -# @ref kernels::CpuConcatenateDepthKernel (if underlying concatenation axis is 2). 41 * -# @ref kernels::CpuConcatenateBatchKernel (if underlying concatenation axis is 3). 42 */ 43 class CpuConcatenate : public ICpuOperator 44 { 45 public: 46 CpuConcatenate() = default; 47 /** Configure operator for a given list of arguments 48 * 49 * @note Input and output tensor dimensions preconditions defer depending on the concatenation axis. 50 * @note Preconditions can be found respectively at @ref kernels::CpuConcatenateWidthKernel, @ref kernels::CpuConcatenateHeightKernel, 51 * @ref kernels::CpuConcatenateDepthKernel and @ref kernels::CpuConcatenateBatchKernel. 52 * 53 * @param[in,out] srcs_vector The vectors containing all the tensors to concatenate. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32. 54 * @param[out] dst Output tensor. Data types supported: Same as @p srcs_vector. 55 * @param[in] axis Concatenation axis. Supported underlying concatenation axis are 0, 1, 2 and 3. 56 */ 57 void configure(const std::vector<const ITensorInfo *> &srcs_vector, ITensorInfo *dst, size_t axis); 58 /** Static function to check if given info will lead to a valid configuration 59 * 60 * Similar to @ref CpuConcatenate::configure() 61 * 62 * @return a status 63 */ 64 static Status validate(const std::vector<const ITensorInfo *> &srcs_vector, const ITensorInfo *dst, size_t axis); 65 66 // Inherited methods overridden: 67 void run(ITensorPack &tensors) override; 68 69 private: 70 std::vector<std::unique_ptr<ICPPKernel>> _concat_kernels{}; 71 unsigned int _num_srcs{ 0 }; 72 unsigned int _axis{ 0 }; 73 }; 74 } // namespace cpu 75 } // namespace arm_compute 76 #endif /* ARM_COMPUTE_CPU_CONCATENATE_H */ 77