1 /* 2 * Copyright (c) 2019-2021 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_NEROIALIGNLAYER_H 25 #define ARM_COMPUTE_NEROIALIGNLAYER_H 26 27 #include "arm_compute/core/Types.h" 28 #include "arm_compute/runtime/NEON/INESimpleFunctionNoBorder.h" 29 30 namespace arm_compute 31 { 32 class ITensor; 33 class ITensorInfo; 34 35 /** Basic function to run @ref NEROIAlignLayerKernel. */ 36 class NEROIAlignLayer : public INESimpleFunctionNoBorder 37 { 38 public: 39 /** Set the input and output tensors. 40 * 41 * Valid data layouts: 42 * - All 43 * 44 * Valid data type configurations: 45 * |src0 |src1 |dst | 46 * |:--------------|:--------------|:--------------| 47 * |F16 |F16 |F16 | 48 * |F32 |F32 |F32 | 49 * |QASYMM8 |QASYMM16 |QASYMM8 | 50 * |QASYMM8_SIGNED |QASYMM16 |QASYMM8_SIGNED | 51 * 52 * @param[in] input Source tensor. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32. 53 * @param[in] rois ROIs tensor, it is a 2D tensor of size [5, N] (where N is the number of ROIs) containing top left and bottom right corner 54 * as coordinate of an image and batch_id of ROI [ batch_id, x1, y1, x2, y2 ]. 55 * Data types supported: QASYMM16 with scale of 0.125 and 0 offset if @p input is QASYMM8/QASYMM8_SIGNED, otherwise same as @p input 56 * @param[out] output Destination tensor. Data types supported: Same as @p input. 57 * @param[in] pool_info Contains pooling operation information described in @ref ROIPoolingLayerInfo. 58 * 59 * @note The x and y dimensions of @p output tensor must be the same as @p pool_info 's pooled 60 * width and pooled height. 61 * @note The z dimensions of @p output tensor and @p input tensor must be the same. 62 * @note The fourth dimension of @p output tensor must be the same as the number of elements in @p rois array. 63 */ 64 void configure(const ITensor *input, const ITensor *rois, ITensor *output, const ROIPoolingLayerInfo &pool_info); 65 /** Static function to check if given info will lead to a valid configuration of @ref NEROIAlignLayerKernel 66 * 67 * @param[in] input Source tensor info. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32. 68 * @param[in] rois ROIs tensor info. Data types supported: QASYMM16 with scale of 0.125 and 0 offset if @p input is QASYMM8/QASYMM8_SIGNED, 69 * otherwise same as @p input 70 * @param[in] output Destination tensor info. Data types supported: Same as @p input. 71 * @param[in] pool_info Contains pooling operation information described in @ref ROIPoolingLayerInfo. 72 * 73 * @note The x and y dimensions of @p output tensor must be the same as @p pool_info 's pooled 74 * width and pooled height. 75 * @note The z dimensions of @p output tensor and @p input tensor must be the same. 76 * @note The fourth dimension of @p output tensor must be the same as the number of elements in @p rois array. 77 * 78 * @return a Status 79 */ 80 static Status validate(const ITensorInfo *input, const ITensorInfo *rois, ITensorInfo *output, const ROIPoolingLayerInfo &pool_info); 81 }; 82 } // namespace arm_compute 83 #endif /* ARM_COMPUTE_NEROIALIGNLAYER_H */ 84