1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _UAPI__SOUND_EMU10K1_H 8 #define _UAPI__SOUND_EMU10K1_H 9 #ifdef __linux__ 10 #include <linux/types.h> 11 #endif 12 #define EMU10K1_FX8010_PCM_COUNT 8 13 #define __EMU10K1_DECLARE_BITMAP(name,bits) unsigned long name[(bits) / (sizeof(unsigned long) * 8)] 14 #define iMAC0 0x00 15 #define iMAC1 0x01 16 #define iMAC2 0x02 17 #define iMAC3 0x03 18 #define iMACINT0 0x04 19 #define iMACINT1 0x05 20 #define iACC3 0x06 21 #define iMACMV 0x07 22 #define iANDXOR 0x08 23 #define iTSTNEG 0x09 24 #define iLIMITGE 0x0a 25 #define iLIMITLT 0x0b 26 #define iLOG 0x0c 27 #define iEXP 0x0d 28 #define iINTERP 0x0e 29 #define iSKIP 0x0f 30 #define LOWORD_OPX_MASK 0x000ffc00 31 #define LOWORD_OPY_MASK 0x000003ff 32 #define HIWORD_OPCODE_MASK 0x00f00000 33 #define HIWORD_RESULT_MASK 0x000ffc00 34 #define HIWORD_OPA_MASK 0x000003ff 35 #define A_LOWORD_OPX_MASK 0x007ff000 36 #define A_LOWORD_OPY_MASK 0x000007ff 37 #define A_HIWORD_OPCODE_MASK 0x0f000000 38 #define A_HIWORD_RESULT_MASK 0x007ff000 39 #define A_HIWORD_OPA_MASK 0x000007ff 40 #define FXBUS(x) (0x00 + (x)) 41 #define EXTIN(x) (0x10 + (x)) 42 #define EXTOUT(x) (0x20 + (x)) 43 #define FXBUS2(x) (0x30 + (x)) 44 #define A_FXBUS(x) (0x00 + (x)) 45 #define A_EXTIN(x) (0x40 + (x)) 46 #define A_P16VIN(x) (0x50 + (x)) 47 #define A_EXTOUT(x) (0x60 + (x)) 48 #define A_FXBUS2(x) (0x80 + (x)) 49 #define A_EMU32OUTH(x) (0xa0 + (x)) 50 #define A_EMU32OUTL(x) (0xb0 + (x)) 51 #define A3_EMU32IN(x) (0x160 + (x)) 52 #define A3_EMU32OUT(x) (0x1E0 + (x)) 53 #define C_00000000 0x40 54 #define C_00000001 0x41 55 #define C_00000002 0x42 56 #define C_00000003 0x43 57 #define C_00000004 0x44 58 #define C_00000008 0x45 59 #define C_00000010 0x46 60 #define C_00000020 0x47 61 #define C_00000100 0x48 62 #define C_00010000 0x49 63 #define C_00080000 0x4a 64 #define C_10000000 0x4b 65 #define C_20000000 0x4c 66 #define C_40000000 0x4d 67 #define C_80000000 0x4e 68 #define C_7fffffff 0x4f 69 #define C_ffffffff 0x50 70 #define C_fffffffe 0x51 71 #define C_c0000000 0x52 72 #define C_4f1bbcdc 0x53 73 #define C_5a7ef9db 0x54 74 #define C_00100000 0x55 75 #define GPR_ACCU 0x56 76 #define GPR_COND 0x57 77 #define GPR_NOISE0 0x58 78 #define GPR_NOISE1 0x59 79 #define GPR_IRQ 0x5a 80 #define GPR_DBAC 0x5b 81 #define A_C_00000000 0xc0 82 #define A_C_00000001 0xc1 83 #define A_C_00000002 0xc2 84 #define A_C_00000003 0xc3 85 #define A_C_00000004 0xc4 86 #define A_C_00000008 0xc5 87 #define A_C_00000010 0xc6 88 #define A_C_00000020 0xc7 89 #define A_C_00000100 0xc8 90 #define A_C_00010000 0xc9 91 #define A_C_00000800 0xca 92 #define A_C_10000000 0xcb 93 #define A_C_20000000 0xcc 94 #define A_C_40000000 0xcd 95 #define A_C_80000000 0xce 96 #define A_C_7fffffff 0xcf 97 #define A_C_ffffffff 0xd0 98 #define A_C_fffffffe 0xd1 99 #define A_C_c0000000 0xd2 100 #define A_C_4f1bbcdc 0xd3 101 #define A_C_5a7ef9db 0xd4 102 #define A_C_00100000 0xd5 103 #define A_GPR_ACCU 0xd6 104 #define A_GPR_COND 0xd7 105 #define A_GPR_NOISE0 0xd8 106 #define A_GPR_NOISE1 0xd9 107 #define A_GPR_IRQ 0xda 108 #define A_GPR_DBAC 0xdb 109 #define A_GPR_DBACE 0xde 110 #define FXGPREGBASE 0x100 111 #define A_FXGPREGBASE 0x400 112 #define A_TANKMEMCTLREGBASE 0x100 113 #define A_TANKMEMCTLREG_MASK 0x1f 114 #define TANKMEMDATAREGBASE 0x200 115 #define TANKMEMDATAREG_MASK 0x000fffff 116 #define TANKMEMADDRREGBASE 0x300 117 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff 118 #define TANKMEMADDRREG_CLEAR 0x00800000 119 #define TANKMEMADDRREG_ALIGN 0x00400000 120 #define TANKMEMADDRREG_WRITE 0x00200000 121 #define TANKMEMADDRREG_READ 0x00100000 122 #define GPR(x) (FXGPREGBASE + (x)) 123 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) 124 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) 125 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) 126 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) 127 #define A_GPR(x) (A_FXGPREGBASE + (x)) 128 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) 129 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) 130 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) 131 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) 132 #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) 133 #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) 134 #define CC_REG_NORMALIZED C_00000001 135 #define CC_REG_BORROW C_00000002 136 #define CC_REG_MINUS C_00000004 137 #define CC_REG_ZERO C_00000008 138 #define CC_REG_SATURATE C_00000010 139 #define CC_REG_NONZERO C_00000100 140 #define A_CC_REG_NORMALIZED A_C_00000001 141 #define A_CC_REG_BORROW A_C_00000002 142 #define A_CC_REG_MINUS A_C_00000004 143 #define A_CC_REG_ZERO A_C_00000008 144 #define A_CC_REG_SATURATE A_C_00000010 145 #define A_CC_REG_NONZERO A_C_00000100 146 #define FXBUS_PCM_LEFT 0x00 147 #define FXBUS_PCM_RIGHT 0x01 148 #define FXBUS_PCM_LEFT_REAR 0x02 149 #define FXBUS_PCM_RIGHT_REAR 0x03 150 #define FXBUS_MIDI_LEFT 0x04 151 #define FXBUS_MIDI_RIGHT 0x05 152 #define FXBUS_PCM_CENTER 0x06 153 #define FXBUS_PCM_LFE 0x07 154 #define FXBUS_PCM_LEFT_FRONT 0x08 155 #define FXBUS_PCM_RIGHT_FRONT 0x09 156 #define FXBUS_MIDI_REVERB 0x0c 157 #define FXBUS_MIDI_CHORUS 0x0d 158 #define FXBUS_PCM_LEFT_SIDE 0x0e 159 #define FXBUS_PCM_RIGHT_SIDE 0x0f 160 #define FXBUS_PT_LEFT 0x14 161 #define FXBUS_PT_RIGHT 0x15 162 #define EXTIN_AC97_L 0x00 163 #define EXTIN_AC97_R 0x01 164 #define EXTIN_SPDIF_CD_L 0x02 165 #define EXTIN_SPDIF_CD_R 0x03 166 #define EXTIN_ZOOM_L 0x04 167 #define EXTIN_ZOOM_R 0x05 168 #define EXTIN_TOSLINK_L 0x06 169 #define EXTIN_TOSLINK_R 0x07 170 #define EXTIN_LINE1_L 0x08 171 #define EXTIN_LINE1_R 0x09 172 #define EXTIN_COAX_SPDIF_L 0x0a 173 #define EXTIN_COAX_SPDIF_R 0x0b 174 #define EXTIN_LINE2_L 0x0c 175 #define EXTIN_LINE2_R 0x0d 176 #define EXTOUT_AC97_L 0x00 177 #define EXTOUT_AC97_R 0x01 178 #define EXTOUT_TOSLINK_L 0x02 179 #define EXTOUT_TOSLINK_R 0x03 180 #define EXTOUT_AC97_CENTER 0x04 181 #define EXTOUT_AC97_LFE 0x05 182 #define EXTOUT_HEADPHONE_L 0x06 183 #define EXTOUT_HEADPHONE_R 0x07 184 #define EXTOUT_REAR_L 0x08 185 #define EXTOUT_REAR_R 0x09 186 #define EXTOUT_ADC_CAP_L 0x0a 187 #define EXTOUT_ADC_CAP_R 0x0b 188 #define EXTOUT_MIC_CAP 0x0c 189 #define EXTOUT_AC97_REAR_L 0x0d 190 #define EXTOUT_AC97_REAR_R 0x0e 191 #define EXTOUT_ACENTER 0x11 192 #define EXTOUT_ALFE 0x12 193 #define A_EXTIN_AC97_L 0x00 194 #define A_EXTIN_AC97_R 0x01 195 #define A_EXTIN_SPDIF_CD_L 0x02 196 #define A_EXTIN_SPDIF_CD_R 0x03 197 #define A_EXTIN_OPT_SPDIF_L 0x04 198 #define A_EXTIN_OPT_SPDIF_R 0x05 199 #define A_EXTIN_LINE2_L 0x08 200 #define A_EXTIN_LINE2_R 0x09 201 #define A_EXTIN_ADC_L 0x0a 202 #define A_EXTIN_ADC_R 0x0b 203 #define A_EXTIN_AUX2_L 0x0c 204 #define A_EXTIN_AUX2_R 0x0d 205 #define A_EXTOUT_FRONT_L 0x00 206 #define A_EXTOUT_FRONT_R 0x01 207 #define A_EXTOUT_CENTER 0x02 208 #define A_EXTOUT_LFE 0x03 209 #define A_EXTOUT_HEADPHONE_L 0x04 210 #define A_EXTOUT_HEADPHONE_R 0x05 211 #define A_EXTOUT_REAR_L 0x06 212 #define A_EXTOUT_REAR_R 0x07 213 #define A_EXTOUT_AFRONT_L 0x08 214 #define A_EXTOUT_AFRONT_R 0x09 215 #define A_EXTOUT_ACENTER 0x0a 216 #define A_EXTOUT_ALFE 0x0b 217 #define A_EXTOUT_ASIDE_L 0x0c 218 #define A_EXTOUT_ASIDE_R 0x0d 219 #define A_EXTOUT_AREAR_L 0x0e 220 #define A_EXTOUT_AREAR_R 0x0f 221 #define A_EXTOUT_AC97_L 0x10 222 #define A_EXTOUT_AC97_R 0x11 223 #define A_EXTOUT_ADC_CAP_L 0x16 224 #define A_EXTOUT_ADC_CAP_R 0x17 225 #define A_EXTOUT_MIC_CAP 0x18 226 #define EMU10K1_DBG_ZC 0x80000000 227 #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 228 #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 229 #define EMU10K1_DBG_SINGLE_STEP 0x00008000 230 #define EMU10K1_DBG_STEP 0x00004000 231 #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 232 #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff 233 #define A_DBG_ZC 0x40000000 234 #define A_DBG_SATURATION_OCCURED 0x20000000 235 #define A_DBG_SATURATION_ADDR 0x0ffc0000 236 #define A_DBG_SINGLE_STEP 0x00020000 237 #define A_DBG_STEP 0x00010000 238 #define A_DBG_CONDITION_CODE 0x0000f800 239 #define A_DBG_STEP_ADDR 0x000003ff 240 struct snd_emu10k1_fx8010_info { 241 unsigned int internal_tram_size; 242 unsigned int external_tram_size; 243 char fxbus_names[16][32]; 244 char extin_names[16][32]; 245 char extout_names[32][32]; 246 unsigned int gpr_controls; 247 }; 248 #define EMU10K1_GPR_TRANSLATION_NONE 0 249 #define EMU10K1_GPR_TRANSLATION_TABLE100 1 250 #define EMU10K1_GPR_TRANSLATION_BASS 2 251 #define EMU10K1_GPR_TRANSLATION_TREBLE 3 252 #define EMU10K1_GPR_TRANSLATION_ONOFF 4 253 #define EMU10K1_GPR_TRANSLATION_NEGATE 5 254 #define EMU10K1_GPR_TRANSLATION_NEG_TABLE100 6 255 enum emu10k1_ctl_elem_iface { 256 EMU10K1_CTL_ELEM_IFACE_MIXER = 2, 257 EMU10K1_CTL_ELEM_IFACE_PCM = 3, 258 }; 259 struct emu10k1_ctl_elem_id { 260 unsigned int pad; 261 int iface; 262 unsigned int device; 263 unsigned int subdevice; 264 unsigned char name[44]; 265 unsigned int index; 266 }; 267 struct snd_emu10k1_fx8010_control_gpr { 268 struct emu10k1_ctl_elem_id id; 269 unsigned int vcount; 270 unsigned int count; 271 unsigned short gpr[32]; 272 int value[32]; 273 int min; 274 int max; 275 unsigned int translation; 276 const unsigned int * tlv; 277 }; 278 struct snd_emu10k1_fx8010_control_old_gpr { 279 struct emu10k1_ctl_elem_id id; 280 unsigned int vcount; 281 unsigned int count; 282 unsigned short gpr[32]; 283 unsigned int value[32]; 284 unsigned int min; 285 unsigned int max; 286 unsigned int translation; 287 }; 288 struct snd_emu10k1_fx8010_code { 289 char name[128]; 290 __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200); 291 __u32 * gpr_map; 292 unsigned int gpr_add_control_count; 293 struct snd_emu10k1_fx8010_control_gpr * gpr_add_controls; 294 unsigned int gpr_del_control_count; 295 struct emu10k1_ctl_elem_id * gpr_del_controls; 296 unsigned int gpr_list_control_count; 297 unsigned int gpr_list_control_total; 298 struct snd_emu10k1_fx8010_control_gpr * gpr_list_controls; 299 __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100); 300 __u32 * tram_data_map; 301 __u32 * tram_addr_map; 302 __EMU10K1_DECLARE_BITMAP(code_valid, 1024); 303 __u32 * code; 304 }; 305 struct snd_emu10k1_fx8010_tram { 306 unsigned int address; 307 unsigned int size; 308 unsigned int * samples; 309 }; 310 struct snd_emu10k1_fx8010_pcm_rec { 311 unsigned int substream; 312 unsigned int res1; 313 unsigned int channels; 314 unsigned int tram_start; 315 unsigned int buffer_size; 316 unsigned short gpr_size; 317 unsigned short gpr_ptr; 318 unsigned short gpr_count; 319 unsigned short gpr_tmpcount; 320 unsigned short gpr_trigger; 321 unsigned short gpr_running; 322 unsigned char pad; 323 unsigned char etram[32]; 324 unsigned int res2; 325 }; 326 #define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) 327 #define SNDRV_EMU10K1_IOCTL_INFO _IOR('H', 0x10, struct snd_emu10k1_fx8010_info) 328 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW('H', 0x11, struct snd_emu10k1_fx8010_code) 329 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code) 330 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW('H', 0x20, int) 331 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW('H', 0x21, struct snd_emu10k1_fx8010_tram) 332 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram) 333 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec) 334 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec) 335 #define SNDRV_EMU10K1_IOCTL_PVERSION _IOR('H', 0x40, int) 336 #define SNDRV_EMU10K1_IOCTL_STOP _IO('H', 0x80) 337 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO('H', 0x81) 338 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO('H', 0x82) 339 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW('H', 0x83, int) 340 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR('H', 0x84, int) 341 #endif 342