1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _UAPI__LINUX_MDIO_H__ 8 #define _UAPI__LINUX_MDIO_H__ 9 #include <linux/types.h> 10 #include <linux/mii.h> 11 #define MDIO_MMD_PMAPMD 1 12 #define MDIO_MMD_WIS 2 13 #define MDIO_MMD_PCS 3 14 #define MDIO_MMD_PHYXS 4 15 #define MDIO_MMD_DTEXS 5 16 #define MDIO_MMD_TC 6 17 #define MDIO_MMD_AN 7 18 #define MDIO_MMD_C22EXT 29 19 #define MDIO_MMD_VEND1 30 20 #define MDIO_MMD_VEND2 31 21 #define MDIO_CTRL1 MII_BMCR 22 #define MDIO_STAT1 MII_BMSR 23 #define MDIO_DEVID1 MII_PHYSID1 24 #define MDIO_DEVID2 MII_PHYSID2 25 #define MDIO_SPEED 4 26 #define MDIO_DEVS1 5 27 #define MDIO_DEVS2 6 28 #define MDIO_CTRL2 7 29 #define MDIO_STAT2 8 30 #define MDIO_PMA_TXDIS 9 31 #define MDIO_PMA_RXDET 10 32 #define MDIO_PMA_EXTABLE 11 33 #define MDIO_PKGID1 14 34 #define MDIO_PKGID2 15 35 #define MDIO_AN_ADVERTISE 16 36 #define MDIO_AN_LPA 19 37 #define MDIO_PCS_EEE_ABLE 20 38 #define MDIO_PCS_EEE_ABLE2 21 39 #define MDIO_PMA_NG_EXTABLE 21 40 #define MDIO_PCS_EEE_WK_ERR 22 41 #define MDIO_PHYXS_LNSTAT 24 42 #define MDIO_AN_EEE_ADV 60 43 #define MDIO_AN_EEE_LPABLE 61 44 #define MDIO_AN_EEE_ADV2 62 45 #define MDIO_AN_EEE_LPABLE2 63 46 #define MDIO_AN_CTRL2 64 47 #define MDIO_PMA_10GBT_SWAPPOL 130 48 #define MDIO_PMA_10GBT_TXPWR 131 49 #define MDIO_PMA_10GBT_SNR 133 50 #define MDIO_PMA_10GBR_FSRT_CSR 147 51 #define MDIO_PMA_10GBR_FECABLE 170 52 #define MDIO_PCS_10GBX_STAT1 24 53 #define MDIO_PCS_10GBRT_STAT1 32 54 #define MDIO_PCS_10GBRT_STAT2 33 55 #define MDIO_AN_10GBT_CTRL 32 56 #define MDIO_AN_10GBT_STAT 33 57 #define MDIO_B10L_PMA_CTRL 2294 58 #define MDIO_PMA_10T1L_STAT 2295 59 #define MDIO_PCS_10T1L_CTRL 2278 60 #define MDIO_PMA_PMD_BT1 18 61 #define MDIO_AN_T1_CTRL 512 62 #define MDIO_AN_T1_STAT 513 63 #define MDIO_AN_T1_ADV_L 514 64 #define MDIO_AN_T1_ADV_M 515 65 #define MDIO_AN_T1_ADV_H 516 66 #define MDIO_AN_T1_LP_L 517 67 #define MDIO_AN_T1_LP_M 518 68 #define MDIO_AN_T1_LP_H 519 69 #define MDIO_AN_10BT1_AN_CTRL 526 70 #define MDIO_AN_10BT1_AN_STAT 527 71 #define MDIO_PMA_PMD_BT1_CTRL 2100 72 #define MDIO_PCS_1000BT1_CTRL 2304 73 #define MDIO_PCS_1000BT1_STAT 2305 74 #define MDIO_PMA_LASI_RXCTRL 0x9000 75 #define MDIO_PMA_LASI_TXCTRL 0x9001 76 #define MDIO_PMA_LASI_CTRL 0x9002 77 #define MDIO_PMA_LASI_RXSTAT 0x9003 78 #define MDIO_PMA_LASI_TXSTAT 0x9004 79 #define MDIO_PMA_LASI_STAT 0x9005 80 #define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100) 81 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c) 82 #define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX 83 #define MDIO_CTRL1_LPOWER BMCR_PDOWN 84 #define MDIO_CTRL1_RESET BMCR_RESET 85 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001 86 #define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000 87 #define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100 88 #define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK 89 #define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK 90 #define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART 91 #define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE 92 #define MDIO_AN_CTRL1_XNP 0x2000 93 #define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 94 #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) 95 #define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) 96 #define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18) 97 #define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c) 98 #define MDIO_STAT1_LPOWERABLE 0x0002 99 #define MDIO_STAT1_LSTATUS BMSR_LSTATUS 100 #define MDIO_STAT1_FAULT 0x0080 101 #define MDIO_AN_STAT1_LPABLE 0x0001 102 #define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE 103 #define MDIO_AN_STAT1_RFAULT BMSR_RFAULT 104 #define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE 105 #define MDIO_AN_STAT1_PAGE 0x0040 106 #define MDIO_AN_STAT1_XNP 0x0080 107 #define MDIO_SPEED_10G 0x0001 108 #define MDIO_PMA_SPEED_2B 0x0002 109 #define MDIO_PMA_SPEED_10P 0x0004 110 #define MDIO_PMA_SPEED_1000 0x0010 111 #define MDIO_PMA_SPEED_100 0x0020 112 #define MDIO_PMA_SPEED_10 0x0040 113 #define MDIO_PMA_SPEED_2_5G 0x2000 114 #define MDIO_PMA_SPEED_5G 0x4000 115 #define MDIO_PCS_SPEED_10P2B 0x0002 116 #define MDIO_PCS_SPEED_2_5G 0x0040 117 #define MDIO_PCS_SPEED_5G 0x0080 118 #define MDIO_DEVS_PRESENT(devad) (1 << (devad)) 119 #define MDIO_DEVS_C22PRESENT MDIO_DEVS_PRESENT(0) 120 #define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD) 121 #define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS) 122 #define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS) 123 #define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS) 124 #define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS) 125 #define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC) 126 #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN) 127 #define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT) 128 #define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1) 129 #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2) 130 #define MDIO_PMA_CTRL2_TYPE 0x000f 131 #define MDIO_PMA_CTRL2_10GBCX4 0x0000 132 #define MDIO_PMA_CTRL2_10GBEW 0x0001 133 #define MDIO_PMA_CTRL2_10GBLW 0x0002 134 #define MDIO_PMA_CTRL2_10GBSW 0x0003 135 #define MDIO_PMA_CTRL2_10GBLX4 0x0004 136 #define MDIO_PMA_CTRL2_10GBER 0x0005 137 #define MDIO_PMA_CTRL2_10GBLR 0x0006 138 #define MDIO_PMA_CTRL2_10GBSR 0x0007 139 #define MDIO_PMA_CTRL2_10GBLRM 0x0008 140 #define MDIO_PMA_CTRL2_10GBT 0x0009 141 #define MDIO_PMA_CTRL2_10GBKX4 0x000a 142 #define MDIO_PMA_CTRL2_10GBKR 0x000b 143 #define MDIO_PMA_CTRL2_1000BT 0x000c 144 #define MDIO_PMA_CTRL2_1000BKX 0x000d 145 #define MDIO_PMA_CTRL2_100BTX 0x000e 146 #define MDIO_PMA_CTRL2_10BT 0x000f 147 #define MDIO_PMA_CTRL2_2_5GBT 0x0030 148 #define MDIO_PMA_CTRL2_5GBT 0x0031 149 #define MDIO_PMA_CTRL2_BASET1 0x003D 150 #define MDIO_PCS_CTRL2_TYPE 0x0003 151 #define MDIO_PCS_CTRL2_10GBR 0x0000 152 #define MDIO_PCS_CTRL2_10GBX 0x0001 153 #define MDIO_PCS_CTRL2_10GBW 0x0002 154 #define MDIO_PCS_CTRL2_10GBT 0x0003 155 #define MDIO_STAT2_RXFAULT 0x0400 156 #define MDIO_STAT2_TXFAULT 0x0800 157 #define MDIO_STAT2_DEVPRST 0xc000 158 #define MDIO_STAT2_DEVPRST_VAL 0x8000 159 #define MDIO_PMA_STAT2_LBABLE 0x0001 160 #define MDIO_PMA_STAT2_10GBEW 0x0002 161 #define MDIO_PMA_STAT2_10GBLW 0x0004 162 #define MDIO_PMA_STAT2_10GBSW 0x0008 163 #define MDIO_PMA_STAT2_10GBLX4 0x0010 164 #define MDIO_PMA_STAT2_10GBER 0x0020 165 #define MDIO_PMA_STAT2_10GBLR 0x0040 166 #define MDIO_PMA_STAT2_10GBSR 0x0080 167 #define MDIO_PMD_STAT2_TXDISAB 0x0100 168 #define MDIO_PMA_STAT2_EXTABLE 0x0200 169 #define MDIO_PMA_STAT2_RXFLTABLE 0x1000 170 #define MDIO_PMA_STAT2_TXFLTABLE 0x2000 171 #define MDIO_PCS_STAT2_10GBR 0x0001 172 #define MDIO_PCS_STAT2_10GBX 0x0002 173 #define MDIO_PCS_STAT2_10GBW 0x0004 174 #define MDIO_PCS_STAT2_RXFLTABLE 0x1000 175 #define MDIO_PCS_STAT2_TXFLTABLE 0x2000 176 #define MDIO_PMD_TXDIS_GLOBAL 0x0001 177 #define MDIO_PMD_TXDIS_0 0x0002 178 #define MDIO_PMD_TXDIS_1 0x0004 179 #define MDIO_PMD_TXDIS_2 0x0008 180 #define MDIO_PMD_TXDIS_3 0x0010 181 #define MDIO_PMD_RXDET_GLOBAL 0x0001 182 #define MDIO_PMD_RXDET_0 0x0002 183 #define MDIO_PMD_RXDET_1 0x0004 184 #define MDIO_PMD_RXDET_2 0x0008 185 #define MDIO_PMD_RXDET_3 0x0010 186 #define MDIO_PMA_EXTABLE_10GCX4 0x0001 187 #define MDIO_PMA_EXTABLE_10GBLRM 0x0002 188 #define MDIO_PMA_EXTABLE_10GBT 0x0004 189 #define MDIO_PMA_EXTABLE_10GBKX4 0x0008 190 #define MDIO_PMA_EXTABLE_10GBKR 0x0010 191 #define MDIO_PMA_EXTABLE_1000BT 0x0020 192 #define MDIO_PMA_EXTABLE_1000BKX 0x0040 193 #define MDIO_PMA_EXTABLE_100BTX 0x0080 194 #define MDIO_PMA_EXTABLE_10BT 0x0100 195 #define MDIO_PMA_EXTABLE_BT1 0x0800 196 #define MDIO_PMA_EXTABLE_NBT 0x4000 197 #define MDIO_AN_C73_0_S_MASK GENMASK(4, 0) 198 #define MDIO_AN_C73_0_E_MASK GENMASK(9, 5) 199 #define MDIO_AN_C73_0_PAUSE BIT(10) 200 #define MDIO_AN_C73_0_ASM_DIR BIT(11) 201 #define MDIO_AN_C73_0_C2 BIT(12) 202 #define MDIO_AN_C73_0_RF BIT(13) 203 #define MDIO_AN_C73_0_ACK BIT(14) 204 #define MDIO_AN_C73_0_NP BIT(15) 205 #define MDIO_AN_C73_1_T_MASK GENMASK(4, 0) 206 #define MDIO_AN_C73_1_1000BASE_KX BIT(5) 207 #define MDIO_AN_C73_1_10GBASE_KX4 BIT(6) 208 #define MDIO_AN_C73_1_10GBASE_KR BIT(7) 209 #define MDIO_AN_C73_1_40GBASE_KR4 BIT(8) 210 #define MDIO_AN_C73_1_40GBASE_CR4 BIT(9) 211 #define MDIO_AN_C73_1_100GBASE_CR10 BIT(10) 212 #define MDIO_AN_C73_1_100GBASE_KP4 BIT(11) 213 #define MDIO_AN_C73_1_100GBASE_KR4 BIT(12) 214 #define MDIO_AN_C73_1_100GBASE_CR4 BIT(13) 215 #define MDIO_AN_C73_1_25GBASE_R_S BIT(14) 216 #define MDIO_AN_C73_1_25GBASE_R BIT(15) 217 #define MDIO_AN_C73_2_2500BASE_KX BIT(0) 218 #define MDIO_AN_C73_2_5GBASE_KR BIT(1) 219 #define MDIO_PHYXS_LNSTAT_SYNC0 0x0001 220 #define MDIO_PHYXS_LNSTAT_SYNC1 0x0002 221 #define MDIO_PHYXS_LNSTAT_SYNC2 0x0004 222 #define MDIO_PHYXS_LNSTAT_SYNC3 0x0008 223 #define MDIO_PHYXS_LNSTAT_ALIGN 0x1000 224 #define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 225 #define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 226 #define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 227 #define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 228 #define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 229 #define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 230 #define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 231 #define MDIO_PMA_10GBT_SNR_BIAS 0x8000 232 #define MDIO_PMA_10GBT_SNR_MAX 127 233 #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 234 #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 235 #define MDIO_PMA_10GBR_FSRT_ENABLE 0x0001 236 #define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 237 #define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff 238 #define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 239 #define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G 0x0020 240 #define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 241 #define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 242 #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 243 #define MDIO_AN_10GBT_STAT_LP2_5G 0x0020 244 #define MDIO_AN_10GBT_STAT_LP5G 0x0040 245 #define MDIO_AN_10GBT_STAT_LPTRR 0x0200 246 #define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 247 #define MDIO_AN_10GBT_STAT_LP10G 0x0800 248 #define MDIO_AN_10GBT_STAT_REMOK 0x1000 249 #define MDIO_AN_10GBT_STAT_LOCOK 0x2000 250 #define MDIO_AN_10GBT_STAT_MS 0x4000 251 #define MDIO_AN_10GBT_STAT_MSFLT 0x8000 252 #define MDIO_PMA_10T1L_CTRL_LB_EN 0x0001 253 #define MDIO_PMA_10T1L_CTRL_EEE_EN 0x0400 254 #define MDIO_PMA_10T1L_CTRL_LOW_POWER 0x0800 255 #define MDIO_PMA_10T1L_CTRL_2V4_EN 0x1000 256 #define MDIO_PMA_10T1L_CTRL_TX_DIS 0x4000 257 #define MDIO_PMA_10T1L_CTRL_PMA_RST 0x8000 258 #define MDIO_PMA_10T1L_STAT_LINK 0x0001 259 #define MDIO_PMA_10T1L_STAT_FAULT 0x0002 260 #define MDIO_PMA_10T1L_STAT_POLARITY 0x0004 261 #define MDIO_PMA_10T1L_STAT_RECV_FAULT 0x0200 262 #define MDIO_PMA_10T1L_STAT_EEE 0x0400 263 #define MDIO_PMA_10T1L_STAT_LOW_POWER 0x0800 264 #define MDIO_PMA_10T1L_STAT_2V4_ABLE 0x1000 265 #define MDIO_PMA_10T1L_STAT_LB_ABLE 0x2000 266 #define MDIO_PCS_10T1L_CTRL_LB 0x4000 267 #define MDIO_PCS_10T1L_CTRL_RESET 0x8000 268 #define MDIO_PMA_PMD_BT1_B100_ABLE 0x0001 269 #define MDIO_PMA_PMD_BT1_B1000_ABLE 0x0002 270 #define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004 271 #define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP 272 #define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM 273 #define MDIO_AN_T1_ADV_L_FORCE_MS 0x1000 274 #define MDIO_AN_T1_ADV_L_REMOTE_FAULT ADVERTISE_RFAULT 275 #define MDIO_AN_T1_ADV_L_ACK ADVERTISE_LPACK 276 #define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ ADVERTISE_NPAGE 277 #define MDIO_AN_T1_ADV_M_B10L 0x4000 278 #define MDIO_AN_T1_ADV_M_1000BT1 0x0080 279 #define MDIO_AN_T1_ADV_M_100BT1 0x0020 280 #define MDIO_AN_T1_ADV_M_MST 0x0010 281 #define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000 282 #define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000 283 #define MDIO_AN_T1_LP_L_PAUSE_CAP LPA_PAUSE_CAP 284 #define MDIO_AN_T1_LP_L_PAUSE_ASYM LPA_PAUSE_ASYM 285 #define MDIO_AN_T1_LP_L_FORCE_MS 0x1000 286 #define MDIO_AN_T1_LP_L_REMOTE_FAULT LPA_RFAULT 287 #define MDIO_AN_T1_LP_L_ACK LPA_LPACK 288 #define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ LPA_NPAGE 289 #define MDIO_AN_T1_LP_M_MST 0x0010 290 #define MDIO_AN_T1_LP_M_B10L 0x4000 291 #define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 292 #define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 293 #define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L 0x4000 294 #define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000 295 #define MDIO_PMA_PMD_BT1_CTRL_STRAP 0x000F 296 #define MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000 0x0001 297 #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 298 #define MDIO_PCS_1000BT1_CTRL_LOW_POWER 0x0800 299 #define MDIO_PCS_1000BT1_CTRL_DISABLE_TX 0x4000 300 #define MDIO_PCS_1000BT1_CTRL_RESET 0x8000 301 #define MDIO_PCS_1000BT1_STAT_LINK 0x0004 302 #define MDIO_PCS_1000BT1_STAT_FAULT 0x0080 303 #define MDIO_AN_EEE_ADV_100TX 0x0002 304 #define MDIO_AN_EEE_ADV_1000T 0x0004 305 #define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX 306 #define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T 307 #define MDIO_EEE_10GT 0x0008 308 #define MDIO_EEE_1000KX 0x0010 309 #define MDIO_EEE_10GKX4 0x0020 310 #define MDIO_EEE_10GKR 0x0040 311 #define MDIO_EEE_40GR_FW 0x0100 312 #define MDIO_EEE_40GR_DS 0x0200 313 #define MDIO_EEE_100GR_FW 0x1000 314 #define MDIO_EEE_100GR_DS 0x2000 315 #define MDIO_EEE_2_5GT 0x0001 316 #define MDIO_EEE_5GT 0x0002 317 #define MDIO_AN_THP_BP2_5GT 0x0008 318 #define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 319 #define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 320 #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 321 #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 322 #define MDIO_PMA_LASI_RX_PMALFLT 0x0010 323 #define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 324 #define MDIO_PMA_LASI_RX_WISLFLT 0x0200 325 #define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 326 #define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 327 #define MDIO_PMA_LASI_TX_PMALFLT 0x0010 328 #define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 329 #define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 330 #define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 331 #define MDIO_PMA_LASI_LSALARM 0x0001 332 #define MDIO_PMA_LASI_TXALARM 0x0002 333 #define MDIO_PMA_LASI_RXALARM 0x0004 334 #define MDIO_PHY_ID_C45 0x8000 335 #define MDIO_PHY_ID_PRTAD 0x03e0 336 #define MDIO_PHY_ID_DEVAD 0x001f 337 #define MDIO_PHY_ID_C45_MASK (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD) 338 #define MDIO_USXGMII_EEE_CLK_STP 0x0080 339 #define MDIO_USXGMII_EEE 0x0100 340 #define MDIO_USXGMII_SPD_MASK 0x0e00 341 #define MDIO_USXGMII_FULL_DUPLEX 0x1000 342 #define MDIO_USXGMII_DPX_SPD_MASK 0x1e00 343 #define MDIO_USXGMII_10 0x0000 344 #define MDIO_USXGMII_10HALF 0x0000 345 #define MDIO_USXGMII_10FULL 0x1000 346 #define MDIO_USXGMII_100 0x0200 347 #define MDIO_USXGMII_100HALF 0x0200 348 #define MDIO_USXGMII_100FULL 0x1200 349 #define MDIO_USXGMII_1000 0x0400 350 #define MDIO_USXGMII_1000HALF 0x0400 351 #define MDIO_USXGMII_1000FULL 0x1400 352 #define MDIO_USXGMII_10G 0x0600 353 #define MDIO_USXGMII_10GHALF 0x0600 354 #define MDIO_USXGMII_10GFULL 0x1600 355 #define MDIO_USXGMII_2500 0x0800 356 #define MDIO_USXGMII_2500HALF 0x0800 357 #define MDIO_USXGMII_2500FULL 0x1800 358 #define MDIO_USXGMII_5000 0x0a00 359 #define MDIO_USXGMII_5000HALF 0x0a00 360 #define MDIO_USXGMII_5000FULL 0x1a00 361 #define MDIO_USXGMII_LINK 0x8000 362 #endif 363