1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _USR_IDXD_H_ 8 #define _USR_IDXD_H_ 9 #include <stdint.h> 10 enum idxd_scmd_stat { 11 IDXD_SCMD_DEV_ENABLED = 0x80000010, 12 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020, 13 IDXD_SCMD_WQ_ENABLED = 0x80000021, 14 IDXD_SCMD_DEV_DMA_ERR = 0x80020000, 15 IDXD_SCMD_WQ_NO_GRP = 0x80030000, 16 IDXD_SCMD_WQ_NO_NAME = 0x80040000, 17 IDXD_SCMD_WQ_NO_SVM = 0x80050000, 18 IDXD_SCMD_WQ_NO_THRESH = 0x80060000, 19 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000, 20 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000, 21 IDXD_SCMD_PERCPU_ERR = 0x80090000, 22 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000, 23 IDXD_SCMD_CDEV_ERR = 0x800b0000, 24 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000, 25 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000, 26 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000, 27 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000, 28 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000, 29 IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000, 30 IDXD_SCMD_DEV_EVL_ERR = 0x80120000, 31 IDXD_SCMD_WQ_NO_DRV_NAME = 0x80200000, 32 }; 33 #define IDXD_SCMD_SOFTERR_MASK 0x80000000 34 #define IDXD_SCMD_SOFTERR_SHIFT 16 35 #define IDXD_OP_FLAG_FENCE 0x0001 36 #define IDXD_OP_FLAG_BOF 0x0002 37 #define IDXD_OP_FLAG_CRAV 0x0004 38 #define IDXD_OP_FLAG_RCR 0x0008 39 #define IDXD_OP_FLAG_RCI 0x0010 40 #define IDXD_OP_FLAG_CRSTS 0x0020 41 #define IDXD_OP_FLAG_CR 0x0080 42 #define IDXD_OP_FLAG_CC 0x0100 43 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200 44 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400 45 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800 46 #define IDXD_OP_FLAG_CR_TCS 0x1000 47 #define IDXD_OP_FLAG_STORD 0x2000 48 #define IDXD_OP_FLAG_DRDBK 0x4000 49 #define IDXD_OP_FLAG_DSTS 0x8000 50 #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 51 #define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000 52 #define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000 53 #define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000 54 #define IDXD_OP_FLAG_SRC2_STS 0x100000 55 #define IDXD_OP_FLAG_CRC_RFC3720 0x200000 56 enum dsa_opcode { 57 DSA_OPCODE_NOOP = 0, 58 DSA_OPCODE_BATCH, 59 DSA_OPCODE_DRAIN, 60 DSA_OPCODE_MEMMOVE, 61 DSA_OPCODE_MEMFILL, 62 DSA_OPCODE_COMPARE, 63 DSA_OPCODE_COMPVAL, 64 DSA_OPCODE_CR_DELTA, 65 DSA_OPCODE_AP_DELTA, 66 DSA_OPCODE_DUALCAST, 67 DSA_OPCODE_TRANSL_FETCH, 68 DSA_OPCODE_CRCGEN = 0x10, 69 DSA_OPCODE_COPY_CRC, 70 DSA_OPCODE_DIF_CHECK, 71 DSA_OPCODE_DIF_INS, 72 DSA_OPCODE_DIF_STRP, 73 DSA_OPCODE_DIF_UPDT, 74 DSA_OPCODE_DIX_GEN = 0x17, 75 DSA_OPCODE_CFLUSH = 0x20, 76 }; 77 enum iax_opcode { 78 IAX_OPCODE_NOOP = 0, 79 IAX_OPCODE_DRAIN = 2, 80 IAX_OPCODE_MEMMOVE, 81 IAX_OPCODE_DECOMPRESS = 0x42, 82 IAX_OPCODE_COMPRESS, 83 IAX_OPCODE_CRC64, 84 IAX_OPCODE_ZERO_DECOMP_32 = 0x48, 85 IAX_OPCODE_ZERO_DECOMP_16, 86 IAX_OPCODE_ZERO_COMP_32 = 0x4c, 87 IAX_OPCODE_ZERO_COMP_16, 88 IAX_OPCODE_SCAN = 0x50, 89 IAX_OPCODE_SET_MEMBER, 90 IAX_OPCODE_EXTRACT, 91 IAX_OPCODE_SELECT, 92 IAX_OPCODE_RLE_BURST, 93 IAX_OPCODE_FIND_UNIQUE, 94 IAX_OPCODE_EXPAND, 95 }; 96 enum dsa_completion_status { 97 DSA_COMP_NONE = 0, 98 DSA_COMP_SUCCESS, 99 DSA_COMP_SUCCESS_PRED, 100 DSA_COMP_PAGE_FAULT_NOBOF, 101 DSA_COMP_PAGE_FAULT_IR, 102 DSA_COMP_BATCH_FAIL, 103 DSA_COMP_BATCH_PAGE_FAULT, 104 DSA_COMP_DR_OFFSET_NOINC, 105 DSA_COMP_DR_OFFSET_ERANGE, 106 DSA_COMP_DIF_ERR, 107 DSA_COMP_BAD_OPCODE = 0x10, 108 DSA_COMP_INVALID_FLAGS, 109 DSA_COMP_NOZERO_RESERVE, 110 DSA_COMP_XFER_ERANGE, 111 DSA_COMP_DESC_CNT_ERANGE, 112 DSA_COMP_DR_ERANGE, 113 DSA_COMP_OVERLAP_BUFFERS, 114 DSA_COMP_DCAST_ERR, 115 DSA_COMP_DESCLIST_ALIGN, 116 DSA_COMP_INT_HANDLE_INVAL, 117 DSA_COMP_CRA_XLAT, 118 DSA_COMP_CRA_ALIGN, 119 DSA_COMP_ADDR_ALIGN, 120 DSA_COMP_PRIV_BAD, 121 DSA_COMP_TRAFFIC_CLASS_CONF, 122 DSA_COMP_PFAULT_RDBA, 123 DSA_COMP_HW_ERR1, 124 DSA_COMP_HW_ERR_DRB, 125 DSA_COMP_TRANSLATION_FAIL, 126 DSA_COMP_DRAIN_EVL = 0x26, 127 DSA_COMP_BATCH_EVL_ERR, 128 }; 129 enum iax_completion_status { 130 IAX_COMP_NONE = 0, 131 IAX_COMP_SUCCESS, 132 IAX_COMP_PAGE_FAULT_IR = 0x04, 133 IAX_COMP_ANALYTICS_ERROR = 0x0a, 134 IAX_COMP_OUTBUF_OVERFLOW, 135 IAX_COMP_BAD_OPCODE = 0x10, 136 IAX_COMP_INVALID_FLAGS, 137 IAX_COMP_NOZERO_RESERVE, 138 IAX_COMP_INVALID_SIZE, 139 IAX_COMP_OVERLAP_BUFFERS = 0x16, 140 IAX_COMP_INT_HANDLE_INVAL = 0x19, 141 IAX_COMP_CRA_XLAT, 142 IAX_COMP_CRA_ALIGN, 143 IAX_COMP_ADDR_ALIGN, 144 IAX_COMP_PRIV_BAD, 145 IAX_COMP_TRAFFIC_CLASS_CONF, 146 IAX_COMP_PFAULT_RDBA, 147 IAX_COMP_HW_ERR1, 148 IAX_COMP_HW_ERR_DRB, 149 IAX_COMP_TRANSLATION_FAIL, 150 IAX_COMP_PRS_TIMEOUT, 151 IAX_COMP_WATCHDOG, 152 IAX_COMP_INVALID_COMP_FLAG = 0x30, 153 IAX_COMP_INVALID_FILTER_FLAG, 154 IAX_COMP_INVALID_INPUT_SIZE, 155 IAX_COMP_INVALID_NUM_ELEMS, 156 IAX_COMP_INVALID_SRC1_WIDTH, 157 IAX_COMP_INVALID_INVERT_OUT, 158 }; 159 #define DSA_COMP_STATUS_MASK 0x7f 160 #define DSA_COMP_STATUS_WRITE 0x80 161 #define DSA_COMP_STATUS(status) ((status) & DSA_COMP_STATUS_MASK) 162 struct dsa_hw_desc { 163 uint32_t pasid : 20; 164 uint32_t rsvd : 11; 165 uint32_t priv : 1; 166 uint32_t flags : 24; 167 uint32_t opcode : 8; 168 uint64_t completion_addr; 169 union { 170 uint64_t src_addr; 171 uint64_t rdback_addr; 172 uint64_t pattern; 173 uint64_t desc_list_addr; 174 uint64_t pattern_lower; 175 uint64_t transl_fetch_addr; 176 }; 177 union { 178 uint64_t dst_addr; 179 uint64_t rdback_addr2; 180 uint64_t src2_addr; 181 uint64_t comp_pattern; 182 }; 183 union { 184 uint32_t xfer_size; 185 uint32_t desc_count; 186 uint32_t region_size; 187 }; 188 uint16_t int_handle; 189 uint16_t rsvd1; 190 union { 191 uint8_t expected_res; 192 struct { 193 uint64_t delta_addr; 194 uint32_t max_delta_size; 195 uint32_t delt_rsvd; 196 uint8_t expected_res_mask; 197 }; 198 uint32_t delta_rec_size; 199 uint64_t dest2; 200 struct { 201 uint32_t crc_seed; 202 uint32_t crc_rsvd; 203 uint64_t seed_addr; 204 }; 205 struct { 206 uint8_t src_dif_flags; 207 uint8_t dif_chk_res; 208 uint8_t dif_chk_flags; 209 uint8_t dif_chk_res2[5]; 210 uint32_t chk_ref_tag_seed; 211 uint16_t chk_app_tag_mask; 212 uint16_t chk_app_tag_seed; 213 }; 214 struct { 215 uint8_t dif_ins_res; 216 uint8_t dest_dif_flag; 217 uint8_t dif_ins_flags; 218 uint8_t dif_ins_res2[13]; 219 uint32_t ins_ref_tag_seed; 220 uint16_t ins_app_tag_mask; 221 uint16_t ins_app_tag_seed; 222 }; 223 struct { 224 uint8_t src_upd_flags; 225 uint8_t upd_dest_flags; 226 uint8_t dif_upd_flags; 227 uint8_t dif_upd_res[5]; 228 uint32_t src_ref_tag_seed; 229 uint16_t src_app_tag_mask; 230 uint16_t src_app_tag_seed; 231 uint32_t dest_ref_tag_seed; 232 uint16_t dest_app_tag_mask; 233 uint16_t dest_app_tag_seed; 234 }; 235 uint64_t pattern_upper; 236 struct { 237 uint64_t transl_fetch_res; 238 uint32_t region_stride; 239 }; 240 struct { 241 uint8_t dix_gen_res; 242 uint8_t dest_dif_flags; 243 uint8_t dif_flags; 244 uint8_t dix_gen_res2[13]; 245 uint32_t ref_tag_seed; 246 uint16_t app_tag_mask; 247 uint16_t app_tag_seed; 248 }; 249 uint8_t op_specific[24]; 250 }; 251 } __attribute__((packed)); 252 struct iax_hw_desc { 253 uint32_t pasid : 20; 254 uint32_t rsvd : 11; 255 uint32_t priv : 1; 256 uint32_t flags : 24; 257 uint32_t opcode : 8; 258 uint64_t completion_addr; 259 uint64_t src1_addr; 260 uint64_t dst_addr; 261 uint32_t src1_size; 262 uint16_t int_handle; 263 union { 264 uint16_t compr_flags; 265 uint16_t decompr_flags; 266 }; 267 uint64_t src2_addr; 268 uint32_t max_dst_size; 269 uint32_t src2_size; 270 uint32_t filter_flags; 271 uint32_t num_inputs; 272 } __attribute__((packed)); 273 struct dsa_raw_desc { 274 uint64_t field[8]; 275 } __attribute__((packed)); 276 struct dsa_completion_record { 277 volatile uint8_t status; 278 union { 279 uint8_t result; 280 uint8_t dif_status; 281 }; 282 uint8_t fault_info; 283 uint8_t rsvd; 284 union { 285 uint32_t bytes_completed; 286 uint32_t descs_completed; 287 }; 288 uint64_t fault_addr; 289 union { 290 struct { 291 uint32_t invalid_flags : 24; 292 uint32_t rsvd2 : 8; 293 }; 294 uint32_t delta_rec_size; 295 uint64_t crc_val; 296 struct { 297 uint32_t dif_chk_ref_tag; 298 uint16_t dif_chk_app_tag_mask; 299 uint16_t dif_chk_app_tag; 300 }; 301 struct { 302 uint64_t dif_ins_res; 303 uint32_t dif_ins_ref_tag; 304 uint16_t dif_ins_app_tag_mask; 305 uint16_t dif_ins_app_tag; 306 }; 307 struct { 308 uint32_t dif_upd_src_ref_tag; 309 uint16_t dif_upd_src_app_tag_mask; 310 uint16_t dif_upd_src_app_tag; 311 uint32_t dif_upd_dest_ref_tag; 312 uint16_t dif_upd_dest_app_tag_mask; 313 uint16_t dif_upd_dest_app_tag; 314 }; 315 struct { 316 uint64_t dix_gen_res; 317 uint32_t dix_ref_tag; 318 uint16_t dix_app_tag_mask; 319 uint16_t dix_app_tag; 320 }; 321 uint8_t op_specific[16]; 322 }; 323 } __attribute__((packed)); 324 struct dsa_raw_completion_record { 325 uint64_t field[4]; 326 } __attribute__((packed)); 327 struct iax_completion_record { 328 volatile uint8_t status; 329 uint8_t error_code; 330 uint8_t fault_info; 331 uint8_t rsvd; 332 uint32_t bytes_completed; 333 uint64_t fault_addr; 334 uint32_t invalid_flags; 335 uint32_t rsvd2; 336 uint32_t output_size; 337 uint8_t output_bits; 338 uint8_t rsvd3; 339 uint16_t xor_csum; 340 uint32_t crc; 341 uint32_t min; 342 uint32_t max; 343 uint32_t sum; 344 uint64_t rsvd4[2]; 345 } __attribute__((packed)); 346 struct iax_raw_completion_record { 347 uint64_t field[8]; 348 } __attribute__((packed)); 349 #endif 350