1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _UAPI_LINUX_ETHTOOL_H 8 #define _UAPI_LINUX_ETHTOOL_H 9 #include <linux/const.h> 10 #include <linux/types.h> 11 #include <linux/if_ether.h> 12 #include <limits.h> 13 struct ethtool_cmd { 14 __u32 cmd; 15 __u32 supported; 16 __u32 advertising; 17 __u16 speed; 18 __u8 duplex; 19 __u8 port; 20 __u8 phy_address; 21 __u8 transceiver; 22 __u8 autoneg; 23 __u8 mdio_support; 24 __u32 maxtxpkt; 25 __u32 maxrxpkt; 26 __u16 speed_hi; 27 __u8 eth_tp_mdix; 28 __u8 eth_tp_mdix_ctrl; 29 __u32 lp_advertising; 30 __u32 reserved[2]; 31 }; 32 #define ETH_MDIO_SUPPORTS_C22 1 33 #define ETH_MDIO_SUPPORTS_C45 2 34 #define ETHTOOL_FWVERS_LEN 32 35 #define ETHTOOL_BUSINFO_LEN 32 36 #define ETHTOOL_EROMVERS_LEN 32 37 struct ethtool_drvinfo { 38 __u32 cmd; 39 char driver[32]; 40 char version[32]; 41 char fw_version[ETHTOOL_FWVERS_LEN]; 42 char bus_info[ETHTOOL_BUSINFO_LEN]; 43 char erom_version[ETHTOOL_EROMVERS_LEN]; 44 char reserved2[12]; 45 __u32 n_priv_flags; 46 __u32 n_stats; 47 __u32 testinfo_len; 48 __u32 eedump_len; 49 __u32 regdump_len; 50 }; 51 #define SOPASS_MAX 6 52 struct ethtool_wolinfo { 53 __u32 cmd; 54 __u32 supported; 55 __u32 wolopts; 56 __u8 sopass[SOPASS_MAX]; 57 }; 58 struct ethtool_value { 59 __u32 cmd; 60 __u32 data; 61 }; 62 #define PFC_STORM_PREVENTION_AUTO 0xffff 63 #define PFC_STORM_PREVENTION_DISABLE 0 64 enum tunable_id { 65 ETHTOOL_ID_UNSPEC, 66 ETHTOOL_RX_COPYBREAK, 67 ETHTOOL_TX_COPYBREAK, 68 ETHTOOL_PFC_PREVENTION_TOUT, 69 ETHTOOL_TX_COPYBREAK_BUF_SIZE, 70 __ETHTOOL_TUNABLE_COUNT, 71 }; 72 enum tunable_type_id { 73 ETHTOOL_TUNABLE_UNSPEC, 74 ETHTOOL_TUNABLE_U8, 75 ETHTOOL_TUNABLE_U16, 76 ETHTOOL_TUNABLE_U32, 77 ETHTOOL_TUNABLE_U64, 78 ETHTOOL_TUNABLE_STRING, 79 ETHTOOL_TUNABLE_S8, 80 ETHTOOL_TUNABLE_S16, 81 ETHTOOL_TUNABLE_S32, 82 ETHTOOL_TUNABLE_S64, 83 }; 84 struct ethtool_tunable { 85 __u32 cmd; 86 __u32 id; 87 __u32 type_id; 88 __u32 len; 89 void * data[]; 90 }; 91 #define DOWNSHIFT_DEV_DEFAULT_COUNT 0xff 92 #define DOWNSHIFT_DEV_DISABLE 0 93 #define ETHTOOL_PHY_FAST_LINK_DOWN_ON 0 94 #define ETHTOOL_PHY_FAST_LINK_DOWN_OFF 0xff 95 #define ETHTOOL_PHY_EDPD_DFLT_TX_MSECS 0xffff 96 #define ETHTOOL_PHY_EDPD_NO_TX 0xfffe 97 #define ETHTOOL_PHY_EDPD_DISABLE 0 98 enum phy_tunable_id { 99 ETHTOOL_PHY_ID_UNSPEC, 100 ETHTOOL_PHY_DOWNSHIFT, 101 ETHTOOL_PHY_FAST_LINK_DOWN, 102 ETHTOOL_PHY_EDPD, 103 __ETHTOOL_PHY_TUNABLE_COUNT, 104 }; 105 struct ethtool_regs { 106 __u32 cmd; 107 __u32 version; 108 __u32 len; 109 __u8 data[]; 110 }; 111 struct ethtool_eeprom { 112 __u32 cmd; 113 __u32 magic; 114 __u32 offset; 115 __u32 len; 116 __u8 data[]; 117 }; 118 struct ethtool_eee { 119 __u32 cmd; 120 __u32 supported; 121 __u32 advertised; 122 __u32 lp_advertised; 123 __u32 eee_active; 124 __u32 eee_enabled; 125 __u32 tx_lpi_enabled; 126 __u32 tx_lpi_timer; 127 __u32 reserved[2]; 128 }; 129 struct ethtool_modinfo { 130 __u32 cmd; 131 __u32 type; 132 __u32 eeprom_len; 133 __u32 reserved[8]; 134 }; 135 struct ethtool_coalesce { 136 __u32 cmd; 137 __u32 rx_coalesce_usecs; 138 __u32 rx_max_coalesced_frames; 139 __u32 rx_coalesce_usecs_irq; 140 __u32 rx_max_coalesced_frames_irq; 141 __u32 tx_coalesce_usecs; 142 __u32 tx_max_coalesced_frames; 143 __u32 tx_coalesce_usecs_irq; 144 __u32 tx_max_coalesced_frames_irq; 145 __u32 stats_block_coalesce_usecs; 146 __u32 use_adaptive_rx_coalesce; 147 __u32 use_adaptive_tx_coalesce; 148 __u32 pkt_rate_low; 149 __u32 rx_coalesce_usecs_low; 150 __u32 rx_max_coalesced_frames_low; 151 __u32 tx_coalesce_usecs_low; 152 __u32 tx_max_coalesced_frames_low; 153 __u32 pkt_rate_high; 154 __u32 rx_coalesce_usecs_high; 155 __u32 rx_max_coalesced_frames_high; 156 __u32 tx_coalesce_usecs_high; 157 __u32 tx_max_coalesced_frames_high; 158 __u32 rate_sample_interval; 159 }; 160 struct ethtool_ringparam { 161 __u32 cmd; 162 __u32 rx_max_pending; 163 __u32 rx_mini_max_pending; 164 __u32 rx_jumbo_max_pending; 165 __u32 tx_max_pending; 166 __u32 rx_pending; 167 __u32 rx_mini_pending; 168 __u32 rx_jumbo_pending; 169 __u32 tx_pending; 170 }; 171 struct ethtool_channels { 172 __u32 cmd; 173 __u32 max_rx; 174 __u32 max_tx; 175 __u32 max_other; 176 __u32 max_combined; 177 __u32 rx_count; 178 __u32 tx_count; 179 __u32 other_count; 180 __u32 combined_count; 181 }; 182 struct ethtool_pauseparam { 183 __u32 cmd; 184 __u32 autoneg; 185 __u32 rx_pause; 186 __u32 tx_pause; 187 }; 188 enum ethtool_link_ext_state { 189 ETHTOOL_LINK_EXT_STATE_AUTONEG, 190 ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 191 ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 192 ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 193 ETHTOOL_LINK_EXT_STATE_NO_CABLE, 194 ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 195 ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 196 ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, 197 ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 198 ETHTOOL_LINK_EXT_STATE_OVERHEAT, 199 ETHTOOL_LINK_EXT_STATE_MODULE, 200 }; 201 enum ethtool_link_ext_substate_autoneg { 202 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED = 1, 203 ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED, 204 ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED, 205 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE, 206 ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE, 207 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD, 208 }; 209 enum ethtool_link_ext_substate_link_training { 210 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED = 1, 211 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT, 212 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY, 213 ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT, 214 }; 215 enum ethtool_link_ext_substate_link_logical_mismatch { 216 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK = 1, 217 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK, 218 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS, 219 ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED, 220 ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED, 221 }; 222 enum ethtool_link_ext_substate_bad_signal_integrity { 223 ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1, 224 ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE, 225 ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST, 226 ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS, 227 }; 228 enum ethtool_link_ext_substate_cable_issue { 229 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE = 1, 230 ETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE, 231 }; 232 enum ethtool_link_ext_substate_module { 233 ETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY = 1, 234 }; 235 #define ETH_GSTRING_LEN 32 236 enum ethtool_stringset { 237 ETH_SS_TEST = 0, 238 ETH_SS_STATS, 239 ETH_SS_PRIV_FLAGS, 240 ETH_SS_NTUPLE_FILTERS, 241 ETH_SS_FEATURES, 242 ETH_SS_RSS_HASH_FUNCS, 243 ETH_SS_TUNABLES, 244 ETH_SS_PHY_STATS, 245 ETH_SS_PHY_TUNABLES, 246 ETH_SS_LINK_MODES, 247 ETH_SS_MSG_CLASSES, 248 ETH_SS_WOL_MODES, 249 ETH_SS_SOF_TIMESTAMPING, 250 ETH_SS_TS_TX_TYPES, 251 ETH_SS_TS_RX_FILTERS, 252 ETH_SS_UDP_TUNNEL_TYPES, 253 ETH_SS_STATS_STD, 254 ETH_SS_STATS_ETH_PHY, 255 ETH_SS_STATS_ETH_MAC, 256 ETH_SS_STATS_ETH_CTRL, 257 ETH_SS_STATS_RMON, 258 ETH_SS_COUNT 259 }; 260 enum ethtool_mac_stats_src { 261 ETHTOOL_MAC_STATS_SRC_AGGREGATE, 262 ETHTOOL_MAC_STATS_SRC_EMAC, 263 ETHTOOL_MAC_STATS_SRC_PMAC, 264 }; 265 enum ethtool_module_power_mode_policy { 266 ETHTOOL_MODULE_POWER_MODE_POLICY_HIGH = 1, 267 ETHTOOL_MODULE_POWER_MODE_POLICY_AUTO, 268 }; 269 enum ethtool_module_power_mode { 270 ETHTOOL_MODULE_POWER_MODE_LOW = 1, 271 ETHTOOL_MODULE_POWER_MODE_HIGH, 272 }; 273 enum ethtool_c33_pse_ext_state { 274 ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION = 1, 275 ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID, 276 ETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE, 277 ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED, 278 ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM, 279 ETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED, 280 ETHTOOL_C33_PSE_EXT_STATE_PD_DLL_POWER_TYPE, 281 ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE, 282 ETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED, 283 }; 284 enum ethtool_c33_pse_ext_substate_mr_mps_valid { 285 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_DETECTED_UNDERLOAD = 1, 286 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_CONNECTION_OPEN, 287 }; 288 enum ethtool_c33_pse_ext_substate_error_condition { 289 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT = 1, 290 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT, 291 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT, 292 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_COMM_ERROR_AFTER_FORCE_ON, 293 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS, 294 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_TURN_OFF, 295 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_HOST_CRASH_FORCE_SHUTDOWN, 296 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE, 297 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP, 298 }; 299 enum ethtool_c33_pse_ext_substate_mr_pse_enable { 300 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE = 1, 301 }; 302 enum ethtool_c33_pse_ext_substate_option_detect_ted { 303 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS = 1, 304 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR, 305 }; 306 enum ethtool_c33_pse_ext_substate_option_vport_lim { 307 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE = 1, 308 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE, 309 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION, 310 }; 311 enum ethtool_c33_pse_ext_substate_ovld_detected { 312 ETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD = 1, 313 }; 314 enum ethtool_c33_pse_ext_substate_power_not_available { 315 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED = 1, 316 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET, 317 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT, 318 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT, 319 }; 320 enum ethtool_c33_pse_ext_substate_short_detected { 321 ETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION = 1, 322 }; 323 enum ethtool_pse_types { 324 ETHTOOL_PSE_UNKNOWN = 1 << 0, 325 ETHTOOL_PSE_PODL = 1 << 1, 326 ETHTOOL_PSE_C33 = 1 << 2, 327 }; 328 enum ethtool_c33_pse_admin_state { 329 ETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN = 1, 330 ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED, 331 ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED, 332 }; 333 enum ethtool_c33_pse_pw_d_status { 334 ETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN = 1, 335 ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED, 336 ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING, 337 ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING, 338 ETHTOOL_C33_PSE_PW_D_STATUS_TEST, 339 ETHTOOL_C33_PSE_PW_D_STATUS_FAULT, 340 ETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT, 341 }; 342 enum ethtool_podl_pse_admin_state { 343 ETHTOOL_PODL_PSE_ADMIN_STATE_UNKNOWN = 1, 344 ETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED, 345 ETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED, 346 }; 347 enum ethtool_podl_pse_pw_d_status { 348 ETHTOOL_PODL_PSE_PW_D_STATUS_UNKNOWN = 1, 349 ETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED, 350 ETHTOOL_PODL_PSE_PW_D_STATUS_SEARCHING, 351 ETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING, 352 ETHTOOL_PODL_PSE_PW_D_STATUS_SLEEP, 353 ETHTOOL_PODL_PSE_PW_D_STATUS_IDLE, 354 ETHTOOL_PODL_PSE_PW_D_STATUS_ERROR, 355 }; 356 enum ethtool_mm_verify_status { 357 ETHTOOL_MM_VERIFY_STATUS_UNKNOWN, 358 ETHTOOL_MM_VERIFY_STATUS_INITIAL, 359 ETHTOOL_MM_VERIFY_STATUS_VERIFYING, 360 ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED, 361 ETHTOOL_MM_VERIFY_STATUS_FAILED, 362 ETHTOOL_MM_VERIFY_STATUS_DISABLED, 363 }; 364 enum ethtool_module_fw_flash_status { 365 ETHTOOL_MODULE_FW_FLASH_STATUS_STARTED = 1, 366 ETHTOOL_MODULE_FW_FLASH_STATUS_IN_PROGRESS, 367 ETHTOOL_MODULE_FW_FLASH_STATUS_COMPLETED, 368 ETHTOOL_MODULE_FW_FLASH_STATUS_ERROR, 369 }; 370 struct ethtool_gstrings { 371 __u32 cmd; 372 __u32 string_set; 373 __u32 len; 374 __u8 data[]; 375 }; 376 struct ethtool_sset_info { 377 __u32 cmd; 378 __u32 reserved; 379 __u64 sset_mask; 380 __u32 data[]; 381 }; 382 enum ethtool_test_flags { 383 ETH_TEST_FL_OFFLINE = (1 << 0), 384 ETH_TEST_FL_FAILED = (1 << 1), 385 ETH_TEST_FL_EXTERNAL_LB = (1 << 2), 386 ETH_TEST_FL_EXTERNAL_LB_DONE = (1 << 3), 387 }; 388 struct ethtool_test { 389 __u32 cmd; 390 __u32 flags; 391 __u32 reserved; 392 __u32 len; 393 __u64 data[]; 394 }; 395 struct ethtool_stats { 396 __u32 cmd; 397 __u32 n_stats; 398 __u64 data[]; 399 }; 400 struct ethtool_perm_addr { 401 __u32 cmd; 402 __u32 size; 403 __u8 data[]; 404 }; 405 enum ethtool_flags { 406 ETH_FLAG_TXVLAN = (1 << 7), 407 ETH_FLAG_RXVLAN = (1 << 8), 408 ETH_FLAG_LRO = (1 << 15), 409 ETH_FLAG_NTUPLE = (1 << 27), 410 ETH_FLAG_RXHASH = (1 << 28), 411 }; 412 struct ethtool_tcpip4_spec { 413 __be32 ip4src; 414 __be32 ip4dst; 415 __be16 psrc; 416 __be16 pdst; 417 __u8 tos; 418 }; 419 struct ethtool_ah_espip4_spec { 420 __be32 ip4src; 421 __be32 ip4dst; 422 __be32 spi; 423 __u8 tos; 424 }; 425 #define ETH_RX_NFC_IP4 1 426 struct ethtool_usrip4_spec { 427 __be32 ip4src; 428 __be32 ip4dst; 429 __be32 l4_4_bytes; 430 __u8 tos; 431 __u8 ip_ver; 432 __u8 proto; 433 }; 434 struct ethtool_tcpip6_spec { 435 __be32 ip6src[4]; 436 __be32 ip6dst[4]; 437 __be16 psrc; 438 __be16 pdst; 439 __u8 tclass; 440 }; 441 struct ethtool_ah_espip6_spec { 442 __be32 ip6src[4]; 443 __be32 ip6dst[4]; 444 __be32 spi; 445 __u8 tclass; 446 }; 447 struct ethtool_usrip6_spec { 448 __be32 ip6src[4]; 449 __be32 ip6dst[4]; 450 __be32 l4_4_bytes; 451 __u8 tclass; 452 __u8 l4_proto; 453 }; 454 union ethtool_flow_union { 455 struct ethtool_tcpip4_spec tcp_ip4_spec; 456 struct ethtool_tcpip4_spec udp_ip4_spec; 457 struct ethtool_tcpip4_spec sctp_ip4_spec; 458 struct ethtool_ah_espip4_spec ah_ip4_spec; 459 struct ethtool_ah_espip4_spec esp_ip4_spec; 460 struct ethtool_usrip4_spec usr_ip4_spec; 461 struct ethtool_tcpip6_spec tcp_ip6_spec; 462 struct ethtool_tcpip6_spec udp_ip6_spec; 463 struct ethtool_tcpip6_spec sctp_ip6_spec; 464 struct ethtool_ah_espip6_spec ah_ip6_spec; 465 struct ethtool_ah_espip6_spec esp_ip6_spec; 466 struct ethtool_usrip6_spec usr_ip6_spec; 467 struct ethhdr ether_spec; 468 __u8 hdata[52]; 469 }; 470 struct ethtool_flow_ext { 471 __u8 padding[2]; 472 unsigned char h_dest[ETH_ALEN]; 473 __be16 vlan_etype; 474 __be16 vlan_tci; 475 __be32 data[2]; 476 }; 477 struct ethtool_rx_flow_spec { 478 __u32 flow_type; 479 union ethtool_flow_union h_u; 480 struct ethtool_flow_ext h_ext; 481 union ethtool_flow_union m_u; 482 struct ethtool_flow_ext m_ext; 483 __u64 ring_cookie; 484 __u32 location; 485 }; 486 #define ETHTOOL_RX_FLOW_SPEC_RING 0x00000000FFFFFFFFLL 487 #define ETHTOOL_RX_FLOW_SPEC_RING_VF 0x000000FF00000000LL 488 #define ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF 32 489 struct ethtool_rxnfc { 490 __u32 cmd; 491 __u32 flow_type; 492 __u64 data; 493 struct ethtool_rx_flow_spec fs; 494 union { 495 __u32 rule_cnt; 496 __u32 rss_context; 497 }; 498 __u32 rule_locs[]; 499 }; 500 struct ethtool_rxfh_indir { 501 __u32 cmd; 502 __u32 size; 503 __u32 ring_index[]; 504 }; 505 struct ethtool_rxfh { 506 __u32 cmd; 507 __u32 rss_context; 508 __u32 indir_size; 509 __u32 key_size; 510 __u8 hfunc; 511 __u8 input_xfrm; 512 __u8 rsvd8[2]; 513 __u32 rsvd32; 514 __u32 rss_config[]; 515 }; 516 #define ETH_RXFH_CONTEXT_ALLOC 0xffffffff 517 #define ETH_RXFH_INDIR_NO_CHANGE 0xffffffff 518 struct ethtool_rx_ntuple_flow_spec { 519 __u32 flow_type; 520 union { 521 struct ethtool_tcpip4_spec tcp_ip4_spec; 522 struct ethtool_tcpip4_spec udp_ip4_spec; 523 struct ethtool_tcpip4_spec sctp_ip4_spec; 524 struct ethtool_ah_espip4_spec ah_ip4_spec; 525 struct ethtool_ah_espip4_spec esp_ip4_spec; 526 struct ethtool_usrip4_spec usr_ip4_spec; 527 struct ethhdr ether_spec; 528 __u8 hdata[72]; 529 } h_u, m_u; 530 __u16 vlan_tag; 531 __u16 vlan_tag_mask; 532 __u64 data; 533 __u64 data_mask; 534 __s32 action; 535 #define ETHTOOL_RXNTUPLE_ACTION_DROP (- 1) 536 #define ETHTOOL_RXNTUPLE_ACTION_CLEAR (- 2) 537 }; 538 struct ethtool_rx_ntuple { 539 __u32 cmd; 540 struct ethtool_rx_ntuple_flow_spec fs; 541 }; 542 #define ETHTOOL_FLASH_MAX_FILENAME 128 543 enum ethtool_flash_op_type { 544 ETHTOOL_FLASH_ALL_REGIONS = 0, 545 }; 546 struct ethtool_flash { 547 __u32 cmd; 548 __u32 region; 549 char data[ETHTOOL_FLASH_MAX_FILENAME]; 550 }; 551 struct ethtool_dump { 552 __u32 cmd; 553 __u32 version; 554 __u32 flag; 555 __u32 len; 556 __u8 data[]; 557 }; 558 #define ETH_FW_DUMP_DISABLE 0 559 struct ethtool_get_features_block { 560 __u32 available; 561 __u32 requested; 562 __u32 active; 563 __u32 never_changed; 564 }; 565 struct ethtool_gfeatures { 566 __u32 cmd; 567 __u32 size; 568 struct ethtool_get_features_block features[]; 569 }; 570 struct ethtool_set_features_block { 571 __u32 valid; 572 __u32 requested; 573 }; 574 struct ethtool_sfeatures { 575 __u32 cmd; 576 __u32 size; 577 struct ethtool_set_features_block features[]; 578 }; 579 struct ethtool_ts_info { 580 __u32 cmd; 581 __u32 so_timestamping; 582 __s32 phc_index; 583 __u32 tx_types; 584 __u32 tx_reserved[3]; 585 __u32 rx_filters; 586 __u32 rx_reserved[3]; 587 }; 588 enum ethtool_sfeatures_retval_bits { 589 ETHTOOL_F_UNSUPPORTED__BIT, 590 ETHTOOL_F_WISH__BIT, 591 ETHTOOL_F_COMPAT__BIT, 592 }; 593 #define ETHTOOL_F_UNSUPPORTED (1 << ETHTOOL_F_UNSUPPORTED__BIT) 594 #define ETHTOOL_F_WISH (1 << ETHTOOL_F_WISH__BIT) 595 #define ETHTOOL_F_COMPAT (1 << ETHTOOL_F_COMPAT__BIT) 596 #define MAX_NUM_QUEUE 4096 597 struct ethtool_per_queue_op { 598 __u32 cmd; 599 __u32 sub_command; 600 __u32 queue_mask[__KERNEL_DIV_ROUND_UP(MAX_NUM_QUEUE, 32)]; 601 char data[]; 602 }; 603 struct ethtool_fecparam { 604 __u32 cmd; 605 __u32 active_fec; 606 __u32 fec; 607 __u32 reserved; 608 }; 609 enum ethtool_fec_config_bits { 610 ETHTOOL_FEC_NONE_BIT, 611 ETHTOOL_FEC_AUTO_BIT, 612 ETHTOOL_FEC_OFF_BIT, 613 ETHTOOL_FEC_RS_BIT, 614 ETHTOOL_FEC_BASER_BIT, 615 ETHTOOL_FEC_LLRS_BIT, 616 }; 617 #define ETHTOOL_FEC_NONE (1 << ETHTOOL_FEC_NONE_BIT) 618 #define ETHTOOL_FEC_AUTO (1 << ETHTOOL_FEC_AUTO_BIT) 619 #define ETHTOOL_FEC_OFF (1 << ETHTOOL_FEC_OFF_BIT) 620 #define ETHTOOL_FEC_RS (1 << ETHTOOL_FEC_RS_BIT) 621 #define ETHTOOL_FEC_BASER (1 << ETHTOOL_FEC_BASER_BIT) 622 #define ETHTOOL_FEC_LLRS (1 << ETHTOOL_FEC_LLRS_BIT) 623 #define ETHTOOL_GSET 0x00000001 624 #define ETHTOOL_SSET 0x00000002 625 #define ETHTOOL_GDRVINFO 0x00000003 626 #define ETHTOOL_GREGS 0x00000004 627 #define ETHTOOL_GWOL 0x00000005 628 #define ETHTOOL_SWOL 0x00000006 629 #define ETHTOOL_GMSGLVL 0x00000007 630 #define ETHTOOL_SMSGLVL 0x00000008 631 #define ETHTOOL_NWAY_RST 0x00000009 632 #define ETHTOOL_GLINK 0x0000000a 633 #define ETHTOOL_GEEPROM 0x0000000b 634 #define ETHTOOL_SEEPROM 0x0000000c 635 #define ETHTOOL_GCOALESCE 0x0000000e 636 #define ETHTOOL_SCOALESCE 0x0000000f 637 #define ETHTOOL_GRINGPARAM 0x00000010 638 #define ETHTOOL_SRINGPARAM 0x00000011 639 #define ETHTOOL_GPAUSEPARAM 0x00000012 640 #define ETHTOOL_SPAUSEPARAM 0x00000013 641 #define ETHTOOL_GRXCSUM 0x00000014 642 #define ETHTOOL_SRXCSUM 0x00000015 643 #define ETHTOOL_GTXCSUM 0x00000016 644 #define ETHTOOL_STXCSUM 0x00000017 645 #define ETHTOOL_GSG 0x00000018 646 #define ETHTOOL_SSG 0x00000019 647 #define ETHTOOL_TEST 0x0000001a 648 #define ETHTOOL_GSTRINGS 0x0000001b 649 #define ETHTOOL_PHYS_ID 0x0000001c 650 #define ETHTOOL_GSTATS 0x0000001d 651 #define ETHTOOL_GTSO 0x0000001e 652 #define ETHTOOL_STSO 0x0000001f 653 #define ETHTOOL_GPERMADDR 0x00000020 654 #define ETHTOOL_GUFO 0x00000021 655 #define ETHTOOL_SUFO 0x00000022 656 #define ETHTOOL_GGSO 0x00000023 657 #define ETHTOOL_SGSO 0x00000024 658 #define ETHTOOL_GFLAGS 0x00000025 659 #define ETHTOOL_SFLAGS 0x00000026 660 #define ETHTOOL_GPFLAGS 0x00000027 661 #define ETHTOOL_SPFLAGS 0x00000028 662 #define ETHTOOL_GRXFH 0x00000029 663 #define ETHTOOL_SRXFH 0x0000002a 664 #define ETHTOOL_GGRO 0x0000002b 665 #define ETHTOOL_SGRO 0x0000002c 666 #define ETHTOOL_GRXRINGS 0x0000002d 667 #define ETHTOOL_GRXCLSRLCNT 0x0000002e 668 #define ETHTOOL_GRXCLSRULE 0x0000002f 669 #define ETHTOOL_GRXCLSRLALL 0x00000030 670 #define ETHTOOL_SRXCLSRLDEL 0x00000031 671 #define ETHTOOL_SRXCLSRLINS 0x00000032 672 #define ETHTOOL_FLASHDEV 0x00000033 673 #define ETHTOOL_RESET 0x00000034 674 #define ETHTOOL_SRXNTUPLE 0x00000035 675 #define ETHTOOL_GRXNTUPLE 0x00000036 676 #define ETHTOOL_GSSET_INFO 0x00000037 677 #define ETHTOOL_GRXFHINDIR 0x00000038 678 #define ETHTOOL_SRXFHINDIR 0x00000039 679 #define ETHTOOL_GFEATURES 0x0000003a 680 #define ETHTOOL_SFEATURES 0x0000003b 681 #define ETHTOOL_GCHANNELS 0x0000003c 682 #define ETHTOOL_SCHANNELS 0x0000003d 683 #define ETHTOOL_SET_DUMP 0x0000003e 684 #define ETHTOOL_GET_DUMP_FLAG 0x0000003f 685 #define ETHTOOL_GET_DUMP_DATA 0x00000040 686 #define ETHTOOL_GET_TS_INFO 0x00000041 687 #define ETHTOOL_GMODULEINFO 0x00000042 688 #define ETHTOOL_GMODULEEEPROM 0x00000043 689 #define ETHTOOL_GEEE 0x00000044 690 #define ETHTOOL_SEEE 0x00000045 691 #define ETHTOOL_GRSSH 0x00000046 692 #define ETHTOOL_SRSSH 0x00000047 693 #define ETHTOOL_GTUNABLE 0x00000048 694 #define ETHTOOL_STUNABLE 0x00000049 695 #define ETHTOOL_GPHYSTATS 0x0000004a 696 #define ETHTOOL_PERQUEUE 0x0000004b 697 #define ETHTOOL_GLINKSETTINGS 0x0000004c 698 #define ETHTOOL_SLINKSETTINGS 0x0000004d 699 #define ETHTOOL_PHY_GTUNABLE 0x0000004e 700 #define ETHTOOL_PHY_STUNABLE 0x0000004f 701 #define ETHTOOL_GFECPARAM 0x00000050 702 #define ETHTOOL_SFECPARAM 0x00000051 703 #define SPARC_ETH_GSET ETHTOOL_GSET 704 #define SPARC_ETH_SSET ETHTOOL_SSET 705 enum ethtool_link_mode_bit_indices { 706 ETHTOOL_LINK_MODE_10baseT_Half_BIT = 0, 707 ETHTOOL_LINK_MODE_10baseT_Full_BIT = 1, 708 ETHTOOL_LINK_MODE_100baseT_Half_BIT = 2, 709 ETHTOOL_LINK_MODE_100baseT_Full_BIT = 3, 710 ETHTOOL_LINK_MODE_1000baseT_Half_BIT = 4, 711 ETHTOOL_LINK_MODE_1000baseT_Full_BIT = 5, 712 ETHTOOL_LINK_MODE_Autoneg_BIT = 6, 713 ETHTOOL_LINK_MODE_TP_BIT = 7, 714 ETHTOOL_LINK_MODE_AUI_BIT = 8, 715 ETHTOOL_LINK_MODE_MII_BIT = 9, 716 ETHTOOL_LINK_MODE_FIBRE_BIT = 10, 717 ETHTOOL_LINK_MODE_BNC_BIT = 11, 718 ETHTOOL_LINK_MODE_10000baseT_Full_BIT = 12, 719 ETHTOOL_LINK_MODE_Pause_BIT = 13, 720 ETHTOOL_LINK_MODE_Asym_Pause_BIT = 14, 721 ETHTOOL_LINK_MODE_2500baseX_Full_BIT = 15, 722 ETHTOOL_LINK_MODE_Backplane_BIT = 16, 723 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT = 17, 724 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT = 18, 725 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT = 19, 726 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT = 20, 727 ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT = 21, 728 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT = 22, 729 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT = 23, 730 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT = 24, 731 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT = 25, 732 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT = 26, 733 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT = 27, 734 ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT = 28, 735 ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT = 29, 736 ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT = 30, 737 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31, 738 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32, 739 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33, 740 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT = 34, 741 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT = 35, 742 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT = 36, 743 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT = 37, 744 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT = 38, 745 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT = 39, 746 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT = 40, 747 ETHTOOL_LINK_MODE_1000baseX_Full_BIT = 41, 748 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT = 42, 749 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT = 43, 750 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT = 44, 751 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT = 45, 752 ETHTOOL_LINK_MODE_10000baseER_Full_BIT = 46, 753 ETHTOOL_LINK_MODE_2500baseT_Full_BIT = 47, 754 ETHTOOL_LINK_MODE_5000baseT_Full_BIT = 48, 755 ETHTOOL_LINK_MODE_FEC_NONE_BIT = 49, 756 ETHTOOL_LINK_MODE_FEC_RS_BIT = 50, 757 ETHTOOL_LINK_MODE_FEC_BASER_BIT = 51, 758 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT = 52, 759 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT = 53, 760 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT = 54, 761 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT = 55, 762 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT = 56, 763 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT = 57, 764 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT = 58, 765 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT = 59, 766 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60, 767 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT = 61, 768 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT = 62, 769 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT = 63, 770 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64, 771 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT = 65, 772 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66, 773 ETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67, 774 ETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68, 775 ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69, 776 ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70, 777 ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71, 778 ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72, 779 ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73, 780 ETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74, 781 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT = 75, 782 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT = 76, 783 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT = 77, 784 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT = 78, 785 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT = 79, 786 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT = 80, 787 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT = 81, 788 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82, 789 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT = 83, 790 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT = 84, 791 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT = 85, 792 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT = 86, 793 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87, 794 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88, 795 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89, 796 ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90, 797 ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91, 798 ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92, 799 ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT = 93, 800 ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT = 94, 801 ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT = 95, 802 ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96, 803 ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97, 804 ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98, 805 ETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99, 806 ETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100, 807 ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101, 808 ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102, 809 __ETHTOOL_LINK_MODE_MASK_NBITS 810 }; 811 #define __ETHTOOL_LINK_MODE_LEGACY_MASK(base_name) (1UL << (ETHTOOL_LINK_MODE_ ##base_name ##_BIT)) 812 #define SUPPORTED_10baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(10baseT_Half) 813 #define SUPPORTED_10baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10baseT_Full) 814 #define SUPPORTED_100baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(100baseT_Half) 815 #define SUPPORTED_100baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(100baseT_Full) 816 #define SUPPORTED_1000baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseT_Half) 817 #define SUPPORTED_1000baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseT_Full) 818 #define SUPPORTED_Autoneg __ETHTOOL_LINK_MODE_LEGACY_MASK(Autoneg) 819 #define SUPPORTED_TP __ETHTOOL_LINK_MODE_LEGACY_MASK(TP) 820 #define SUPPORTED_AUI __ETHTOOL_LINK_MODE_LEGACY_MASK(AUI) 821 #define SUPPORTED_MII __ETHTOOL_LINK_MODE_LEGACY_MASK(MII) 822 #define SUPPORTED_FIBRE __ETHTOOL_LINK_MODE_LEGACY_MASK(FIBRE) 823 #define SUPPORTED_BNC __ETHTOOL_LINK_MODE_LEGACY_MASK(BNC) 824 #define SUPPORTED_10000baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseT_Full) 825 #define SUPPORTED_Pause __ETHTOOL_LINK_MODE_LEGACY_MASK(Pause) 826 #define SUPPORTED_Asym_Pause __ETHTOOL_LINK_MODE_LEGACY_MASK(Asym_Pause) 827 #define SUPPORTED_2500baseX_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(2500baseX_Full) 828 #define SUPPORTED_Backplane __ETHTOOL_LINK_MODE_LEGACY_MASK(Backplane) 829 #define SUPPORTED_1000baseKX_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseKX_Full) 830 #define SUPPORTED_10000baseKX4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseKX4_Full) 831 #define SUPPORTED_10000baseKR_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseKR_Full) 832 #define SUPPORTED_10000baseR_FEC __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseR_FEC) 833 #define SUPPORTED_20000baseMLD2_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(20000baseMLD2_Full) 834 #define SUPPORTED_20000baseKR2_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(20000baseKR2_Full) 835 #define SUPPORTED_40000baseKR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseKR4_Full) 836 #define SUPPORTED_40000baseCR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseCR4_Full) 837 #define SUPPORTED_40000baseSR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseSR4_Full) 838 #define SUPPORTED_40000baseLR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseLR4_Full) 839 #define SUPPORTED_56000baseKR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseKR4_Full) 840 #define SUPPORTED_56000baseCR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseCR4_Full) 841 #define SUPPORTED_56000baseSR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseSR4_Full) 842 #define SUPPORTED_56000baseLR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseLR4_Full) 843 #define ADVERTISED_10baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(10baseT_Half) 844 #define ADVERTISED_10baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10baseT_Full) 845 #define ADVERTISED_100baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(100baseT_Half) 846 #define ADVERTISED_100baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(100baseT_Full) 847 #define ADVERTISED_1000baseT_Half __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseT_Half) 848 #define ADVERTISED_1000baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseT_Full) 849 #define ADVERTISED_Autoneg __ETHTOOL_LINK_MODE_LEGACY_MASK(Autoneg) 850 #define ADVERTISED_TP __ETHTOOL_LINK_MODE_LEGACY_MASK(TP) 851 #define ADVERTISED_AUI __ETHTOOL_LINK_MODE_LEGACY_MASK(AUI) 852 #define ADVERTISED_MII __ETHTOOL_LINK_MODE_LEGACY_MASK(MII) 853 #define ADVERTISED_FIBRE __ETHTOOL_LINK_MODE_LEGACY_MASK(FIBRE) 854 #define ADVERTISED_BNC __ETHTOOL_LINK_MODE_LEGACY_MASK(BNC) 855 #define ADVERTISED_10000baseT_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseT_Full) 856 #define ADVERTISED_Pause __ETHTOOL_LINK_MODE_LEGACY_MASK(Pause) 857 #define ADVERTISED_Asym_Pause __ETHTOOL_LINK_MODE_LEGACY_MASK(Asym_Pause) 858 #define ADVERTISED_2500baseX_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(2500baseX_Full) 859 #define ADVERTISED_Backplane __ETHTOOL_LINK_MODE_LEGACY_MASK(Backplane) 860 #define ADVERTISED_1000baseKX_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(1000baseKX_Full) 861 #define ADVERTISED_10000baseKX4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseKX4_Full) 862 #define ADVERTISED_10000baseKR_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseKR_Full) 863 #define ADVERTISED_10000baseR_FEC __ETHTOOL_LINK_MODE_LEGACY_MASK(10000baseR_FEC) 864 #define ADVERTISED_20000baseMLD2_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(20000baseMLD2_Full) 865 #define ADVERTISED_20000baseKR2_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(20000baseKR2_Full) 866 #define ADVERTISED_40000baseKR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseKR4_Full) 867 #define ADVERTISED_40000baseCR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseCR4_Full) 868 #define ADVERTISED_40000baseSR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseSR4_Full) 869 #define ADVERTISED_40000baseLR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(40000baseLR4_Full) 870 #define ADVERTISED_56000baseKR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseKR4_Full) 871 #define ADVERTISED_56000baseCR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseCR4_Full) 872 #define ADVERTISED_56000baseSR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseSR4_Full) 873 #define ADVERTISED_56000baseLR4_Full __ETHTOOL_LINK_MODE_LEGACY_MASK(56000baseLR4_Full) 874 #define SPEED_10 10 875 #define SPEED_100 100 876 #define SPEED_1000 1000 877 #define SPEED_2500 2500 878 #define SPEED_5000 5000 879 #define SPEED_10000 10000 880 #define SPEED_14000 14000 881 #define SPEED_20000 20000 882 #define SPEED_25000 25000 883 #define SPEED_40000 40000 884 #define SPEED_50000 50000 885 #define SPEED_56000 56000 886 #define SPEED_100000 100000 887 #define SPEED_200000 200000 888 #define SPEED_400000 400000 889 #define SPEED_800000 800000 890 #define SPEED_UNKNOWN - 1 891 #define DUPLEX_HALF 0x00 892 #define DUPLEX_FULL 0x01 893 #define DUPLEX_UNKNOWN 0xff 894 #define MASTER_SLAVE_CFG_UNSUPPORTED 0 895 #define MASTER_SLAVE_CFG_UNKNOWN 1 896 #define MASTER_SLAVE_CFG_MASTER_PREFERRED 2 897 #define MASTER_SLAVE_CFG_SLAVE_PREFERRED 3 898 #define MASTER_SLAVE_CFG_MASTER_FORCE 4 899 #define MASTER_SLAVE_CFG_SLAVE_FORCE 5 900 #define MASTER_SLAVE_STATE_UNSUPPORTED 0 901 #define MASTER_SLAVE_STATE_UNKNOWN 1 902 #define MASTER_SLAVE_STATE_MASTER 2 903 #define MASTER_SLAVE_STATE_SLAVE 3 904 #define MASTER_SLAVE_STATE_ERR 4 905 #define RATE_MATCH_NONE 0 906 #define RATE_MATCH_PAUSE 1 907 #define RATE_MATCH_CRS 2 908 #define RATE_MATCH_OPEN_LOOP 3 909 #define PORT_TP 0x00 910 #define PORT_AUI 0x01 911 #define PORT_MII 0x02 912 #define PORT_FIBRE 0x03 913 #define PORT_BNC 0x04 914 #define PORT_DA 0x05 915 #define PORT_NONE 0xef 916 #define PORT_OTHER 0xff 917 #define XCVR_INTERNAL 0x00 918 #define XCVR_EXTERNAL 0x01 919 #define XCVR_DUMMY1 0x02 920 #define XCVR_DUMMY2 0x03 921 #define XCVR_DUMMY3 0x04 922 #define AUTONEG_DISABLE 0x00 923 #define AUTONEG_ENABLE 0x01 924 #define ETH_TP_MDI_INVALID 0x00 925 #define ETH_TP_MDI 0x01 926 #define ETH_TP_MDI_X 0x02 927 #define ETH_TP_MDI_AUTO 0x03 928 #define WAKE_PHY (1 << 0) 929 #define WAKE_UCAST (1 << 1) 930 #define WAKE_MCAST (1 << 2) 931 #define WAKE_BCAST (1 << 3) 932 #define WAKE_ARP (1 << 4) 933 #define WAKE_MAGIC (1 << 5) 934 #define WAKE_MAGICSECURE (1 << 6) 935 #define WAKE_FILTER (1 << 7) 936 #define WOL_MODE_COUNT 8 937 #define RXH_XFRM_SYM_XOR (1 << 0) 938 #define RXH_XFRM_NO_CHANGE 0xff 939 #define TCP_V4_FLOW 0x01 940 #define UDP_V4_FLOW 0x02 941 #define SCTP_V4_FLOW 0x03 942 #define AH_ESP_V4_FLOW 0x04 943 #define TCP_V6_FLOW 0x05 944 #define UDP_V6_FLOW 0x06 945 #define SCTP_V6_FLOW 0x07 946 #define AH_ESP_V6_FLOW 0x08 947 #define AH_V4_FLOW 0x09 948 #define ESP_V4_FLOW 0x0a 949 #define AH_V6_FLOW 0x0b 950 #define ESP_V6_FLOW 0x0c 951 #define IPV4_USER_FLOW 0x0d 952 #define IP_USER_FLOW IPV4_USER_FLOW 953 #define IPV6_USER_FLOW 0x0e 954 #define IPV4_FLOW 0x10 955 #define IPV6_FLOW 0x11 956 #define ETHER_FLOW 0x12 957 #define GTPU_V4_FLOW 0x13 958 #define GTPU_V6_FLOW 0x14 959 #define GTPC_V4_FLOW 0x15 960 #define GTPC_V6_FLOW 0x16 961 #define GTPC_TEID_V4_FLOW 0x17 962 #define GTPC_TEID_V6_FLOW 0x18 963 #define GTPU_EH_V4_FLOW 0x19 964 #define GTPU_EH_V6_FLOW 0x1a 965 #define GTPU_UL_V4_FLOW 0x1b 966 #define GTPU_UL_V6_FLOW 0x1c 967 #define GTPU_DL_V4_FLOW 0x1d 968 #define GTPU_DL_V6_FLOW 0x1e 969 #define FLOW_EXT 0x80000000 970 #define FLOW_MAC_EXT 0x40000000 971 #define FLOW_RSS 0x20000000 972 #define RXH_L2DA (1 << 1) 973 #define RXH_VLAN (1 << 2) 974 #define RXH_L3_PROTO (1 << 3) 975 #define RXH_IP_SRC (1 << 4) 976 #define RXH_IP_DST (1 << 5) 977 #define RXH_L4_B_0_1 (1 << 6) 978 #define RXH_L4_B_2_3 (1 << 7) 979 #define RXH_GTP_TEID (1 << 8) 980 #define RXH_DISCARD (1 << 31) 981 #define RX_CLS_FLOW_DISC 0xffffffffffffffffULL 982 #define RX_CLS_FLOW_WAKE 0xfffffffffffffffeULL 983 #define RX_CLS_LOC_SPECIAL 0x80000000 984 #define RX_CLS_LOC_ANY 0xffffffff 985 #define RX_CLS_LOC_FIRST 0xfffffffe 986 #define RX_CLS_LOC_LAST 0xfffffffd 987 #define ETH_MODULE_SFF_8079 0x1 988 #define ETH_MODULE_SFF_8079_LEN 256 989 #define ETH_MODULE_SFF_8472 0x2 990 #define ETH_MODULE_SFF_8472_LEN 512 991 #define ETH_MODULE_SFF_8636 0x3 992 #define ETH_MODULE_SFF_8636_LEN 256 993 #define ETH_MODULE_SFF_8436 0x4 994 #define ETH_MODULE_SFF_8436_LEN 256 995 #define ETH_MODULE_SFF_8636_MAX_LEN 640 996 #define ETH_MODULE_SFF_8436_MAX_LEN 640 997 enum ethtool_reset_flags { 998 ETH_RESET_MGMT = 1 << 0, 999 ETH_RESET_IRQ = 1 << 1, 1000 ETH_RESET_DMA = 1 << 2, 1001 ETH_RESET_FILTER = 1 << 3, 1002 ETH_RESET_OFFLOAD = 1 << 4, 1003 ETH_RESET_MAC = 1 << 5, 1004 ETH_RESET_PHY = 1 << 6, 1005 ETH_RESET_RAM = 1 << 7, 1006 ETH_RESET_AP = 1 << 8, 1007 ETH_RESET_DEDICATED = 0x0000ffff, 1008 ETH_RESET_ALL = 0xffffffff, 1009 }; 1010 #define ETH_RESET_SHARED_SHIFT 16 1011 struct ethtool_link_settings { 1012 __u32 cmd; 1013 __u32 speed; 1014 __u8 duplex; 1015 __u8 port; 1016 __u8 phy_address; 1017 __u8 autoneg; 1018 __u8 mdio_support; 1019 __u8 eth_tp_mdix; 1020 __u8 eth_tp_mdix_ctrl; 1021 __s8 link_mode_masks_nwords; 1022 __u8 transceiver; 1023 __u8 master_slave_cfg; 1024 __u8 master_slave_state; 1025 __u8 rate_matching; 1026 __u32 reserved[7]; 1027 __u32 link_mode_masks[]; 1028 }; 1029 #endif 1030