1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __AMDGPU_DRM_H__ 8 #define __AMDGPU_DRM_H__ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define DRM_AMDGPU_GEM_CREATE 0x00 14 #define DRM_AMDGPU_GEM_MMAP 0x01 15 #define DRM_AMDGPU_CTX 0x02 16 #define DRM_AMDGPU_BO_LIST 0x03 17 #define DRM_AMDGPU_CS 0x04 18 #define DRM_AMDGPU_INFO 0x05 19 #define DRM_AMDGPU_GEM_METADATA 0x06 20 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 21 #define DRM_AMDGPU_GEM_VA 0x08 22 #define DRM_AMDGPU_WAIT_CS 0x09 23 #define DRM_AMDGPU_GEM_OP 0x10 24 #define DRM_AMDGPU_GEM_USERPTR 0x11 25 #define DRM_AMDGPU_WAIT_FENCES 0x12 26 #define DRM_AMDGPU_VM 0x13 27 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 28 #define DRM_AMDGPU_SCHED 0x15 29 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 30 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 31 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 32 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 33 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 34 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 35 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 36 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 37 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 38 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 39 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 40 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 41 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 42 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 43 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 44 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 45 #define AMDGPU_GEM_DOMAIN_CPU 0x1 46 #define AMDGPU_GEM_DOMAIN_GTT 0x2 47 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 48 #define AMDGPU_GEM_DOMAIN_GDS 0x8 49 #define AMDGPU_GEM_DOMAIN_GWS 0x10 50 #define AMDGPU_GEM_DOMAIN_OA 0x20 51 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 52 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | AMDGPU_GEM_DOMAIN_DOORBELL) 53 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 54 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 55 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 56 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 57 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 58 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 59 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 60 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 61 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 62 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 63 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 64 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 65 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 66 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 67 #define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) 68 #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) 69 struct drm_amdgpu_gem_create_in { 70 __u64 bo_size; 71 __u64 alignment; 72 __u64 domains; 73 __u64 domain_flags; 74 }; 75 struct drm_amdgpu_gem_create_out { 76 __u32 handle; 77 __u32 _pad; 78 }; 79 union drm_amdgpu_gem_create { 80 struct drm_amdgpu_gem_create_in in; 81 struct drm_amdgpu_gem_create_out out; 82 }; 83 #define AMDGPU_BO_LIST_OP_CREATE 0 84 #define AMDGPU_BO_LIST_OP_DESTROY 1 85 #define AMDGPU_BO_LIST_OP_UPDATE 2 86 struct drm_amdgpu_bo_list_in { 87 __u32 operation; 88 __u32 list_handle; 89 __u32 bo_number; 90 __u32 bo_info_size; 91 __u64 bo_info_ptr; 92 }; 93 struct drm_amdgpu_bo_list_entry { 94 __u32 bo_handle; 95 __u32 bo_priority; 96 }; 97 struct drm_amdgpu_bo_list_out { 98 __u32 list_handle; 99 __u32 _pad; 100 }; 101 union drm_amdgpu_bo_list { 102 struct drm_amdgpu_bo_list_in in; 103 struct drm_amdgpu_bo_list_out out; 104 }; 105 #define AMDGPU_CTX_OP_ALLOC_CTX 1 106 #define AMDGPU_CTX_OP_FREE_CTX 2 107 #define AMDGPU_CTX_OP_QUERY_STATE 3 108 #define AMDGPU_CTX_OP_QUERY_STATE2 4 109 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 110 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 111 #define AMDGPU_CTX_NO_RESET 0 112 #define AMDGPU_CTX_GUILTY_RESET 1 113 #define AMDGPU_CTX_INNOCENT_RESET 2 114 #define AMDGPU_CTX_UNKNOWN_RESET 3 115 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1 << 0) 116 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1 << 1) 117 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1 << 2) 118 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1 << 3) 119 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1 << 4) 120 #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1 << 5) 121 #define AMDGPU_CTX_PRIORITY_UNSET - 2048 122 #define AMDGPU_CTX_PRIORITY_VERY_LOW - 1023 123 #define AMDGPU_CTX_PRIORITY_LOW - 512 124 #define AMDGPU_CTX_PRIORITY_NORMAL 0 125 #define AMDGPU_CTX_PRIORITY_HIGH 512 126 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 127 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 128 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 129 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 130 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 131 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 132 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 133 struct drm_amdgpu_ctx_in { 134 __u32 op; 135 __u32 flags; 136 __u32 ctx_id; 137 __s32 priority; 138 }; 139 union drm_amdgpu_ctx_out { 140 struct { 141 __u32 ctx_id; 142 __u32 _pad; 143 } alloc; 144 struct { 145 __u64 flags; 146 __u32 hangs; 147 __u32 reset_status; 148 } state; 149 struct { 150 __u32 flags; 151 __u32 _pad; 152 } pstate; 153 }; 154 union drm_amdgpu_ctx { 155 struct drm_amdgpu_ctx_in in; 156 union drm_amdgpu_ctx_out out; 157 }; 158 #define AMDGPU_VM_OP_RESERVE_VMID 1 159 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 160 struct drm_amdgpu_vm_in { 161 __u32 op; 162 __u32 flags; 163 }; 164 struct drm_amdgpu_vm_out { 165 __u64 flags; 166 }; 167 union drm_amdgpu_vm { 168 struct drm_amdgpu_vm_in in; 169 struct drm_amdgpu_vm_out out; 170 }; 171 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 172 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 173 struct drm_amdgpu_sched_in { 174 __u32 op; 175 __u32 fd; 176 __s32 priority; 177 __u32 ctx_id; 178 }; 179 union drm_amdgpu_sched { 180 struct drm_amdgpu_sched_in in; 181 }; 182 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 183 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 184 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 185 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 186 struct drm_amdgpu_gem_userptr { 187 __u64 addr; 188 __u64 size; 189 __u32 flags; 190 __u32 handle; 191 }; 192 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 193 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 194 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 195 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 196 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 197 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 198 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 199 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 200 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 201 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 202 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 203 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 204 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 205 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 206 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 207 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 208 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 209 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 210 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 211 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 212 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 213 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 214 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 215 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 216 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 217 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 218 #define AMDGPU_TILING_SCANOUT_SHIFT 63 219 #define AMDGPU_TILING_SCANOUT_MASK 0x1 220 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 221 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 222 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 223 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 224 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 225 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 226 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 227 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f 228 #define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) 229 #define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) 230 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 231 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 232 struct drm_amdgpu_gem_metadata { 233 __u32 handle; 234 __u32 op; 235 struct { 236 __u64 flags; 237 __u64 tiling_info; 238 __u32 data_size_bytes; 239 __u32 data[64]; 240 } data; 241 }; 242 struct drm_amdgpu_gem_mmap_in { 243 __u32 handle; 244 __u32 _pad; 245 }; 246 struct drm_amdgpu_gem_mmap_out { 247 __u64 addr_ptr; 248 }; 249 union drm_amdgpu_gem_mmap { 250 struct drm_amdgpu_gem_mmap_in in; 251 struct drm_amdgpu_gem_mmap_out out; 252 }; 253 struct drm_amdgpu_gem_wait_idle_in { 254 __u32 handle; 255 __u32 flags; 256 __u64 timeout; 257 }; 258 struct drm_amdgpu_gem_wait_idle_out { 259 __u32 status; 260 __u32 domain; 261 }; 262 union drm_amdgpu_gem_wait_idle { 263 struct drm_amdgpu_gem_wait_idle_in in; 264 struct drm_amdgpu_gem_wait_idle_out out; 265 }; 266 struct drm_amdgpu_wait_cs_in { 267 __u64 handle; 268 __u64 timeout; 269 __u32 ip_type; 270 __u32 ip_instance; 271 __u32 ring; 272 __u32 ctx_id; 273 }; 274 struct drm_amdgpu_wait_cs_out { 275 __u64 status; 276 }; 277 union drm_amdgpu_wait_cs { 278 struct drm_amdgpu_wait_cs_in in; 279 struct drm_amdgpu_wait_cs_out out; 280 }; 281 struct drm_amdgpu_fence { 282 __u32 ctx_id; 283 __u32 ip_type; 284 __u32 ip_instance; 285 __u32 ring; 286 __u64 seq_no; 287 }; 288 struct drm_amdgpu_wait_fences_in { 289 __u64 fences; 290 __u32 fence_count; 291 __u32 wait_all; 292 __u64 timeout_ns; 293 }; 294 struct drm_amdgpu_wait_fences_out { 295 __u32 status; 296 __u32 first_signaled; 297 }; 298 union drm_amdgpu_wait_fences { 299 struct drm_amdgpu_wait_fences_in in; 300 struct drm_amdgpu_wait_fences_out out; 301 }; 302 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 303 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 304 struct drm_amdgpu_gem_op { 305 __u32 handle; 306 __u32 op; 307 __u64 value; 308 }; 309 #define AMDGPU_VA_OP_MAP 1 310 #define AMDGPU_VA_OP_UNMAP 2 311 #define AMDGPU_VA_OP_CLEAR 3 312 #define AMDGPU_VA_OP_REPLACE 4 313 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 314 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 315 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 316 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 317 #define AMDGPU_VM_PAGE_PRT (1 << 4) 318 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 319 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 320 #define AMDGPU_VM_MTYPE_NC (1 << 5) 321 #define AMDGPU_VM_MTYPE_WC (2 << 5) 322 #define AMDGPU_VM_MTYPE_CC (3 << 5) 323 #define AMDGPU_VM_MTYPE_UC (4 << 5) 324 #define AMDGPU_VM_MTYPE_RW (5 << 5) 325 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 326 struct drm_amdgpu_gem_va { 327 __u32 handle; 328 __u32 _pad; 329 __u32 operation; 330 __u32 flags; 331 __u64 va_address; 332 __u64 offset_in_bo; 333 __u64 map_size; 334 }; 335 #define AMDGPU_HW_IP_GFX 0 336 #define AMDGPU_HW_IP_COMPUTE 1 337 #define AMDGPU_HW_IP_DMA 2 338 #define AMDGPU_HW_IP_UVD 3 339 #define AMDGPU_HW_IP_VCE 4 340 #define AMDGPU_HW_IP_UVD_ENC 5 341 #define AMDGPU_HW_IP_VCN_DEC 6 342 #define AMDGPU_HW_IP_VCN_ENC 7 343 #define AMDGPU_HW_IP_VCN_JPEG 8 344 #define AMDGPU_HW_IP_VPE 9 345 #define AMDGPU_HW_IP_NUM 10 346 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 347 #define AMDGPU_CHUNK_ID_IB 0x01 348 #define AMDGPU_CHUNK_ID_FENCE 0x02 349 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 350 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 351 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 352 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 353 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 354 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 355 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 356 #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 357 struct drm_amdgpu_cs_chunk { 358 __u32 chunk_id; 359 __u32 length_dw; 360 __u64 chunk_data; 361 }; 362 struct drm_amdgpu_cs_in { 363 __u32 ctx_id; 364 __u32 bo_list_handle; 365 __u32 num_chunks; 366 __u32 flags; 367 __u64 chunks; 368 }; 369 struct drm_amdgpu_cs_out { 370 __u64 handle; 371 }; 372 union drm_amdgpu_cs { 373 struct drm_amdgpu_cs_in in; 374 struct drm_amdgpu_cs_out out; 375 }; 376 #define AMDGPU_IB_FLAG_CE (1 << 0) 377 #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) 378 #define AMDGPU_IB_FLAG_PREEMPT (1 << 2) 379 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 380 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 381 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 382 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 383 struct drm_amdgpu_cs_chunk_ib { 384 __u32 _pad; 385 __u32 flags; 386 __u64 va_start; 387 __u32 ib_bytes; 388 __u32 ip_type; 389 __u32 ip_instance; 390 __u32 ring; 391 }; 392 struct drm_amdgpu_cs_chunk_dep { 393 __u32 ip_type; 394 __u32 ip_instance; 395 __u32 ring; 396 __u32 ctx_id; 397 __u64 handle; 398 }; 399 struct drm_amdgpu_cs_chunk_fence { 400 __u32 handle; 401 __u32 offset; 402 }; 403 struct drm_amdgpu_cs_chunk_sem { 404 __u32 handle; 405 }; 406 struct drm_amdgpu_cs_chunk_syncobj { 407 __u32 handle; 408 __u32 flags; 409 __u64 point; 410 }; 411 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 412 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 413 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 414 union drm_amdgpu_fence_to_handle { 415 struct { 416 struct drm_amdgpu_fence fence; 417 __u32 what; 418 __u32 pad; 419 } in; 420 struct { 421 __u32 handle; 422 } out; 423 }; 424 struct drm_amdgpu_cs_chunk_data { 425 union { 426 struct drm_amdgpu_cs_chunk_ib ib_data; 427 struct drm_amdgpu_cs_chunk_fence fence_data; 428 }; 429 }; 430 #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 431 struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 432 __u64 shadow_va; 433 __u64 csa_va; 434 __u64 gds_va; 435 __u64 flags; 436 }; 437 #define AMDGPU_IDS_FLAGS_FUSION 0x1 438 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 439 #define AMDGPU_IDS_FLAGS_TMZ 0x4 440 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 441 #define AMDGPU_INFO_ACCEL_WORKING 0x00 442 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 443 #define AMDGPU_INFO_HW_IP_INFO 0x02 444 #define AMDGPU_INFO_HW_IP_COUNT 0x03 445 #define AMDGPU_INFO_TIMESTAMP 0x05 446 #define AMDGPU_INFO_FW_VERSION 0x0e 447 #define AMDGPU_INFO_FW_VCE 0x1 448 #define AMDGPU_INFO_FW_UVD 0x2 449 #define AMDGPU_INFO_FW_GMC 0x03 450 #define AMDGPU_INFO_FW_GFX_ME 0x04 451 #define AMDGPU_INFO_FW_GFX_PFP 0x05 452 #define AMDGPU_INFO_FW_GFX_CE 0x06 453 #define AMDGPU_INFO_FW_GFX_RLC 0x07 454 #define AMDGPU_INFO_FW_GFX_MEC 0x08 455 #define AMDGPU_INFO_FW_SMC 0x0a 456 #define AMDGPU_INFO_FW_SDMA 0x0b 457 #define AMDGPU_INFO_FW_SOS 0x0c 458 #define AMDGPU_INFO_FW_ASD 0x0d 459 #define AMDGPU_INFO_FW_VCN 0x0e 460 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 461 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 462 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 463 #define AMDGPU_INFO_FW_DMCU 0x12 464 #define AMDGPU_INFO_FW_TA 0x13 465 #define AMDGPU_INFO_FW_DMCUB 0x14 466 #define AMDGPU_INFO_FW_TOC 0x15 467 #define AMDGPU_INFO_FW_CAP 0x16 468 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 469 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 470 #define AMDGPU_INFO_FW_MES_KIQ 0x19 471 #define AMDGPU_INFO_FW_MES 0x1a 472 #define AMDGPU_INFO_FW_IMU 0x1b 473 #define AMDGPU_INFO_FW_VPE 0x1c 474 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 475 #define AMDGPU_INFO_VRAM_USAGE 0x10 476 #define AMDGPU_INFO_GTT_USAGE 0x11 477 #define AMDGPU_INFO_GDS_CONFIG 0x13 478 #define AMDGPU_INFO_VRAM_GTT 0x14 479 #define AMDGPU_INFO_READ_MMR_REG 0x15 480 #define AMDGPU_INFO_DEV_INFO 0x16 481 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 482 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 483 #define AMDGPU_INFO_MEMORY 0x19 484 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 485 #define AMDGPU_INFO_VBIOS 0x1B 486 #define AMDGPU_INFO_VBIOS_SIZE 0x1 487 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 488 #define AMDGPU_INFO_VBIOS_INFO 0x3 489 #define AMDGPU_INFO_NUM_HANDLES 0x1C 490 #define AMDGPU_INFO_SENSOR 0x1D 491 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 492 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 493 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 494 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 495 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 496 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 497 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 498 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 499 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 500 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 501 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 502 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc 503 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 504 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 505 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 506 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 507 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 508 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 509 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 510 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 511 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 512 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 513 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 514 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 515 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 516 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 517 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 518 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 519 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 520 #define AMDGPU_INFO_VIDEO_CAPS 0x21 521 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 522 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 523 #define AMDGPU_INFO_MAX_IBS 0x22 524 #define AMDGPU_INFO_GPUVM_FAULT 0x23 525 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 526 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 527 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 528 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 529 struct drm_amdgpu_query_fw { 530 __u32 fw_type; 531 __u32 ip_instance; 532 __u32 index; 533 __u32 _pad; 534 }; 535 struct drm_amdgpu_info { 536 __u64 return_pointer; 537 __u32 return_size; 538 __u32 query; 539 union { 540 struct { 541 __u32 id; 542 __u32 _pad; 543 } mode_crtc; 544 struct { 545 __u32 type; 546 __u32 ip_instance; 547 } query_hw_ip; 548 struct { 549 __u32 dword_offset; 550 __u32 count; 551 __u32 instance; 552 __u32 flags; 553 } read_mmr_reg; 554 struct drm_amdgpu_query_fw query_fw; 555 struct { 556 __u32 type; 557 __u32 offset; 558 } vbios_info; 559 struct { 560 __u32 type; 561 } sensor_info; 562 struct { 563 __u32 type; 564 } video_cap; 565 }; 566 }; 567 struct drm_amdgpu_info_gds { 568 __u32 gds_gfx_partition_size; 569 __u32 compute_partition_size; 570 __u32 gds_total_size; 571 __u32 gws_per_gfx_partition; 572 __u32 gws_per_compute_partition; 573 __u32 oa_per_gfx_partition; 574 __u32 oa_per_compute_partition; 575 __u32 _pad; 576 }; 577 struct drm_amdgpu_info_vram_gtt { 578 __u64 vram_size; 579 __u64 vram_cpu_accessible_size; 580 __u64 gtt_size; 581 }; 582 struct drm_amdgpu_heap_info { 583 __u64 total_heap_size; 584 __u64 usable_heap_size; 585 __u64 heap_usage; 586 __u64 max_allocation; 587 }; 588 struct drm_amdgpu_memory_info { 589 struct drm_amdgpu_heap_info vram; 590 struct drm_amdgpu_heap_info cpu_accessible_vram; 591 struct drm_amdgpu_heap_info gtt; 592 }; 593 struct drm_amdgpu_info_firmware { 594 __u32 ver; 595 __u32 feature; 596 }; 597 struct drm_amdgpu_info_vbios { 598 __u8 name[64]; 599 __u8 vbios_pn[64]; 600 __u32 version; 601 __u32 pad; 602 __u8 vbios_ver_str[32]; 603 __u8 date[32]; 604 }; 605 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 606 #define AMDGPU_VRAM_TYPE_GDDR1 1 607 #define AMDGPU_VRAM_TYPE_DDR2 2 608 #define AMDGPU_VRAM_TYPE_GDDR3 3 609 #define AMDGPU_VRAM_TYPE_GDDR4 4 610 #define AMDGPU_VRAM_TYPE_GDDR5 5 611 #define AMDGPU_VRAM_TYPE_HBM 6 612 #define AMDGPU_VRAM_TYPE_DDR3 7 613 #define AMDGPU_VRAM_TYPE_DDR4 8 614 #define AMDGPU_VRAM_TYPE_GDDR6 9 615 #define AMDGPU_VRAM_TYPE_DDR5 10 616 #define AMDGPU_VRAM_TYPE_LPDDR4 11 617 #define AMDGPU_VRAM_TYPE_LPDDR5 12 618 struct drm_amdgpu_info_device { 619 __u32 device_id; 620 __u32 chip_rev; 621 __u32 external_rev; 622 __u32 pci_rev; 623 __u32 family; 624 __u32 num_shader_engines; 625 __u32 num_shader_arrays_per_engine; 626 __u32 gpu_counter_freq; 627 __u64 max_engine_clock; 628 __u64 max_memory_clock; 629 __u32 cu_active_number; 630 __u32 cu_ao_mask; 631 __u32 cu_bitmap[4][4]; 632 __u32 enabled_rb_pipes_mask; 633 __u32 num_rb_pipes; 634 __u32 num_hw_gfx_contexts; 635 __u32 pcie_gen; 636 __u64 ids_flags; 637 __u64 virtual_address_offset; 638 __u64 virtual_address_max; 639 __u32 virtual_address_alignment; 640 __u32 pte_fragment_size; 641 __u32 gart_page_size; 642 __u32 ce_ram_size; 643 __u32 vram_type; 644 __u32 vram_bit_width; 645 __u32 vce_harvest_config; 646 __u32 gc_double_offchip_lds_buf; 647 __u64 prim_buf_gpu_addr; 648 __u64 pos_buf_gpu_addr; 649 __u64 cntl_sb_buf_gpu_addr; 650 __u64 param_buf_gpu_addr; 651 __u32 prim_buf_size; 652 __u32 pos_buf_size; 653 __u32 cntl_sb_buf_size; 654 __u32 param_buf_size; 655 __u32 wave_front_size; 656 __u32 num_shader_visible_vgprs; 657 __u32 num_cu_per_sh; 658 __u32 num_tcc_blocks; 659 __u32 gs_vgt_table_depth; 660 __u32 gs_prim_buffer_depth; 661 __u32 max_gs_waves_per_vgt; 662 __u32 pcie_num_lanes; 663 __u32 cu_ao_bitmap[4][4]; 664 __u64 high_va_offset; 665 __u64 high_va_max; 666 __u32 pa_sc_tile_steering_override; 667 __u64 tcc_disabled_mask; 668 __u64 min_engine_clock; 669 __u64 min_memory_clock; 670 __u32 tcp_cache_size; 671 __u32 num_sqc_per_wgp; 672 __u32 sqc_data_cache_size; 673 __u32 sqc_inst_cache_size; 674 __u32 gl1c_cache_size; 675 __u32 gl2c_cache_size; 676 __u64 mall_size; 677 __u32 enabled_rb_pipes_mask_hi; 678 __u32 shadow_size; 679 __u32 shadow_alignment; 680 __u32 csa_size; 681 __u32 csa_alignment; 682 }; 683 struct drm_amdgpu_info_hw_ip { 684 __u32 hw_ip_version_major; 685 __u32 hw_ip_version_minor; 686 __u64 capabilities_flags; 687 __u32 ib_start_alignment; 688 __u32 ib_size_alignment; 689 __u32 available_rings; 690 __u32 ip_discovery_version; 691 }; 692 struct drm_amdgpu_info_num_handles { 693 __u32 uvd_max_handles; 694 __u32 uvd_used_handles; 695 }; 696 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 697 struct drm_amdgpu_info_vce_clock_table_entry { 698 __u32 sclk; 699 __u32 mclk; 700 __u32 eclk; 701 __u32 pad; 702 }; 703 struct drm_amdgpu_info_vce_clock_table { 704 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 705 __u32 num_valid_entries; 706 __u32 pad; 707 }; 708 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 709 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 710 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 711 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 712 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 713 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 714 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 715 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 716 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 717 struct drm_amdgpu_info_video_codec_info { 718 __u32 valid; 719 __u32 max_width; 720 __u32 max_height; 721 __u32 max_pixels_per_frame; 722 __u32 max_level; 723 __u32 pad; 724 }; 725 struct drm_amdgpu_info_video_caps { 726 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 727 }; 728 #define AMDGPU_VMHUB_TYPE_MASK 0xff 729 #define AMDGPU_VMHUB_TYPE_SHIFT 0 730 #define AMDGPU_VMHUB_TYPE_GFX 0 731 #define AMDGPU_VMHUB_TYPE_MM0 1 732 #define AMDGPU_VMHUB_TYPE_MM1 2 733 #define AMDGPU_VMHUB_IDX_MASK 0xff00 734 #define AMDGPU_VMHUB_IDX_SHIFT 8 735 struct drm_amdgpu_info_gpuvm_fault { 736 __u64 addr; 737 __u32 status; 738 __u32 vmhub; 739 }; 740 #define AMDGPU_FAMILY_UNKNOWN 0 741 #define AMDGPU_FAMILY_SI 110 742 #define AMDGPU_FAMILY_CI 120 743 #define AMDGPU_FAMILY_KV 125 744 #define AMDGPU_FAMILY_VI 130 745 #define AMDGPU_FAMILY_CZ 135 746 #define AMDGPU_FAMILY_AI 141 747 #define AMDGPU_FAMILY_RV 142 748 #define AMDGPU_FAMILY_NV 143 749 #define AMDGPU_FAMILY_VGH 144 750 #define AMDGPU_FAMILY_GC_11_0_0 145 751 #define AMDGPU_FAMILY_YC 146 752 #define AMDGPU_FAMILY_GC_11_0_1 148 753 #define AMDGPU_FAMILY_GC_10_3_6 149 754 #define AMDGPU_FAMILY_GC_10_3_7 151 755 #define AMDGPU_FAMILY_GC_11_5_0 150 756 #define AMDGPU_FAMILY_GC_12_0_0 152 757 struct drm_color_ctm_3x4 { 758 __u64 matrix[12]; 759 }; 760 #ifdef __cplusplus 761 } 762 #endif 763 #endif 764