1# Copyright (C) 2016 The Android Open Source Project 2# 3# Licensed under the Apache License, Version 2.0 (the "License"); 4# you may not use this file except in compliance with the License. 5# You may obtain a copy of the License at 6# 7# http://www.apache.org/licenses/LICENSE-2.0 8# 9# Unless required by applicable law or agreed to in writing, software 10# distributed under the License is distributed on an "AS IS" BASIS, 11# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12# See the License for the specific language governing permissions and 13# limitations under the License. 14 15.class public LIrreducibleLoop; 16 17.super Ljava/lang/Object; 18 19# Test case where liveness analysis produces linear order where loop blocks are 20# not adjacent. This revealed a bug in our SSA builder, where a dead loop phi would 21# be replaced by its incoming input during SsaRedundantPhiElimination. 22 23# Check that the outer loop suspend check environment only has the two parameter vregs. 24## CHECK-START: int IrreducibleLoop.liveness(int, int) builder (after) 25## CHECK-DAG: <<Phi1:i\d+>> Phi reg:3 loop:{{B\d+}} irreducible:false 26## CHECK-DAG: <<Phi2:i\d+>> Phi reg:4 loop:{{B\d+}} irreducible:false 27## CHECK-DAG: SuspendCheck env:[[_,_,_,<<Phi1>>,<<Phi2>>]] loop:{{B\d+}} irreducible:false 28 29# Check that the linear order has non-adjacent loop blocks. 30## CHECK-START: int IrreducibleLoop.liveness(int, int) liveness (after) 31## CHECK-DAG: Mul liveness:<<LPreEntry2:\d+>> 32## CHECK-DAG: Add liveness:<<LBackEdge1:\d+>> 33## CHECK-EVAL: <<LBackEdge1>> < <<LPreEntry2>> 34 35.method public static liveness(II)I 36 .registers 5 37 38 const-string v1, "MyString" 39 40 :header1 41 if-eqz p0, :body1 42 43 :exit 44 return p0 45 46 :body1 47 # The test will generate an incorrect linear order when the following IF swaps 48 # its successors. To do that, load a boolean value and compare NotEqual to 1. 49 sget-boolean v2, LIrreducibleLoop;->f:Z 50 const v3, 1 51 if-ne v2, v3, :pre_header2 52 53 :pre_entry2 54 # Add a marker on the irreducible loop entry. Here we use p1 because p0 is a 55 # known constant and we eliminate the Mul otherwise. 56 mul-int/2addr p1, p1 57 goto :back_edge2 58 59 :back_edge2 60 goto :header2 61 62 :header2 63 if-eqz p0, :back_edge2 64 65 :back_edge1 66 # Add a marker on the outer loop back edge. Here we use p1 because p0 is a 67 # known constant and we eliminate the Add otherwise. 68 add-int/2addr p1, p1 69 # Set a wide register, to have v1 undefined at the back edge. 70 const-wide/16 v0, 0x1 71 goto :header1 72 73 :pre_header2 74 goto :header2 75.end method 76 77.field public static f:Z 78