1 /*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #ifndef ART_LIBARTBASE_ARCH_INSTRUCTION_SET_H_
18 #define ART_LIBARTBASE_ARCH_INSTRUCTION_SET_H_
19
20 #include <iosfwd>
21 #include <string>
22 #include <vector>
23
24 #include "base/macros.h"
25 #include "base/pointer_size.h"
26
27 namespace art {
28
29 enum class InstructionSet {
30 kNone,
31 kArm,
32 kArm64,
33 kThumb2,
34 kRiscv64,
35 kX86,
36 kX86_64,
37 kLast = kX86_64
38 };
39 std::ostream& operator<<(std::ostream& os, InstructionSet rhs);
40
41 // kRuntimeISA must match the ISA of the machine that ART will be run on. This ISA will be used for
42 // the native context, native stack frame and native ABI.
43 #if defined(__arm__)
44 static constexpr InstructionSet kRuntimeISA = InstructionSet::kArm;
45 #elif defined(__aarch64__)
46 static constexpr InstructionSet kRuntimeISA = InstructionSet::kArm64;
47 #elif defined (__riscv)
48 static constexpr InstructionSet kRuntimeISA = InstructionSet::kRiscv64;
49 #elif defined(__i386__)
50 static constexpr InstructionSet kRuntimeISA = InstructionSet::kX86;
51 #elif defined(__x86_64__)
52 static constexpr InstructionSet kRuntimeISA = InstructionSet::kX86_64;
53 #else
54 static constexpr InstructionSet kRuntimeISA = InstructionSet::kNone;
55 #endif
56
57 // The ISA that ART will generate quick code for, i.e.: that java code will be compiled to. This
58 // ISA will be used for the quick context, quick stack frame and quick ABI. This may differ from
59 // kRuntimeISA if the simulator is in use where, for example, the native runtime is x86-64 but the
60 // quick code generated by the compiler is Arm64.
61 static constexpr InstructionSet kRuntimeQuickCodeISA = kRuntimeISA;
62
63 // Architecture-specific pointer sizes
64 static constexpr PointerSize kArmPointerSize = PointerSize::k32;
65 static constexpr PointerSize kArm64PointerSize = PointerSize::k64;
66 static constexpr PointerSize kRiscv64PointerSize = PointerSize::k64;
67 static constexpr PointerSize kX86PointerSize = PointerSize::k32;
68 static constexpr PointerSize kX86_64PointerSize = PointerSize::k64;
69
70 // ARM64 default SVE vector length.
71 static constexpr size_t kArm64DefaultSVEVectorLength = 256;
72
73 // Code alignment (used for the first instruction of a subroutine, such as an entrypoint).
74 // This is the recommended alignment for maximum performance.
75 // ARM processors require code to be 4-byte aligned, but ARM ELF requires 8.
76 static constexpr size_t kArmCodeAlignment = 8;
77 static constexpr size_t kArm64CodeAlignment = 16;
78 static constexpr size_t kRiscv64CodeAlignment = 16;
79 static constexpr size_t kX86CodeAlignment = 16;
80
81 // Instruction alignment (every instruction must be aligned at this boundary). This differs from
82 // code alignment, which applies only to the first instruction of a subroutine.
83 // Android requires the RISC-V compressed instruction extension, and that allows
84 // *all* instructions (not just compressed ones) to be 2-byte aligned rather
85 // than the usual 4-byte alignment requirement.
86 static constexpr size_t kThumb2InstructionAlignment = 2;
87 static constexpr size_t kArm64InstructionAlignment = 4;
88 static constexpr size_t kRiscv64InstructionAlignment = 2;
89 static constexpr size_t kX86InstructionAlignment = 1;
90 static constexpr size_t kX86_64InstructionAlignment = 1;
91
92 const char* GetInstructionSetString(InstructionSet isa);
93
94 // Note: Returns kNone when the string cannot be parsed to a known value.
95 InstructionSet GetInstructionSetFromString(const char* instruction_set);
96
97 // Fatal logging out of line to keep the header clean of logging.h.
98 NO_RETURN void InstructionSetAbort(InstructionSet isa);
99
GetInstructionSetPointerSize(InstructionSet isa)100 constexpr PointerSize GetInstructionSetPointerSize(InstructionSet isa) {
101 switch (isa) {
102 case InstructionSet::kArm:
103 case InstructionSet::kThumb2:
104 return kArmPointerSize;
105 case InstructionSet::kArm64:
106 return kArm64PointerSize;
107 case InstructionSet::kRiscv64:
108 return kRiscv64PointerSize;
109 case InstructionSet::kX86:
110 return kX86PointerSize;
111 case InstructionSet::kX86_64:
112 return kX86_64PointerSize;
113 case InstructionSet::kNone:
114 InstructionSetAbort(isa);
115 }
116 }
117
IsValidInstructionSet(InstructionSet isa)118 constexpr bool IsValidInstructionSet(InstructionSet isa) {
119 switch (isa) {
120 case InstructionSet::kArm:
121 case InstructionSet::kThumb2:
122 case InstructionSet::kArm64:
123 case InstructionSet::kRiscv64:
124 case InstructionSet::kX86:
125 case InstructionSet::kX86_64:
126 return true;
127 case InstructionSet::kNone:
128 return false;
129 }
130 }
131
GetInstructionSetInstructionAlignment(InstructionSet isa)132 constexpr size_t GetInstructionSetInstructionAlignment(InstructionSet isa) {
133 switch (isa) {
134 case InstructionSet::kArm:
135 case InstructionSet::kThumb2:
136 return kThumb2InstructionAlignment;
137 case InstructionSet::kArm64:
138 return kArm64InstructionAlignment;
139 case InstructionSet::kRiscv64:
140 return kRiscv64InstructionAlignment;
141 case InstructionSet::kX86:
142 return kX86InstructionAlignment;
143 case InstructionSet::kX86_64:
144 return kX86_64InstructionAlignment;
145 case InstructionSet::kNone:
146 InstructionSetAbort(isa);
147 }
148 }
149
GetInstructionSetCodeAlignment(InstructionSet isa)150 constexpr size_t GetInstructionSetCodeAlignment(InstructionSet isa) {
151 switch (isa) {
152 case InstructionSet::kArm:
153 case InstructionSet::kThumb2:
154 return kArmCodeAlignment;
155 case InstructionSet::kArm64:
156 return kArm64CodeAlignment;
157 case InstructionSet::kRiscv64:
158 return kRiscv64CodeAlignment;
159 case InstructionSet::kX86:
160 case InstructionSet::kX86_64:
161 return kX86CodeAlignment;
162 case InstructionSet::kNone:
163 InstructionSetAbort(isa);
164 }
165 }
166
167 // Returns the difference between the code address and a usable PC.
168 // Mainly to cope with `kThumb2` where the lower bit must be set.
GetInstructionSetEntryPointAdjustment(InstructionSet isa)169 constexpr size_t GetInstructionSetEntryPointAdjustment(InstructionSet isa) {
170 switch (isa) {
171 case InstructionSet::kArm:
172 case InstructionSet::kArm64:
173 case InstructionSet::kRiscv64:
174 case InstructionSet::kX86:
175 case InstructionSet::kX86_64:
176 return 0;
177 case InstructionSet::kThumb2:
178 // +1 to set the low-order bit so a BLX will switch to Thumb mode
179 return 1;
180 case InstructionSet::kNone:
181 InstructionSetAbort(isa);
182 }
183 }
184
Is64BitInstructionSet(InstructionSet isa)185 constexpr bool Is64BitInstructionSet(InstructionSet isa) {
186 switch (isa) {
187 case InstructionSet::kArm:
188 case InstructionSet::kThumb2:
189 case InstructionSet::kX86:
190 return false;
191 case InstructionSet::kArm64:
192 case InstructionSet::kRiscv64:
193 case InstructionSet::kX86_64:
194 return true;
195 case InstructionSet::kNone:
196 InstructionSetAbort(isa);
197 }
198 }
199
InstructionSetPointerSize(InstructionSet isa)200 constexpr PointerSize InstructionSetPointerSize(InstructionSet isa) {
201 return Is64BitInstructionSet(isa) ? PointerSize::k64 : PointerSize::k32;
202 }
203
GetBytesPerGprSpillLocation(InstructionSet isa)204 constexpr size_t GetBytesPerGprSpillLocation(InstructionSet isa) {
205 switch (isa) {
206 case InstructionSet::kArm:
207 case InstructionSet::kThumb2:
208 case InstructionSet::kX86:
209 return 4;
210 case InstructionSet::kArm64:
211 case InstructionSet::kRiscv64:
212 case InstructionSet::kX86_64:
213 return 8;
214 case InstructionSet::kNone:
215 InstructionSetAbort(isa);
216 }
217 }
218
GetBytesPerFprSpillLocation(InstructionSet isa)219 constexpr size_t GetBytesPerFprSpillLocation(InstructionSet isa) {
220 switch (isa) {
221 case InstructionSet::kArm:
222 case InstructionSet::kThumb2:
223 return 4;
224 case InstructionSet::kArm64:
225 case InstructionSet::kRiscv64:
226 case InstructionSet::kX86:
227 case InstructionSet::kX86_64:
228 return 8;
229 case InstructionSet::kNone:
230 InstructionSetAbort(isa);
231 }
232 }
233
234 // Returns the instruction sets supported by the device, or an empty list on failure.
235 std::vector<InstructionSet> GetSupportedInstructionSets(std::string* error_msg);
236
237 namespace instruction_set_details {
238
239 #if !defined(ART_STACK_OVERFLOW_GAP_arm) || !defined(ART_STACK_OVERFLOW_GAP_arm64) || \
240 !defined(ART_STACK_OVERFLOW_GAP_riscv64) || \
241 !defined(ART_STACK_OVERFLOW_GAP_x86) || !defined(ART_STACK_OVERFLOW_GAP_x86_64)
242 #error "Missing defines for stack overflow gap"
243 #endif
244
245 static constexpr size_t kArmStackOverflowReservedBytes = ART_STACK_OVERFLOW_GAP_arm;
246 static constexpr size_t kArm64StackOverflowReservedBytes = ART_STACK_OVERFLOW_GAP_arm64;
247 static constexpr size_t kRiscv64StackOverflowReservedBytes = ART_STACK_OVERFLOW_GAP_riscv64;
248 static constexpr size_t kX86StackOverflowReservedBytes = ART_STACK_OVERFLOW_GAP_x86;
249 static constexpr size_t kX86_64StackOverflowReservedBytes = ART_STACK_OVERFLOW_GAP_x86_64;
250
251 NO_RETURN void GetStackOverflowReservedBytesFailure(const char* error_msg);
252
253 } // namespace instruction_set_details
254
255 ALWAYS_INLINE
GetStackOverflowReservedBytes(InstructionSet isa)256 constexpr size_t GetStackOverflowReservedBytes(InstructionSet isa) {
257 switch (isa) {
258 case InstructionSet::kArm: // Intentional fall-through.
259 case InstructionSet::kThumb2:
260 return instruction_set_details::kArmStackOverflowReservedBytes;
261
262 case InstructionSet::kArm64:
263 return instruction_set_details::kArm64StackOverflowReservedBytes;
264
265 case InstructionSet::kRiscv64:
266 return instruction_set_details::kRiscv64StackOverflowReservedBytes;
267
268 case InstructionSet::kX86:
269 return instruction_set_details::kX86StackOverflowReservedBytes;
270
271 case InstructionSet::kX86_64:
272 return instruction_set_details::kX86_64StackOverflowReservedBytes;
273
274 case InstructionSet::kNone:
275 instruction_set_details::GetStackOverflowReservedBytesFailure(
276 "kNone has no stack overflow size");
277 }
278 }
279
280 // The following definitions create return types for two word-sized entities that will be passed
281 // in registers so that memory operations for the interface trampolines can be avoided. The entities
282 // are the resolved method and the pointer to the code to be invoked.
283 //
284 // On x86 and ARM32, this is given for a *scalar* 64bit value. The definition thus *must* be
285 // uint64_t or long long int.
286 //
287 // On x86_64 and ARM64, structs are decomposed for allocation, so we can create a structs of
288 // two size_t-sized values.
289 //
290 // We need two operations:
291 //
292 // 1) A flag value that signals failure. The assembly stubs expect the lower part to be "0".
293 // GetTwoWordFailureValue() will return a value that has lower part == 0.
294 //
295 // 2) A value that combines two word-sized values.
296 // GetTwoWordSuccessValue() constructs this.
297 //
298 // IMPORTANT: If you use this to transfer object pointers, it is your responsibility to ensure
299 // that the object does not move or the value is updated. Simple use of this is NOT SAFE
300 // when the garbage collector can move objects concurrently. Ensure that required locks
301 // are held when using!
302
303 #if defined(__i386__) || defined(__arm__)
304 using TwoWordReturn = uint64_t;
305
306 // Encodes method_ptr==nullptr and code_ptr==nullptr
GetTwoWordFailureValue()307 static inline constexpr TwoWordReturn GetTwoWordFailureValue() {
308 return 0;
309 }
310
311 // Use the lower 32b for the method pointer and the upper 32b for the code pointer.
GetTwoWordSuccessValue(uintptr_t hi,uintptr_t lo)312 static inline constexpr TwoWordReturn GetTwoWordSuccessValue(uintptr_t hi, uintptr_t lo) {
313 static_assert(sizeof(uint32_t) == sizeof(uintptr_t), "Unexpected size difference");
314 uint32_t lo32 = lo;
315 uint64_t hi64 = static_cast<uint64_t>(hi);
316 return ((hi64 << 32) | lo32);
317 }
318
319 #elif defined(__x86_64__) || defined(__aarch64__) || defined(__riscv)
320
321 // Note: TwoWordReturn can't be constexpr for 64-bit targets. We'd need a constexpr constructor,
322 // which would violate C-linkage in the entrypoint functions.
323
324 struct TwoWordReturn {
325 uintptr_t lo;
326 uintptr_t hi;
327 };
328
329 // Encodes method_ptr==nullptr. Leaves random value in code pointer.
GetTwoWordFailureValue()330 static inline TwoWordReturn GetTwoWordFailureValue() {
331 TwoWordReturn ret;
332 ret.lo = 0;
333 return ret;
334 }
335
336 // Write values into their respective members.
GetTwoWordSuccessValue(uintptr_t hi,uintptr_t lo)337 static inline TwoWordReturn GetTwoWordSuccessValue(uintptr_t hi, uintptr_t lo) {
338 TwoWordReturn ret;
339 ret.lo = lo;
340 ret.hi = hi;
341 return ret;
342 }
343 #else
344 #error "Unsupported architecture"
345 #endif
346
347 } // namespace art
348
349 #endif // ART_LIBARTBASE_ARCH_INSTRUCTION_SET_H_
350