1 /*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "disassembler_arm64.h"
18
19 #include <inttypes.h>
20
21 #include <regex>
22
23 #include <sstream>
24
25 #include "android-base/logging.h"
26 #include "android-base/stringprintf.h"
27
28 using android::base::StringPrintf;
29
30 using namespace vixl::aarch64; // NOLINT(build/namespaces)
31
32 namespace art {
33 namespace arm64 {
34
35 // This enumeration should mirror the declarations in
36 // runtime/arch/arm64/registers_arm64.h. We do not include that file to
37 // avoid a dependency on libart.
38 enum {
39 TR = 19,
40 IP0 = 16,
41 IP1 = 17,
42 FP = 29,
43 LR = 30
44 };
45
AppendRegisterNameToOutput(const Instruction * instr,const CPURegister & reg)46 void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr,
47 const CPURegister& reg) {
48 USE(instr);
49 if (reg.IsRegister() && reg.Is64Bits()) {
50 if (reg.GetCode() == TR) {
51 AppendToOutput("tr");
52 return;
53 } else if (reg.GetCode() == LR) {
54 AppendToOutput("lr");
55 return;
56 }
57 // Fall through.
58 }
59 // Print other register names as usual.
60 Disassembler::AppendRegisterNameToOutput(instr, reg);
61 }
62
AppendCodeRelativeAddressToOutput(const Instruction * instr,const void * addr)63 void CustomDisassembler::AppendCodeRelativeAddressToOutput(const Instruction* instr,
64 const void* addr) {
65 USE(instr);
66 int64_t rel_addr = CodeRelativeAddress(addr);
67 if (rel_addr >= 0) {
68 AppendToOutput("(addr 0x%08" PRIx64 ")", rel_addr);
69 } else {
70 AppendToOutput("(addr -0x%08" PRIx64 ")", -rel_addr);
71 }
72 }
73
Visit(vixl::aarch64::Metadata * metadata,const Instruction * instr)74 void CustomDisassembler::Visit(vixl::aarch64::Metadata* metadata, const Instruction* instr) {
75 vixl::aarch64::Disassembler::Visit(metadata, instr);
76 const std::string& form = (*metadata)["form"];
77
78 // These regexs are long, but it is an attempt to match the mapping entry keys in the
79 // #define DEFAULT_FORM_TO_VISITOR_MAP(VISITORCLASS) in the file
80 // external/vixl/src/aarch64/decoder-visitor-map-aarch64.h
81 // for the ::VisitLoadLiteralInstr, ::VisitLoadStoreUnsignedOffset or ::VisitUnconditionalBranch
82 // function addresess key values.
83 // N.B. the mapping are many to one.
84 if (std::regex_match(form, std::regex("(ldrsw|ldr|prfm)_(32|64|d|b|h|q|s)_loadlit"))) {
85 VisitLoadLiteralInstr(instr);
86 return;
87 }
88
89 if (std::regex_match(form, std::regex(
90 "(ldrb|ldrh|ldrsb|ldrsh|ldrsw|ldr|prfm|strb|strh|str)_(32|64|d|b|h|q|s)_ldst_pos"))) {
91 VisitLoadStoreUnsignedOffsetInstr(instr);
92 return;
93 }
94
95 if (std::regex_match(form, std::regex("(bl|b)_only_branch_imm"))) {
96 VisitUnconditionalBranchInstr(instr);
97 return;
98 }
99 }
100
VisitLoadLiteralInstr(const Instruction * instr)101 void CustomDisassembler::VisitLoadLiteralInstr(const Instruction* instr) {
102 if (!read_literals_) {
103 return;
104 }
105
106 // Get address of literal. Bail if not within expected buffer range to
107 // avoid trying to fetch invalid literals (we can encounter this when
108 // interpreting raw data as instructions).
109 void* data_address = instr->GetLiteralAddress<void*>();
110
111 if (data_address < base_address_ || data_address >= end_address_) {
112 AppendToOutput(" (?)");
113 return;
114 }
115
116 // Output information on literal.
117 Instr op = instr->Mask(LoadLiteralMask);
118 switch (op) {
119 case LDR_w_lit:
120 case LDR_x_lit:
121 case LDRSW_x_lit: {
122 int64_t data = op == LDR_x_lit ? *reinterpret_cast<int64_t*>(data_address)
123 : *reinterpret_cast<int32_t*>(data_address);
124 AppendToOutput(" (0x%" PRIx64 " / %" PRId64 ")", data, data);
125 break;
126 }
127 case LDR_s_lit:
128 case LDR_d_lit: {
129 double data = (op == LDR_s_lit) ? *reinterpret_cast<float*>(data_address)
130 : *reinterpret_cast<double*>(data_address);
131 AppendToOutput(" (%g)", data);
132 break;
133 }
134 default:
135 break;
136 }
137 }
138
VisitLoadStoreUnsignedOffsetInstr(const Instruction * instr)139 void CustomDisassembler::VisitLoadStoreUnsignedOffsetInstr(const Instruction* instr) {
140 if (instr->GetRn() == TR) {
141 AppendThreadOfsetName(instr);
142 }
143 }
144
VisitUnconditionalBranchInstr(const Instruction * instr)145 void CustomDisassembler::VisitUnconditionalBranchInstr(const Instruction* instr) {
146 if (instr->Mask(UnconditionalBranchMask) == BL) {
147 const Instruction* target = instr->GetImmPCOffsetTarget();
148 if (target >= base_address_ &&
149 target < end_address_ &&
150 target->Mask(LoadStoreMask) == LDR_x &&
151 target->GetRn() == TR &&
152 target->GetRt() == IP0 &&
153 target->GetNextInstruction() < end_address_ &&
154 target->GetNextInstruction()->Mask(UnconditionalBranchToRegisterMask) == BR &&
155 target->GetNextInstruction()->GetRn() == IP0) {
156 AppendThreadOfsetName(target);
157 }
158 }
159 }
160
AppendThreadOfsetName(const vixl::aarch64::Instruction * instr)161 void CustomDisassembler::AppendThreadOfsetName(const vixl::aarch64::Instruction* instr) {
162 int64_t offset = instr->GetImmLSUnsigned() << instr->GetSizeLS();
163 std::ostringstream tmp_stream;
164 options_->thread_offset_name_function_(tmp_stream, static_cast<uint32_t>(offset));
165 AppendToOutput(" ; %s", tmp_stream.str().c_str());
166 }
167
Dump(std::ostream & os,const uint8_t * begin)168 size_t DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin) {
169 const Instruction* instr = reinterpret_cast<const Instruction*>(begin);
170 decoder.Decode(instr);
171 os << FormatInstructionPointer(begin)
172 << StringPrintf(": %08x\t%s\n", instr->GetInstructionBits(), disasm.GetOutput());
173 return kInstructionSize;
174 }
175
Dump(std::ostream & os,const uint8_t * begin,const uint8_t * end)176 void DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) {
177 for (const uint8_t* cur = begin; cur < end; cur += kInstructionSize) {
178 Dump(os, cur);
179 }
180 }
181
182 } // namespace arm64
183 } // namespace art
184