xref: /XiangShan/src/test/scala/cache/WpuTest.scala (revision 0466583513e4c1ddbbb566b866b8963635acb20f) 
1package cache
2
3import chisel3._
4import chiseltest._
5import org.scalatest.flatspec.AnyFlatSpec
6import top.DefaultConfig
7import xiangshan.cache.wpu.DCacheWpuWrapper
8import xiangshan.{XSCoreParamsKey, XSTileKey}
9
10class WpuBasicTest extends AnyFlatSpec with ChiselScalatestTester {
11  behavior of "DCacheWPU"
12  it should ("run") in {
13    val defaultConfig = (new DefaultConfig)
14    implicit val config = defaultConfig.alterPartial({
15      case XSCoreParamsKey => defaultConfig(XSTileKey).head.copy()
16    })
17    println("========== Test the correctness of syntactic and datapath ==========")
18    test(new DCacheWpuWrapper()) { c =>
19      println("========== in test ==========")
20      // s0
21      c.io.req(0).bits.vaddr.poke(0.U)
22      c.io.req(0).bits.replayCarry.valid.poke(false.B)
23      c.io.req(0).bits.replayCarry.real_way_en.poke(0.U)
24      c.io.req(0).valid.poke(true.B)
25      c.clock.step()
26      // s1
27      c.io.lookup_upd(0).valid.poke(true.B)
28      c.io.lookup_upd(0).bits.s1_real_way_en.poke("b00010000".U)
29      c.io.req(0).bits.vaddr.poke(0.U)
30      c.io.req(0).bits.replayCarry.valid.poke(false.B)
31      c.io.req(0).bits.replayCarry.real_way_en.poke(0.U)
32      c.io.req(0).valid.poke(true.B)
33      println("output value1 : " + c.io.resp(0).bits.s0_pred_way_en.peek().litValue)
34      c.clock.step()
35      println("output value2 : " + c.io.resp(0).bits.s0_pred_way_en.peek().litValue)
36    }
37    println("========== end test ==========")
38  }
39
40}
41