1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.rob.RobPtr 27import xiangshan.backend.Bundles._ 28import xiangshan.mem._ 29import xiangshan.backend.fu.vector.Bundles._ 30import xiangshan.backend.fu.FuConfig._ 31 32 33class VSplitPipeline(isVStore: Boolean = false)(implicit p: Parameters) extends VLSUModule{ 34 val io = IO(new VSplitPipelineIO(isVStore)) 35 // will be override later 36 def us_whole_reg(fuOpType: UInt): Bool = false.B 37 def us_mask(fuOpType: UInt): Bool = false.B 38 def us_fof(fuOpType: UInt): Bool = false.B 39 //TODO vdIdxReg should no longer be useful, don't delete it for now 40 val vdIdxReg = RegInit(0.U(3.W)) 41 42 val s1_ready = WireInit(false.B) 43 io.in.ready := s1_ready 44 45 /**----------------------------------------------------------- 46 * s0 stage 47 * decode and generate AlignedType, uop mask, preIsSplit 48 * ---------------------------------------------------------- 49 */ 50 val s0_uop = io.in.bits.uop 51 val s0_vtype = s0_uop.vpu.vtype 52 val s0_sew = s0_vtype.vsew 53 val s0_eew = s0_uop.vpu.veew 54 val s0_lmul = s0_vtype.vlmul 55 // when load whole register or unit-stride masked , emul should be 1 56 val s0_fuOpType = s0_uop.fuOpType 57 val s0_mop = s0_fuOpType(6, 5) 58 val s0_nf = Mux(us_whole_reg(s0_fuOpType), 0.U, s0_uop.vpu.nf) 59 val s0_vm = s0_uop.vpu.vm 60 val s0_emul = Mux(us_whole_reg(s0_fuOpType) ,GenUSWholeEmul(s0_uop.vpu.nf), Mux(us_mask(s0_fuOpType), 0.U(mulBits.W), EewLog2(s0_eew) - s0_sew + s0_lmul)) 61 val s0_preIsSplit = !isUnitStride(s0_mop) 62 val s0_nfield = s0_nf +& 1.U 63 64 val s0_valid = Wire(Bool()) 65 val s0_kill = io.in.bits.uop.robIdx.needFlush(io.redirect) 66 val s0_can_go = s1_ready 67 val s0_fire = s0_valid && s0_can_go 68 val s0_out = Wire(new VLSBundle(isVStore)) 69 70 val isUsWholeReg = isUnitStride(s0_mop) && us_whole_reg(s0_fuOpType) 71 val isMaskReg = isUnitStride(s0_mop) && us_mask(s0_fuOpType) 72 val isSegment = s0_nf =/= 0.U && !us_whole_reg(s0_fuOpType) 73 val instType = Cat(isSegment, s0_mop) 74 val uopIdx = io.in.bits.uop.vpu.vuopIdx 75 val uopIdxInField = GenUopIdxInField(instType, s0_emul, s0_lmul, uopIdx) 76 val vdIdxInField = GenVdIdxInField(instType, s0_emul, s0_lmul, uopIdxInField) 77 val lmulLog2 = Mux(s0_lmul.asSInt >= 0.S, 0.U, s0_lmul) 78 val emulLog2 = Mux(s0_emul.asSInt >= 0.S, 0.U, s0_emul) 79 val numEewLog2 = emulLog2 - EewLog2(s0_eew) 80 val numSewLog2 = lmulLog2 - s0_sew 81 val numFlowsSameVdLog2 = Mux( 82 isIndexed(instType), 83 log2Up(VLENB).U - s0_sew(1,0), 84 log2Up(VLENB).U - s0_eew 85 ) 86 // numUops = nf * max(lmul, emul) 87 val lmulLog2Pos = Mux(s0_lmul.asSInt < 0.S, 0.U, s0_lmul) 88 val emulLog2Pos = Mux(s0_emul.asSInt < 0.S, 0.U, s0_emul) 89 val numUops = Mux( 90 isIndexed(s0_mop) && s0_lmul.asSInt > s0_emul.asSInt, 91 (s0_nf +& 1.U) << lmulLog2Pos, 92 (s0_nf +& 1.U) << emulLog2Pos 93 ) 94 95 val vvl = io.in.bits.src_vl.asTypeOf(VConfig()).vl 96 val evl = Mux(isUsWholeReg, 97 GenUSWholeRegVL(io.in.bits.uop.vpu.nf +& 1.U, s0_eew), 98 Mux(isMaskReg, 99 GenUSMaskRegVL(vvl), 100 vvl)) 101 val vvstart = io.in.bits.uop.vpu.vstart 102 val alignedType = Mux(isIndexed(instType), s0_sew(1, 0), s0_eew) 103 val broadenAligendType = Mux(s0_preIsSplit, Cat("b0".U, alignedType), "b100".U) // if is unit-stride, use 128-bits memory access 104 val flowsLog2 = GenRealFlowLog2(instType, s0_emul, s0_lmul, s0_eew, s0_sew) 105 val flowsPrevThisUop = (uopIdxInField << flowsLog2).asUInt // # of flows before this uop in a field 106 val flowsPrevThisVd = (vdIdxInField << numFlowsSameVdLog2).asUInt // # of flows before this vd in a field 107 val flowsIncludeThisUop = ((uopIdxInField +& 1.U) << flowsLog2).asUInt // # of flows before this uop besides this uop 108 val flowNum = io.in.bits.flowNum.get 109 // max index in vd, only use in index instructions for calculate index 110 val maxIdxInVdIndex = GenVLMAX(Mux(s0_emul.asSInt > 0.S, 0.U, s0_emul), s0_eew) 111 val indexVlMaxInVd = GenVlMaxMask(maxIdxInVdIndex, elemIdxBits) 112 113 // For vectore indexed instructions: 114 // When emul is greater than lmul, multiple uop correspond to a Vd, e.g: 115 // vsetvli t1,t0,e8,m1,ta,ma lmul = 1 116 // vluxei16.v v2,(a0),v8 emul = 2 117 // In this case, we need to ensure the flownumis right shift by flowsPrevThisUop, However, the mask passed to mergebuff is right shift by flowsPrevThisVd e.g: 118 // vl = 9 119 // srcMask = 0x1FF 120 // uopIdxInField = 0 and vdIdxInField = 0, flowMask = 0x00FF, toMergeBuffMask = 0x01FF 121 // uopIdxInField = 1 and vdIdxInField = 0, flowMask = 0x0001, toMergeBuffMask = 0x01FF 122 // uopIdxInField = 0 and vdIdxInField = 0, flowMask = 0x0000, toMergeBuffMask = 0x0000 123 // uopIdxInField = 0 and vdIdxInField = 0, flowMask = 0x0000, toMergeBuffMask = 0x0000 124 val isSpecialIndexed = isIndexed(instType) && s0_emul.asSInt > s0_lmul.asSInt 125 126 val srcMask = GenFlowMask(Mux(s0_vm, Fill(VLEN, 1.U(1.W)), io.in.bits.src_mask), vvstart, evl, true) 127 val srcMaskShiftBits = Mux(isSpecialIndexed, flowsPrevThisUop, flowsPrevThisVd) 128 129 val flowMask = ((srcMask & 130 UIntToMask(flowsIncludeThisUop.asUInt, VLEN + 1) & 131 (~UIntToMask(flowsPrevThisUop.asUInt, VLEN)).asUInt 132 ) >> srcMaskShiftBits)(VLENB - 1, 0) 133 val indexedSrcMask = (srcMask >> flowsPrevThisVd).asUInt //only for index instructions 134 135 // Used to calculate the element index. 136 // See 'splitbuffer' for 'io.out.splitIdxOffset' and 'mergebuffer' for 'merge data' 137 val indexedSplitOffset = Mux(isSpecialIndexed, flowsPrevThisUop - flowsPrevThisVd, 0.U) // only for index instructions of emul > lmul 138 val vlmax = GenVLMAX(s0_lmul, s0_sew) 139 140 // connect 141 s0_out := DontCare 142 s0_out match {case x => 143 x.uop := io.in.bits.uop 144 x.uop.vpu.vl := evl 145 x.uop.uopIdx := uopIdx 146 x.uop.numUops := numUops 147 x.uop.lastUop := (uopIdx +& 1.U) === numUops 148 x.uop.vpu.nf := s0_nf 149 x.rawNf := io.in.bits.uop.vpu.nf 150 x.flowMask := flowMask 151 x.indexedSrcMask := indexedSrcMask // Only vector indexed instructions uses it 152 x.indexedSplitOffset := indexedSplitOffset 153 x.byteMask := GenUopByteMask(flowMask, Cat("b0".U, alignedType))(VLENB - 1, 0) 154 x.fof := isUnitStride(s0_mop) && us_fof(s0_fuOpType) 155 x.baseAddr := io.in.bits.src_rs1 156 x.stride := io.in.bits.src_stride 157 x.flowNum := flowNum 158 x.nfields := s0_nfield 159 x.vm := s0_vm 160 x.usWholeReg := isUsWholeReg 161 x.usMaskReg := isMaskReg 162 x.eew := s0_eew 163 x.sew := s0_sew 164 x.emul := s0_emul 165 x.lmul := s0_lmul 166 x.vlmax := Mux(isUsWholeReg, evl, vlmax) 167 x.instType := instType 168 x.data := io.in.bits.src_vs3 169 x.vdIdxInField := vdIdxInField 170 x.preIsSplit := s0_preIsSplit 171 x.alignedType := broadenAligendType 172 x.indexVlMaxInVd := indexVlMaxInVd 173 } 174 s0_valid := io.in.valid && !s0_kill 175 /**------------------------------------- 176 * s1 stage 177 * ------------------------------------ 178 * generate UopOffset 179 */ 180 val s1_valid = RegInit(false.B) 181 val s1_kill = Wire(Bool()) 182 val s1_in = Wire(new VLSBundle(isVStore)) 183 val s1_can_go = io.out.ready && io.toMergeBuffer.req.ready 184 val s1_fire = s1_valid && !s1_kill && s1_can_go 185 186 s1_ready := s1_kill || !s1_valid || s1_can_go 187 188 when(s0_fire){ 189 s1_valid := true.B 190 }.elsewhen(s1_fire){ 191 s1_valid := false.B 192 }.elsewhen(s1_kill){ 193 s1_valid := false.B 194 } 195 s1_in := RegEnable(s0_out, s0_fire) 196 197 val s1_flowNum = s1_in.flowNum 198 val s1_uop = s1_in.uop 199 val s1_uopidx = s1_uop.vpu.vuopIdx 200 val s1_nf = s1_uop.vpu.nf 201 val s1_nfields = s1_in.nfields 202 val s1_eew = s1_in.eew 203 val s1_emul = s1_in.emul 204 val s1_lmul = s1_in.lmul 205 val s1_instType = s1_in.instType 206 val s1_stride = s1_in.stride 207 val s1_vmask = FillInterleaved(8, s1_in.byteMask)(VLEN-1, 0) 208 val s1_alignedType = s1_in.alignedType 209 val s1_isSpecialIndexed = isIndexed(s1_instType) && s1_emul.asSInt > s1_lmul.asSInt 210 val s1_mask = Mux(s1_isSpecialIndexed, s1_in.indexedSrcMask, s1_in.flowMask) 211 val s1_vdIdx = s1_in.vdIdxInField 212 val s1_fof = s1_in.fof 213 val s1_notIndexedStride = Mux( // stride for strided/unit-stride instruction 214 isStrided(s1_instType), 215 s1_stride(XLEN - 1, 0), // for strided load, stride = x[rs2] 216 s1_nfields << s1_eew // for unit-stride load, stride = eew * NFIELDS 217 ) 218 219 val stride = Mux(isIndexed(s1_instType), s1_stride, s1_notIndexedStride).asUInt // if is index instructions, get index when split 220 val uopOffset = genVUopOffset(s1_instType, s1_fof, s1_uopidx, s1_nf, s1_eew, stride, s1_alignedType) 221 val activeNum = Mux(s1_in.preIsSplit, PopCount(s1_in.flowMask), s1_flowNum) 222 // for Unit-Stride, if uop's addr is aligned with 128-bits, split it to one flow, otherwise split two 223 val usLowBitsAddr = getCheckAddrLowBits(s1_in.baseAddr, maxMemByteNum) + getCheckAddrLowBits(uopOffset, maxMemByteNum) 224 val usAligned128 = (getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum) === 0.U)// addr 128-bit aligned 225 val usMask = Cat(0.U(VLENB.W), s1_in.byteMask) << getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum) 226 227 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) 228 229 // query mergeBuffer 230 io.toMergeBuffer.req.valid := io.out.ready && s1_valid// only can_go will get MergeBuffer entry 231 io.toMergeBuffer.req.bits.flowNum := activeNum 232 io.toMergeBuffer.req.bits.data := s1_in.data 233 io.toMergeBuffer.req.bits.uop := s1_in.uop 234 io.toMergeBuffer.req.bits.uop.vpu.nf := s1_in.rawNf 235 io.toMergeBuffer.req.bits.mask := s1_mask 236 io.toMergeBuffer.req.bits.vaddr := s1_in.baseAddr 237 io.toMergeBuffer.req.bits.vdIdx := s1_vdIdx //TODO vdIdxReg should no longer be useful, don't delete it for now 238 io.toMergeBuffer.req.bits.fof := s1_in.fof 239 io.toMergeBuffer.req.bits.vlmax := s1_in.vlmax 240// io.toMergeBuffer.req.bits.vdOffset := 241 242 //TODO vdIdxReg should no longer be useful, don't delete it for now 243// when (s1_in.uop.lastUop && s1_fire || s1_kill) { 244// vdIdxReg := 0.U 245// }.elsewhen(s1_fire) { 246// vdIdxReg := vdIdxReg + 1.U 247// XSError(vdIdxReg + 1.U === 0.U, s"Overflow! The number of vd should be less than 8\n") 248// } 249 // out connect 250 io.out.valid := s1_valid && io.toMergeBuffer.resp.valid && (activeNum =/= 0.U) // if activeNum == 0, this uop do nothing, can be killed. 251 io.out.bits := s1_in 252 io.out.bits.uopOffset := uopOffset 253 io.out.bits.stride := stride 254 io.out.bits.mBIndex := io.toMergeBuffer.resp.bits.mBIndex 255 io.out.bits.usLowBitsAddr := usLowBitsAddr 256 io.out.bits.usAligned128 := usAligned128 257 io.out.bits.usMask := usMask 258 io.out.bits.uop.vpu.nf := s1_in.rawNf 259 260 XSPerfAccumulate("split_out", io.out.fire) 261 XSPerfAccumulate("pipe_block", io.out.valid && !io.out.ready) 262 XSPerfAccumulate("mbuffer_block", s1_valid && io.out.ready && !io.toMergeBuffer.resp.valid) 263} 264 265abstract class VSplitBuffer(isVStore: Boolean = false)(implicit p: Parameters) extends VLSUModule{ 266 val io = IO(new VSplitBufferIO(isVStore)) 267 lazy val fuCfg = if(isVStore) VstuCfg else VlduCfg 268 269 val uopq = Reg(new VLSBundle(isVStore)) 270 val allocated = RegInit(false.B) 271 val needCancel = WireInit(false.B) 272 val activeIssue = Wire(Bool()) 273 val inActiveIssue = Wire(Bool()) 274 val splitFinish = WireInit(false.B) 275 276 // for split 277 val splitIdx = RegInit(0.U(flowIdxBits.W)) 278 val strideOffsetReg = RegInit(0.U(VLEN.W)) 279 280 /** 281 * Redirect 282 */ 283 val cancelEnq = io.in.bits.uop.robIdx.needFlush(io.redirect) 284 val canEnqueue = io.in.valid 285 val needEnqueue = canEnqueue && !cancelEnq 286 287 // enqueue 288 val offset = PopCount(needEnqueue) 289 val canAccept = !allocated || allocated && splitFinish && (activeIssue || inActiveIssue) // if is valid entry, need split finish and send last uop 290 io.in.ready := canAccept 291 val doEnqueue = canAccept && needEnqueue 292 293 when(doEnqueue){ 294 uopq := io.in.bits 295 } 296 297 //split uops 298 val issueValid = allocated && !needCancel 299 val issueEntry = uopq 300 val issueMbIndex = issueEntry.mBIndex 301 val issueFlowNum = issueEntry.flowNum 302 val issueBaseAddr = issueEntry.baseAddr 303 val issueUop = issueEntry.uop 304 val issueUopIdx = issueUop.vpu.vuopIdx 305 val issueInstType = issueEntry.instType 306 val issueUopOffset = issueEntry.uopOffset 307 val issueEew = issueEntry.eew 308 val issueSew = issueEntry.sew 309 val issueLmul = issueEntry.lmul 310 val issueEmul = issueEntry.emul 311 val issueAlignedType = issueEntry.alignedType 312 val issuePreIsSplit = issueEntry.preIsSplit 313 val issueByteMask = issueEntry.byteMask 314 val issueUsMask = issueEntry.usMask 315 val issueVLMAXMask = issueEntry.vlmax - 1.U 316 val issueIsWholeReg = issueEntry.usWholeReg 317 val issueVLMAXLog2 = GenVLMAXLog2(issueEntry.lmul, issueSew) 318 val issueVlMaxInVd = issueEntry.indexVlMaxInVd 319 val issueUsLowBitsAddr = issueEntry.usLowBitsAddr 320 val issueUsAligned128 = issueEntry.usAligned128 321 val elemIdx = GenElemIdx( 322 instType = issueInstType, 323 emul = issueEmul, 324 lmul = issueLmul, 325 eew = issueEew, 326 sew = issueSew, 327 uopIdx = issueUopIdx, 328 flowIdx = splitIdx 329 ) // elemIdx inside an inst, for exception 330 331 val splitIdxOffset = issueEntry.indexedSplitOffset + splitIdx 332 333 val indexFlowInnerIdx = elemIdx & issueVlMaxInVd 334 val nfIdx = Mux(issueIsWholeReg, 0.U, elemIdx >> issueVLMAXLog2) 335 val fieldOffset = nfIdx << issueAlignedType // field offset inside a segment 336 337 val indexedStride = IndexAddr( // index for indexed instruction 338 index = issueEntry.stride, 339 flow_inner_idx = indexFlowInnerIdx, 340 eew = issueEew 341 ) 342 val issueStride = Mux(isIndexed(issueInstType), indexedStride, strideOffsetReg) 343 val vaddr = issueBaseAddr + issueUopOffset + issueStride 344 val mask = genVWmask128(vaddr ,issueAlignedType) // scala maske for flow 345 val flowMask = issueEntry.flowMask 346 val vecActive = (flowMask & UIntToOH(splitIdx)).orR 347 /* 348 * Unit-Stride split to one flow or two flow. 349 * for Unit-Stride, if uop's addr is aligned with 128-bits, split it to one flow, otherwise split two 350 */ 351 val usSplitMask = genUSSplitMask(issueUsMask, splitIdx) 352 val usMaskInSingleUop = (genUSSplitMask(issueUsMask, 1.U) === 0.U) // if second splited Mask is zero, means this uop is unnecessary to split 353 val usNoSplit = (issueUsAligned128 || usMaskInSingleUop) && 354 !issuePreIsSplit && 355 (splitIdx === 0.U)// unit-stride uop don't need to split into two flow 356 val usSplitVaddr = genUSSplitAddr(vaddr, splitIdx, XLEN) 357 val regOffset = getCheckAddrLowBits(issueUsLowBitsAddr, maxMemByteNum) // offset in 256-bits vd 358 XSError((splitIdx > 1.U && usNoSplit) || (splitIdx > 1.U && !issuePreIsSplit) , "Unit-Stride addr split error!\n") 359 360 val addrAligned = LookupTree(issueEew, List( 361 "b00".U -> true.B, //b 362 "b01".U -> (issueBaseAddr(0) === 0.U), //h 363 "b10".U -> (issueBaseAddr(1, 0) === 0.U), //w 364 "b11".U -> (issueBaseAddr(2, 0) === 0.U) //d 365 )) 366 367 // data 368 io.out.bits match { case x => 369 x.uop := issueUop 370 x.uop.exceptionVec := ExceptionNO.selectByFu(issueUop.exceptionVec, fuCfg) 371 x.vaddr := Mux(!issuePreIsSplit, usSplitVaddr, vaddr) 372 x.basevaddr := issueBaseAddr 373 x.alignedType := issueAlignedType 374 x.isvec := true.B 375 x.mask := Mux(!issuePreIsSplit, usSplitMask, mask) 376 x.reg_offset := regOffset //for merge unit-stride data 377 x.vecActive := Mux(!issuePreIsSplit, true.B, vecActive) // currently, unit-stride's flow always send to pipeline 378 x.is_first_ele := DontCare 379 x.usSecondInv := usNoSplit 380 x.elemIdx := elemIdx 381 x.elemIdxInsideVd := splitIdxOffset // if is Unit-Stride, elemIdx is the index of 2 splited mem request (for merge data) 382 x.uop_unit_stride_fof := DontCare 383 x.isFirstIssue := DontCare 384 x.mBIndex := issueMbIndex 385 } 386 387 // redirect 388 needCancel := uopq.uop.robIdx.needFlush(io.redirect) && allocated 389 390 /* Execute logic */ 391 /** Issue to scala pipeline**/ 392 val allowIssue = io.out.ready 393 val issueCount = Mux(usNoSplit, 2.U, (PopCount(inActiveIssue) + PopCount(activeIssue))) // for dont need split unit-stride, issue two flow 394 splitFinish := splitIdx >= (issueFlowNum - issueCount) 395 396 // handshake 397 activeIssue := issueValid && allowIssue && (vecActive || !issuePreIsSplit) // active issue, current use in no unit-stride 398 inActiveIssue := issueValid && !vecActive && issuePreIsSplit 399 when (!issueEntry.uop.robIdx.needFlush(io.redirect)) { 400 when (!splitFinish) { 401 when (activeIssue || inActiveIssue) { 402 // The uop has not been entirly splited yet 403 splitIdx := splitIdx + issueCount 404 strideOffsetReg := Mux(!issuePreIsSplit, strideOffsetReg, strideOffsetReg + issueEntry.stride) // when normal unit-stride, don't use strideOffsetReg 405 } 406 }.otherwise { 407 when (activeIssue || inActiveIssue) { 408 // The uop is done spliting 409 splitIdx := 0.U(flowIdxBits.W) // initialize flowIdx 410 strideOffsetReg := 0.U 411 } 412 } 413 }.otherwise { 414 splitIdx := 0.U(flowIdxBits.W) // initialize flowIdx 415 strideOffsetReg := 0.U 416 } 417 // allocated 418 when(doEnqueue){ // if enqueue need to been cancelled, it will be false, so this have high priority 419 allocated := true.B 420 }.elsewhen(needCancel) { // redirect 421 allocated := false.B 422 }.elsewhen(splitFinish && (activeIssue || inActiveIssue)){ //dequeue 423 allocated := false.B 424 } 425 426 // out connect 427 io.out.valid := issueValid && (vecActive || !issuePreIsSplit) // TODO: inactive unit-stride uop do not send to pipeline 428 429 XSPerfAccumulate("out_valid", io.out.valid) 430 XSPerfAccumulate("out_fire", io.out.fire) 431 XSPerfAccumulate("out_fire_unitstride", io.out.fire && !issuePreIsSplit) 432 XSPerfAccumulate("unitstride_vlenAlign", io.out.fire && !issuePreIsSplit && getCheckAddrLowBits(io.out.bits.vaddr, maxMemByteNum) === 0.U) 433 XSPerfAccumulate("unitstride_invalid", io.out.ready && issueValid && !issuePreIsSplit && PopCount(io.out.bits.mask).orR) 434} 435 436class VSSplitBufferImp(implicit p: Parameters) extends VSplitBuffer(isVStore = true){ 437 // split data 438 val splitData = genVSData( 439 data = issueEntry.data.asUInt, 440 elemIdx = splitIdxOffset, 441 alignedType = issueAlignedType 442 ) 443 val flowData = genVWdata(splitData, issueAlignedType) 444 val usSplitData = genUSSplitData(issueEntry.data.asUInt, splitIdx, vaddr(3,0)) 445 446 val sqIdx = issueUop.sqIdx + splitIdx 447 io.out.bits.uop.sqIdx := sqIdx 448 io.out.bits.uop.exceptionVec(storeAddrMisaligned) := !addrAligned && !issuePreIsSplit && io.out.bits.mask.orR 449 450 // send data to sq 451 val vstd = io.vstd.get 452 vstd.valid := issueValid && (vecActive || !issuePreIsSplit) 453 vstd.bits.uop := issueUop 454 vstd.bits.uop.sqIdx := sqIdx 455 vstd.bits.data := Mux(!issuePreIsSplit, usSplitData, flowData) 456 vstd.bits.debug := DontCare 457 vstd.bits.vdIdx.get := DontCare 458 vstd.bits.vdIdxInField.get := DontCare 459 vstd.bits.isFromLoadUnit := DontCare 460 vstd.bits.mask.get := Mux(!issuePreIsSplit, usSplitMask, mask) 461 462} 463 464class VLSplitBufferImp(implicit p: Parameters) extends VSplitBuffer(isVStore = false){ 465 io.out.bits.uop.lqIdx := issueUop.lqIdx + splitIdx 466 io.out.bits.uop.exceptionVec(loadAddrMisaligned) := !addrAligned && !issuePreIsSplit && io.out.bits.mask.orR 467} 468 469class VSSplitPipelineImp(implicit p: Parameters) extends VSplitPipeline(isVStore = true){ 470 override def us_whole_reg(fuOpType: UInt): Bool = fuOpType === VstuType.vsr 471 override def us_mask(fuOpType: UInt): Bool = fuOpType === VstuType.vsm 472 override def us_fof(fuOpType: UInt): Bool = false.B // dont have vector fof store 473} 474 475class VLSplitPipelineImp(implicit p: Parameters) extends VSplitPipeline(isVStore = false){ 476 477 override def us_whole_reg(fuOpType: UInt): Bool = fuOpType === VlduType.vlr 478 override def us_mask(fuOpType: UInt): Bool = fuOpType === VlduType.vlm 479 override def us_fof(fuOpType: UInt): Bool = fuOpType === VlduType.vleff 480} 481 482class VLSplitImp(implicit p: Parameters) extends VLSUModule{ 483 val io = IO(new VSplitIO(isVStore=false)) 484 val splitPipeline = Module(new VLSplitPipelineImp()) 485 val splitBuffer = Module(new VLSplitBufferImp()) 486 // Split Pipeline 487 splitPipeline.io.in <> io.in 488 splitPipeline.io.redirect <> io.redirect 489 io.toMergeBuffer <> splitPipeline.io.toMergeBuffer 490 491 // skid buffer 492 skidBuffer(splitPipeline.io.out, splitBuffer.io.in, 493 Mux(splitPipeline.io.out.fire, 494 splitPipeline.io.out.bits.uop.robIdx.needFlush(io.redirect), 495 splitBuffer.io.in.bits.uop.robIdx.needFlush(io.redirect)), 496 "VSSplitSkidBuffer") 497 498 // Split Buffer 499 splitBuffer.io.redirect <> io.redirect 500 io.out <> splitBuffer.io.out 501} 502 503class VSSplitImp(implicit p: Parameters) extends VLSUModule{ 504 val io = IO(new VSplitIO(isVStore=true)) 505 val splitPipeline = Module(new VSSplitPipelineImp()) 506 val splitBuffer = Module(new VSSplitBufferImp()) 507 // Split Pipeline 508 splitPipeline.io.in <> io.in 509 splitPipeline.io.redirect <> io.redirect 510 io.toMergeBuffer <> splitPipeline.io.toMergeBuffer 511 512 // skid buffer 513 skidBuffer(splitPipeline.io.out, splitBuffer.io.in, 514 Mux(splitPipeline.io.out.fire, 515 splitPipeline.io.out.bits.uop.robIdx.needFlush(io.redirect), 516 splitBuffer.io.in.bits.uop.robIdx.needFlush(io.redirect)), 517 "VSSplitSkidBuffer") 518 519 // Split Buffer 520 splitBuffer.io.redirect <> io.redirect 521 io.out <> splitBuffer.io.out 522 io.vstd.get <> splitBuffer.io.vstd.get 523} 524 525