timing(VLSU): fix timing issues in `VLSU` (#4158)

## Two main issues were fixed:
**Timing issue caused by too long address calculations for vector
modules:**
- Solved by moving some of the logic

timing(VLSU): fix timing issues in `VLSU` (#4158)

## Two main issues were fixed:
**Timing issue caused by too long address calculations for vector
modules:**
- Solved by moving some of the logic to the previous cycle.

---

**Timing issue caused by long exception logic of load writeback to
`VLMergeBuffer`:**
- Add one cycle to the load writeback exception, now the same number of
cycles as the load write back data.

show more ...

fix(VLSU): `mergebuffer` threshold was added (#4103)

To solve the stuckness caused by insufficient RAW, we use `threshold` to
control the execution of vector instructions.
When the mergebuffer has f

fix(VLSU): `mergebuffer` threshold was added (#4103)

To solve the stuckness caused by insufficient RAW, we use `threshold` to
control the execution of vector instructions.
When the mergebuffer has few free entries than it can hold in the flow,
we backpressure to make `IssueQueue` send the oldest `Uop` for us.

show more ...

fix(VSplit): inactive elements of `UnitStride` are no longer executed (#4100)

Now, we no longer have `inActive` is `unit-stride` sent to the pipeline.
This will fix some bugs caused by `inActive` no

fix(VSplit): inactive elements of `UnitStride` are no longer executed (#4100)

Now, we no longer have `inActive` is `unit-stride` sent to the pipeline.
This will fix some bugs caused by `inActive` not being handled properly in `LSU`.
And will theoretically result in some performance gains.

show more ...

feat(Zicclsm): refactoring misalign and support vector misalign

area(MemBlock): remove redundant signals to optimise area (#3560)

optimise redundant signals to reduce MemBlock area.
1. optimise 'exceptionVec', selected by LduCfg or StaCfg;
2. optimise 'fuType'

area(MemBlock): remove redundant signals to optimise area (#3560)

optimise redundant signals to reduce MemBlock area.
1. optimise 'exceptionVec', selected by LduCfg or StaCfg;
2. optimise 'fuType', reassign the value when writeback Rob in pipeline,
so no longer saved in LSQ.
3. optimise 'uop.imm', vaddr is computed in StoreMisalignBuffer and
there is no need to store the uop.imm.

show more ...

fix(Backend, Mem): add `isFromLoadUnit` to avoid other units polluting RegCache (#3731)

feat(rv64v): support first only fault instruction

feat(VLSU): set vstart when the support vector accesses anomalies

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retain

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retained. And for exceptions detected after address translation, the
48-bit vaddr needs to be zero-extended or sign-extended according to
different modes(`GenExceptionVa`), and then write to *tval.

Also fix some connection bugs.

show more ...

fix(VLSU): fix bug in flush of pipeline connect & skid buffer (#3646)

In the previous design, the judgment of `flush` of pipeline connect and
skid buffer is `io.in.bits.uop.robidx.needFlush(redirec

fix(VLSU): fix bug in flush of pipeline connect & skid buffer (#3646)

In the previous design, the judgment of `flush` of pipeline connect and
skid buffer is `io.in.bits.uop.robidx.needFlush(redirect)`, which will
causes the request stored in the buffer that should not be flushed to be
flushed.

The function of `flush`:
1. When `in.fire`, `flush` means to cancel request that will be buffer
stored.
2. When `!in.fire`, `flush` means to cancel the request which stored in
the buffer can't be send to the next stage, new request can't enter the
buffer.

This patch fixs the meaning of `flush` above.

show more ...

fix(VLSU): fix vector unit-stride address truncation (#3589)

timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Opt

timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Optimize VLSU feedback and redirect
+ Optimise ldCancel and writeback signal generation
+ Optimise TLB Query Vaddr/hlv/hlvx/valid etc
+ Delay MMIO Store writeback for 1 Cycle
+ Fix tlbNoQuery and pmp logic
+ Remove clock gating for s3_fast_rep
+ Remove wbq conflict check to LoadPipe/MainPipe
+ Remove Mux in dcache resp data
+ Optimise data generation logic of LoadUnit
+ Duplicate Register in LoadUnit for data writeback
+ Duplicate Register in loadPipe for missQueue enq
+ Add skid buffer in VLSU
+ Select data from metaArray at S1
+ Simplify the enqueuing logic of missQueue
+ Separately generate the ready logic of miss Queue
+ Relax the conditions valid for bankdataArray reads
+ Add Reg between Dcache Mainpipe with sms prefetcher
+ Optimise store exceptionBuffer pipeline

---------

Co-authored-by: weiding liu <[email protected]>
Co-authored-by: Charlie Liu <[email protected]>
Co-authored-by: good-circle <[email protected]>

show more ...

fix(VLSU): Vector Unit-Stride instr should trigger misaligned exception (#3462)

Vsplit: fix bug of unit-stride split judgement

This commit also lead to batter timing, because judgement of unit-stride split will be faster.

Vsplit: optimize generate of ready for vector issue

VLSU: Modify the width of Veew when decode and remove some useless api (#3258)

VSplit: refactor addr aligned logic for Unit-Stride

VMergeBuffer: add ExceptionVec select By fuCfg for better timing and area

VSplit: refactor enter MergeBuffer handshark logic

VSplit: Optimised address generation

Vsplit: Parameterised splitting address 128-bits alignment checking

VLSU: remove splitBuffer for timing

This commit remove SplitBuffer for better timing. The function of SplitBuffer is only used to store unsplit UOPs, and deletion has little impact.

VSplit: refactor ready signal send to higher-level flow

This commit refactor ready signal's logic, which will get better timing

VLSU: fix bug of vector load/store split & support segment instruction exception (#3033)

* Support segment load/store exception.
* Fix handle of inactive element when split uop.

VSplit: replace the sequential queue with a freelist

Becasue of uop enqueue is out of order. when redirect, the uop which need to flush may not the head of queue, so that we replace the sequential q

VSplit: replace the sequential queue with a freelist

Becasue of uop enqueue is out of order. when redirect, the uop which need to flush may not the head of queue, so that we replace the sequential queue with freelist.

show more ...