1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.rob.RobPtr 26import xiangshan.backend.Bundles._ 27import xiangshan.mem._ 28import xiangshan.backend.fu.vector.Bundles._ 29 30 31class VSplitPipeline(isVStore: Boolean = false)(implicit p: Parameters) extends VLSUModule{ 32 val io = IO(new VSplitPipelineIO(isVStore)) 33 // will be override later 34 def us_whole_reg(fuOpType: UInt): Bool = false.B 35 def us_mask(fuOpType: UInt): Bool = false.B 36 def us_fof(fuOpType: UInt): Bool = false.B 37 //TODO vdIdxReg should no longer be useful, don't delete it for now 38 val vdIdxReg = RegInit(0.U(3.W)) 39 40 val s1_ready = WireInit(false.B) 41 io.in.ready := s1_ready 42 43 /**----------------------------------------------------------- 44 * s0 stage 45 * decode and generate AlignedType, uop mask, preIsSplit 46 * ---------------------------------------------------------- 47 */ 48 val s0_vtype = io.in.bits.uop.vpu.vtype 49 val s0_sew = s0_vtype.vsew 50 val s0_eew = io.in.bits.uop.vpu.veew 51 val s0_lmul = s0_vtype.vlmul 52 // when load whole register or unit-stride masked , emul should be 1 53 val s0_fuOpType = io.in.bits.uop.fuOpType 54 val s0_mop = s0_fuOpType(6, 5) 55 val s0_nf = Mux(us_whole_reg(s0_fuOpType), 0.U, io.in.bits.uop.vpu.nf) 56 val s0_vm = io.in.bits.uop.vpu.vm 57 val s0_emul = Mux(us_whole_reg(s0_fuOpType) ,GenUSWholeEmul(io.in.bits.uop.vpu.nf), Mux(us_mask(s0_fuOpType), 0.U(mulBits.W), EewLog2(s0_eew) - s0_sew + s0_lmul)) 58 val s0_preIsSplit = !(isUnitStride(s0_mop) && !us_fof(s0_fuOpType)) 59 val s0_nfield = s0_nf +& 1.U 60 61 val s0_valid = Wire(Bool()) 62 val s0_kill = io.in.bits.uop.robIdx.needFlush(io.redirect) 63 val s0_can_go = s1_ready 64 val s0_fire = s0_valid && s0_can_go 65 val s0_out = Wire(new VLSBundle(isVStore)) 66 67 val isUsWholeReg = isUnitStride(s0_mop) && us_whole_reg(s0_fuOpType) 68 val isMaskReg = isUnitStride(s0_mop) && us_mask(s0_fuOpType) 69 val isSegment = s0_nf =/= 0.U && !us_whole_reg(s0_fuOpType) 70 val instType = Cat(isSegment, s0_mop) 71 val uopIdx = io.in.bits.uop.vpu.vuopIdx 72 val uopIdxInField = GenUopIdxInField(instType, s0_emul, s0_lmul, uopIdx) 73 val vdIdxInField = GenVdIdxInField(instType, s0_emul, s0_lmul, uopIdxInField) 74 val lmulLog2 = Mux(s0_lmul.asSInt >= 0.S, 0.U, s0_lmul) 75 val emulLog2 = Mux(s0_emul.asSInt >= 0.S, 0.U, s0_emul) 76 val numEewLog2 = emulLog2 - EewLog2(s0_eew) 77 val numSewLog2 = lmulLog2 - s0_sew 78 val numFlowsSameVdLog2 = Mux( 79 isIndexed(instType), 80 log2Up(VLENB).U - s0_sew(1,0), 81 log2Up(VLENB).U - s0_eew(1,0) 82 ) 83 // numUops = nf * max(lmul, emul) 84 val lmulLog2Pos = Mux(s0_lmul.asSInt < 0.S, 0.U, s0_lmul) 85 val emulLog2Pos = Mux(s0_emul.asSInt < 0.S, 0.U, s0_emul) 86 val numUops = Mux( 87 isIndexed(s0_mop) && s0_lmul.asSInt > s0_emul.asSInt, 88 (s0_nf +& 1.U) << lmulLog2Pos, 89 (s0_nf +& 1.U) << emulLog2Pos 90 ) 91 92 val vvl = io.in.bits.src_vl.asTypeOf(VConfig()).vl 93 val evl = Mux(isUsWholeReg, 94 GenUSWholeRegVL(io.in.bits.uop.vpu.nf +& 1.U, s0_eew), 95 Mux(isMaskReg, 96 GenUSMaskRegVL(vvl), 97 vvl)) 98 val vvstart = io.in.bits.uop.vpu.vstart 99 val alignedType = Mux(isIndexed(instType), s0_sew(1, 0), s0_eew(1, 0)) 100 val broadenAligendType = Mux(s0_preIsSplit, Cat("b0".U, alignedType), "b100".U) // if is unit-stride, use 128-bits memory access 101 val flowsLog2 = GenRealFlowLog2(instType, s0_emul, s0_lmul, s0_eew, s0_sew) 102 val flowsPrevThisUop = (uopIdxInField << flowsLog2).asUInt // # of flows before this uop in a field 103 val flowsPrevThisVd = (vdIdxInField << numFlowsSameVdLog2).asUInt // # of flows before this vd in a field 104 val flowsIncludeThisUop = ((uopIdxInField +& 1.U) << flowsLog2).asUInt // # of flows before this uop besides this uop 105 val flowNum = io.in.bits.flowNum.get 106 107 // For vectore indexed instructions: 108 // When emul is greater than lmul, multiple uop correspond to a Vd, e.g: 109 // vsetvli t1,t0,e8,m1,ta,ma lmul = 1 110 // vluxei16.v v2,(a0),v8 emul = 2 111 // In this case, we need to ensure the flownumis right shift by flowsPrevThisUop, However, the mask passed to mergebuff is right shift by flowsPrevThisVd e.g: 112 // vl = 9 113 // srcMask = 0x1FF 114 // uopIdxInField = 0 and vdIdxInField = 0, flowMask = 0x00FF, toMergeBuffMask = 0x01FF 115 // uopIdxInField = 1 and vdIdxInField = 0, flowMask = 0x0001, toMergeBuffMask = 0x01FF 116 // uopIdxInField = 0 and vdIdxInField = 0, flowMask = 0x0000, toMergeBuffMask = 0x0000 117 // uopIdxInField = 0 and vdIdxInField = 0, flowMask = 0x0000, toMergeBuffMask = 0x0000 118 val isSpecialIndexed = isIndexed(instType) && s0_emul.asSInt > s0_lmul.asSInt 119 120 val srcMask = GenFlowMask(Mux(s0_vm, Fill(VLEN, 1.U(1.W)), io.in.bits.src_mask), vvstart, evl, true) 121 val srcMaskShiftBits = Mux(isSpecialIndexed, flowsPrevThisUop, flowsPrevThisVd) 122 123 val flowMask = ((srcMask & 124 UIntToMask(flowsIncludeThisUop.asUInt, VLEN + 1) & 125 (~UIntToMask(flowsPrevThisUop.asUInt, VLEN)).asUInt 126 ) >> srcMaskShiftBits)(VLENB - 1, 0) 127 val indexedSrcMask = (srcMask >> flowsPrevThisVd).asUInt //only for index instructions 128 129 // Used to calculate the element index. 130 // See 'splitbuffer' for 'io.out.splitIdxOffset' and 'mergebuffer' for 'merge data' 131 val indexedSplitOffset = Mux(isSpecialIndexed, flowsPrevThisUop - flowsPrevThisVd, 0.U) // only for index instructions of emul > lmul 132 val vlmax = GenVLMAX(s0_lmul, s0_sew) 133 134 // connect 135 s0_out := DontCare 136 s0_out match {case x => 137 x.uop := io.in.bits.uop 138 x.uop.vpu.vl := evl 139 x.uop.uopIdx := uopIdx 140 x.uop.numUops := numUops 141 x.uop.lastUop := (uopIdx +& 1.U) === numUops 142 x.uop.vpu.nf := s0_nf 143 x.flowMask := flowMask 144 x.indexedSrcMask := indexedSrcMask // Only vector indexed instructions uses it 145 x.indexedSplitOffset := indexedSplitOffset 146 x.byteMask := GenUopByteMask(flowMask, Cat("b0".U, alignedType))(VLENB - 1, 0) 147 x.fof := isUnitStride(s0_mop) && us_fof(s0_fuOpType) 148 x.baseAddr := io.in.bits.src_rs1 149 x.stride := io.in.bits.src_stride 150 x.flowNum := flowNum 151 x.nfields := s0_nfield 152 x.vm := s0_vm 153 x.usWholeReg := isUsWholeReg 154 x.usMaskReg := isMaskReg 155 x.eew := s0_eew 156 x.sew := s0_sew 157 x.emul := s0_emul 158 x.lmul := s0_lmul 159 x.vlmax := Mux(isUsWholeReg, evl, vlmax) 160 x.instType := instType 161 x.data := io.in.bits.src_vs3 162 x.vdIdxInField := vdIdxInField 163 x.preIsSplit := s0_preIsSplit 164 x.alignedType := broadenAligendType 165 } 166 s0_valid := io.in.valid && !s0_kill 167 /**------------------------------------- 168 * s1 stage 169 * ------------------------------------ 170 * generate UopOffset 171 */ 172 val s1_valid = RegInit(false.B) 173 val s1_kill = Wire(Bool()) 174 val s1_in = Wire(new VLSBundle(isVStore)) 175 val s1_can_go = io.out.ready && io.toMergeBuffer.resp.valid 176 val s1_fire = s1_valid && !s1_kill && s1_can_go 177 178 s1_ready := s1_kill || !s1_valid || io.out.ready && io.toMergeBuffer.resp.valid 179 180 when(s0_fire){ 181 s1_valid := true.B 182 }.elsewhen(s1_fire){ 183 s1_valid := false.B 184 }.elsewhen(s1_kill){ 185 s1_valid := false.B 186 } 187 s1_in := RegEnable(s0_out, s0_fire) 188 189 val s1_flowNum = s1_in.flowNum 190 val s1_uopidx = s1_in.uop.vpu.vuopIdx 191 val s1_nf = s1_in.uop.vpu.nf 192 val s1_nfields = s1_in.nfields 193 val s1_eew = s1_in.eew 194 val s1_emul = s1_in.emul 195 val s1_lmul = s1_in.lmul 196 val s1_instType = s1_in.instType 197 val s1_stride = s1_in.stride 198 val s1_vmask = FillInterleaved(8, s1_in.byteMask)(VLEN-1, 0) 199 val s1_alignedType = s1_in.alignedType 200 val s1_isSpecialIndexed = isIndexed(s1_instType) && s1_emul.asSInt > s1_lmul.asSInt 201 val s1_mask = Mux(s1_isSpecialIndexed, s1_in.indexedSrcMask, s1_in.flowMask) 202 val s1_vdIdx = s1_in.vdIdxInField 203 val s1_fof = s1_in.fof 204 val s1_notIndexedStride = Mux( // stride for strided/unit-stride instruction 205 isStrided(s1_instType), 206 s1_stride(XLEN - 1, 0), // for strided load, stride = x[rs2] 207 s1_nfields << s1_eew(1, 0) // for unit-stride load, stride = eew * NFIELDS 208 ) 209 210 val stride = Mux(isIndexed(s1_instType), s1_stride, s1_notIndexedStride).asUInt // if is index instructions, get index when split 211 val uopOffset = genVUopOffset(s1_instType, s1_fof, s1_uopidx, s1_nf, s1_eew(1, 0), stride, s1_alignedType) 212 213 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) 214 215 // query mergeBuffer 216 io.toMergeBuffer.req.valid := s1_fire // only can_go will get MergeBuffer entry 217 io.toMergeBuffer.req.bits.flowNum := Mux(s1_in.preIsSplit, PopCount(s1_in.flowMask), s1_flowNum) 218 io.toMergeBuffer.req.bits.data := s1_in.data 219 io.toMergeBuffer.req.bits.uop := s1_in.uop 220 io.toMergeBuffer.req.bits.mask := s1_mask 221 io.toMergeBuffer.req.bits.vaddr := DontCare 222 io.toMergeBuffer.req.bits.vdIdx := s1_vdIdx //TODO vdIdxReg should no longer be useful, don't delete it for now 223 io.toMergeBuffer.req.bits.fof := s1_in.fof 224 io.toMergeBuffer.req.bits.vlmax := s1_in.vlmax 225// io.toMergeBuffer.req.bits.vdOffset := 226 227 //TODO vdIdxReg should no longer be useful, don't delete it for now 228// when (s1_in.uop.lastUop && s1_fire || s1_kill) { 229// vdIdxReg := 0.U 230// }.elsewhen(s1_fire) { 231// vdIdxReg := vdIdxReg + 1.U 232// XSError(vdIdxReg + 1.U === 0.U, s"Overflow! The number of vd should be less than 8\n") 233// } 234 // out connect 235 io.out.valid := s1_valid && io.toMergeBuffer.resp.valid 236 io.out.bits := s1_in 237 io.out.bits.uopOffset := uopOffset 238 io.out.bits.stride := stride 239 io.out.bits.mBIndex := io.toMergeBuffer.resp.bits.mBIndex 240 241 XSPerfAccumulate("split_out", io.out.fire) 242 XSPerfAccumulate("pipe_block", io.out.valid && !io.out.ready) 243 XSPerfAccumulate("mbuffer_block", s1_valid && io.out.ready && !io.toMergeBuffer.resp.valid) 244} 245 246abstract class VSplitBuffer(isVStore: Boolean = false)(implicit p: Parameters) extends VLSUModule{ 247 val io = IO(new VSplitBufferIO(isVStore)) 248 249 val bufferSize: Int 250 251 class VSplitPtr(implicit p: Parameters) extends CircularQueuePtr[VSplitPtr](bufferSize){ 252 } 253 254 object VSplitPtr { 255 def apply(f: Bool, v: UInt)(implicit p: Parameters): VSplitPtr = { 256 val ptr = Wire(new VSplitPtr) 257 ptr.flag := f 258 ptr.value := v 259 ptr 260 } 261 } 262 263 val uopq = Reg(Vec(bufferSize, new VLSBundle(isVStore))) 264 val valid = RegInit(VecInit(Seq.fill(bufferSize)(false.B))) 265 val srcMaskVec = Reg(Vec(bufferSize, UInt(VLEN.W))) 266 // ptr 267 val enqPtr = RegInit(0.U.asTypeOf(new VSplitPtr)) 268 val deqPtr = RegInit(0.U.asTypeOf(new VSplitPtr)) 269 // for split 270 val splitIdx = RegInit(0.U(flowIdxBits.W)) 271 val strideOffsetReg = RegInit(0.U(VLEN.W)) 272 273 /** 274 * Redirect 275 */ 276 val flushed = WireInit(VecInit(Seq.fill(bufferSize)(false.B))) // entry has been flushed by the redirect arrived in the pre 1 cycle 277 val flushVec = (valid zip flushed).zip(uopq).map { case ((v, f), entry) => v && entry.uop.robIdx.needFlush(io.redirect) && !f } 278 val flushEnq = io.in.fire && io.in.bits.uop.robIdx.needFlush(io.redirect) 279 val flushNumReg = RegNext(PopCount(flushEnq +: flushVec)) 280 val redirectReg = RegNext(io.redirect) 281 val flushVecReg = RegNext(WireInit(VecInit(flushVec))) 282 283 // enqueue, if redirect, it will be flush next cycle 284 when (io.in.fire) { 285 val id = enqPtr.value 286 uopq(id) := io.in.bits 287 valid(id) := true.B 288 } 289 io.in.ready := isNotBefore(enqPtr, deqPtr) 290 291 //split uops 292 val issueValid = valid(deqPtr.value) 293 val issueEntry = uopq(deqPtr.value) 294 val issueMbIndex = issueEntry.mBIndex 295 val issueFlowNum = issueEntry.flowNum 296 val issueBaseAddr = issueEntry.baseAddr 297 val issueUop = issueEntry.uop 298 val issueUopIdx = issueUop.vpu.vuopIdx 299 val issueInstType = issueEntry.instType 300 val issueUopOffset = issueEntry.uopOffset 301 val issueEew = issueEntry.eew 302 val issueSew = issueEntry.sew 303 val issueLmul = issueEntry.lmul 304 val issueEmul = issueEntry.emul 305 val issueAlignedType = issueEntry.alignedType 306 val issuePreIsSplit = issueEntry.preIsSplit 307 val issueByteMask = issueEntry.byteMask 308 val issueVLMAXMask = issueEntry.vlmax - 1.U 309 val issueIsWholeReg = issueEntry.usWholeReg 310 val issueVLMAXLog2 = GenVLMAXLog2(issueEntry.lmul, issueSew) 311 val elemIdx = GenElemIdx( 312 instType = issueInstType, 313 emul = issueEmul, 314 lmul = issueLmul, 315 eew = issueEew, 316 sew = issueSew, 317 uopIdx = issueUopIdx, 318 flowIdx = splitIdx 319 ) // elemIdx inside an inst, for exception 320 321 val splitIdxOffset = issueEntry.indexedSplitOffset + splitIdx 322 323 val elemIdxInsideField = elemIdx & issueVLMAXMask 324 val indexFlowInnerIdx = ((elemIdxInsideField << issueEew(1, 0))(vOffsetBits - 1, 0) >> issueEew(1, 0)).asUInt 325 val nfIdx = Mux(issueIsWholeReg, 0.U, elemIdx >> issueVLMAXLog2) 326 val fieldOffset = nfIdx << issueAlignedType // field offset inside a segment 327 328 val indexedStride = IndexAddr( // index for indexed instruction 329 index = issueEntry.stride, 330 flow_inner_idx = indexFlowInnerIdx, 331 eew = issueEew 332 ) 333 val issueStride = Mux(isIndexed(issueInstType), indexedStride, strideOffsetReg) 334 val vaddr = issueBaseAddr + issueUopOffset + issueStride 335 val mask = genVWmask128(vaddr ,issueAlignedType) // scala maske for flow 336 val flowMask = issueEntry.flowMask 337 val vecActive = (flowMask & UIntToOH(splitIdx)).orR 338 /* 339 * Unit-Stride split to one flow or two flow. 340 * for Unit-Stride, if uop's addr is aligned with 128-bits, split it to one flow, otherwise split two 341 */ 342 343 val usAligned128 = (vaddr(3,0) === 0.U)// addr 128-bit aligned 344 val usSplitMask = genUSSplitMask(issueByteMask, splitIdx, vaddr(3,0)) 345 val usNoSplit = (usAligned128 || !(vaddr(3,0) +& PopCount(usSplitMask))(4)) && !issuePreIsSplit && (splitIdx === 0.U)// unit-stride uop don't need to split into two flow 346 val usSplitVaddr = genUSSplitAddr(vaddr, splitIdx) 347 val regOffset = vaddr(3,0) // offset in 256-bits vd 348 XSError((splitIdx > 1.U && usNoSplit) || (splitIdx > 1.U && !issuePreIsSplit) , "Unit-Stride addr split error!\n") 349 350 // data 351 io.out.bits match { case x => 352 x.uop := issueUop 353 x.vaddr := Mux(!issuePreIsSplit, usSplitVaddr, vaddr) 354 x.alignedType := issueAlignedType 355 x.isvec := true.B 356 x.mask := Mux(!issuePreIsSplit, usSplitMask, mask) 357 x.reg_offset := regOffset //for merge unit-stride data 358 x.vecActive := vecActive 359 x.is_first_ele := DontCare 360 x.usSecondInv := usNoSplit 361 x.elemIdx := elemIdx 362 x.elemIdxInsideVd := splitIdxOffset // if is Unit-Stride, elemIdx is the index of 2 splited mem request (for merge data) 363 x.uop_unit_stride_fof := DontCare 364 x.isFirstIssue := DontCare 365 x.mBIndex := issueMbIndex 366 } 367 368 //update enqptr 369 when (redirectReg.valid && flushNumReg =/= 0.U) { 370 val enqPtrNext = enqPtr - flushNumReg 371 enqPtr := Mux(isBefore(enqPtrNext, deqPtr), deqPtr, enqPtrNext) 372 }.otherwise { 373 when (io.in.fire) { 374 enqPtr := enqPtr + 1.U 375 } 376 } 377 378 // flush queue 379 for (i <- 0 until bufferSize) { 380 when(flushVecReg(i) && redirectReg.valid && flushNumReg =/= 0.U) { 381 valid(i) := false.B 382 flushed(i) := true.B 383 } 384 } 385 386 /* Execute logic */ 387 /** Issue to scala pipeline**/ 388 val canIssue = Wire(Bool()) 389 val allowIssue = io.out.ready 390 val activeIssue = Wire(Bool()) 391 val deqValid = valid(deqPtr.value) 392 val inActiveIssue = deqValid && canIssue && !vecActive && issuePreIsSplit 393 val issueCount = Mux(usNoSplit, 2.U, (PopCount(inActiveIssue) + PopCount(activeIssue))) // for dont need split unit-stride, issue two flow 394 395 // handshake 396 val thisPtr = deqPtr.value 397 canIssue := !issueUop.robIdx.needFlush(io.redirect) && 398 !issueUop.robIdx.needFlush(redirectReg) && 399 deqPtr < enqPtr 400 activeIssue := canIssue && allowIssue && (vecActive || !issuePreIsSplit) // active issue, current use in no unit-stride 401 when (!RegNext(io.redirect.valid) || distanceBetween(enqPtr, deqPtr) > flushNumReg) { 402 when ((splitIdx < (issueFlowNum - issueCount))) { 403 when (activeIssue || inActiveIssue) { 404 // The uop has not been entirly splited yet 405 splitIdx := splitIdx + issueCount 406 strideOffsetReg := Mux(!issuePreIsSplit, strideOffsetReg, strideOffsetReg + issueEntry.stride) // when normal unit-stride, don't use strideOffsetReg 407 } 408 }.otherwise { 409 when (activeIssue || inActiveIssue) { 410 // The uop is done spliting 411 splitIdx := 0.U(flowIdxBits.W) // initialize flowIdx 412 valid(deqPtr.value) := false.B 413 strideOffsetReg := 0.U 414 deqPtr := deqPtr + 1.U 415 } 416 } 417 }.otherwise { 418 splitIdx := 0.U(flowIdxBits.W) // initialize flowIdx 419 strideOffsetReg := 0.U 420 } 421 422 // out connect 423 io.out.valid := canIssue && (vecActive || !issuePreIsSplit) // TODO: inactive uop do not send to pipeline 424 425 XSPerfAccumulate("out_valid", io.out.valid) 426 XSPerfAccumulate("out_fire", io.out.fire) 427 XSPerfAccumulate("out_fire_unitstride", io.out.fire && !issuePreIsSplit) 428 XSPerfAccumulate("unitstride_vlenAlign", io.out.fire && !issuePreIsSplit && io.out.bits.vaddr(3, 0) === 0.U) 429 XSPerfAccumulate("unitstride_invalid", io.out.ready && canIssue && !issuePreIsSplit && PopCount(io.out.bits.mask).orR) 430 431 QueuePerf(bufferSize, distanceBetween(enqPtr, deqPtr), !io.in.ready) 432} 433 434class VSSplitBufferImp(implicit p: Parameters) extends VSplitBuffer(isVStore = true){ 435 override lazy val bufferSize = SplitBufferSize 436 // split data 437 val splitData = genVSData( 438 data = issueEntry.data.asUInt, 439 elemIdx = splitIdxOffset, 440 alignedType = issueAlignedType 441 ) 442 val flowData = genVWdata(splitData, issueAlignedType) 443 val usSplitData = genUSSplitData(issueEntry.data.asUInt, splitIdx, vaddr(3,0)) 444 445 val sqIdx = issueUop.sqIdx + splitIdx 446 io.out.bits.uop.sqIdx := sqIdx 447 448 // send data to sq 449 val vstd = io.vstd.get 450 vstd.valid := canIssue 451 vstd.bits.uop := issueUop 452 vstd.bits.uop.sqIdx := sqIdx 453 vstd.bits.data := Mux(!issuePreIsSplit, usSplitData, flowData) 454 vstd.bits.debug := DontCare 455 vstd.bits.vdIdx.get := DontCare 456 vstd.bits.vdIdxInField.get := DontCare 457 vstd.bits.mask.get := Mux(!issuePreIsSplit, usSplitMask, mask) 458 459} 460 461class VLSplitBufferImp(implicit p: Parameters) extends VSplitBuffer(isVStore = false){ 462 override lazy val bufferSize = SplitBufferSize 463 io.out.bits.uop.lqIdx := issueUop.lqIdx + splitIdx 464} 465 466class VSSplitPipelineImp(implicit p: Parameters) extends VSplitPipeline(isVStore = true){ 467 override def us_whole_reg(fuOpType: UInt): Bool = fuOpType === VstuType.vsr 468 override def us_mask(fuOpType: UInt): Bool = fuOpType === VstuType.vsm 469 override def us_fof(fuOpType: UInt): Bool = false.B // dont have vector fof store 470} 471 472class VLSplitPipelineImp(implicit p: Parameters) extends VSplitPipeline(isVStore = false){ 473 474 override def us_whole_reg(fuOpType: UInt): Bool = fuOpType === VlduType.vlr 475 override def us_mask(fuOpType: UInt): Bool = fuOpType === VlduType.vlm 476 override def us_fof(fuOpType: UInt): Bool = fuOpType === VlduType.vleff 477} 478 479class VLSplitImp(implicit p: Parameters) extends VLSUModule{ 480 val io = IO(new VSplitIO(isVStore=false)) 481 val splitPipeline = Module(new VLSplitPipelineImp()) 482 val splitBuffer = Module(new VLSplitBufferImp()) 483 // Split Pipeline 484 splitPipeline.io.in <> io.in 485 splitPipeline.io.redirect <> io.redirect 486 io.toMergeBuffer <> splitPipeline.io.toMergeBuffer 487 488 // Split Buffer 489 splitBuffer.io.in <> splitPipeline.io.out 490 splitBuffer.io.redirect <> io.redirect 491 io.out <> splitBuffer.io.out 492} 493 494class VSSplitImp(implicit p: Parameters) extends VLSUModule{ 495 val io = IO(new VSplitIO(isVStore=true)) 496 val splitPipeline = Module(new VSSplitPipelineImp()) 497 val splitBuffer = Module(new VSSplitBufferImp()) 498 // Split Pipeline 499 splitPipeline.io.in <> io.in 500 splitPipeline.io.redirect <> io.redirect 501 io.toMergeBuffer <> splitPipeline.io.toMergeBuffer 502 503 // Split Buffer 504 splitBuffer.io.in <> splitPipeline.io.out 505 splitBuffer.io.redirect <> io.redirect 506 io.out <> splitBuffer.io.out 507 io.vstd.get <> splitBuffer.io.vstd.get 508} 509 510