1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.cache.{AtomicWordIO, MemoryOpConstants, HasDCacheParameters} 26import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 27import difftest._ 28import xiangshan.ExceptionNO._ 29import xiangshan.backend.fu.PMPRespBundle 30 31class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants with HasDCacheParameters{ 32 val io = IO(new Bundle() { 33 val hartId = Input(UInt(8.W)) 34 val in = Flipped(Decoupled(new ExuInput)) 35 val storeDataIn = Flipped(Valid(new ExuOutput)) // src2 from rs 36 val out = Decoupled(new ExuOutput) 37 val dcache = new AtomicWordIO 38 val dtlb = new TlbRequestIO(2) 39 val pmpResp = Flipped(new PMPRespBundle()) 40 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 41 val flush_sbuffer = new SbufferFlushBundle 42 val feedbackSlow = ValidIO(new RSFeedback) 43 val redirect = Flipped(ValidIO(new Redirect)) 44 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 45 val csrCtrl = Flipped(new CustomCSRCtrlIO) 46 }) 47 48 //------------------------------------------------------- 49 // Atomics Memory Accsess FSM 50 //------------------------------------------------------- 51 val s_invalid :: s_tlb_and_flush_sbuffer_req :: s_pm :: s_wait_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_cache_resp_latch :: s_finish :: Nil = Enum(8) 52 val state = RegInit(s_invalid) 53 val out_valid = RegInit(false.B) 54 val data_valid = RegInit(false.B) 55 val in = Reg(new ExuInput()) 56 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 57 val atom_override_xtval = RegInit(false.B) 58 val have_sent_first_tlb_req = RegInit(false.B) 59 val isLr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 60 // paddr after translation 61 val paddr = Reg(UInt()) 62 val vaddr = in.src(0) 63 val is_mmio = Reg(Bool()) 64 65 // dcache response data 66 val resp_data = Reg(UInt()) 67 val resp_data_wire = WireInit(0.U) 68 val is_lrsc_valid = Reg(Bool()) 69 // sbuffer is empty or not 70 val sbuffer_empty = io.flush_sbuffer.empty 71 72 73 // Difftest signals 74 val paddr_reg = Reg(UInt(64.W)) 75 val data_reg = Reg(UInt(64.W)) 76 val mask_reg = Reg(UInt(8.W)) 77 val fuop_reg = Reg(UInt(8.W)) 78 79 io.exceptionAddr.valid := atom_override_xtval 80 io.exceptionAddr.bits := in.src(0) 81 82 // assign default value to output signals 83 io.in.ready := false.B 84 85 io.dcache.req.valid := false.B 86 io.dcache.req.bits := DontCare 87 88 io.dtlb.req.valid := false.B 89 io.dtlb.req.bits := DontCare 90 io.dtlb.req_kill := false.B 91 io.dtlb.resp.ready := true.B 92 93 io.flush_sbuffer.valid := false.B 94 95 XSDebug("state: %d\n", state) 96 97 when (state === s_invalid) { 98 io.in.ready := true.B 99 when (io.in.fire) { 100 in := io.in.bits 101 in.src(1) := in.src(1) // leave src2 unchanged 102 state := s_tlb_and_flush_sbuffer_req 103 have_sent_first_tlb_req := false.B 104 } 105 } 106 107 when (io.storeDataIn.fire) { 108 in.src(1) := io.storeDataIn.bits.data 109 data_valid := true.B 110 } 111 112 assert(!(io.storeDataIn.fire && data_valid), "atomic unit re-receive data") 113 114 // Send TLB feedback to store issue queue 115 // we send feedback right after we receives request 116 // also, we always treat amo as tlb hit 117 // since we will continue polling tlb all by ourself 118 io.feedbackSlow.valid := RegNext(RegNext(io.in.valid)) 119 io.feedbackSlow.bits.hit := true.B 120 io.feedbackSlow.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 121 io.feedbackSlow.bits.flushState := DontCare 122 io.feedbackSlow.bits.sourceType := DontCare 123 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 124 125 // tlb translation, manipulating signals && deal with exception 126 // at the same time, flush sbuffer 127 when (state === s_tlb_and_flush_sbuffer_req) { 128 // send req to dtlb 129 // keep firing until tlb hit 130 io.dtlb.req.valid := true.B 131 io.dtlb.req.bits.vaddr := in.src(0) 132 io.dtlb.resp.ready := true.B 133 io.dtlb.req.bits.cmd := Mux(isLr, TlbCmd.atom_read, TlbCmd.atom_write) 134 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 135 io.dtlb.req.bits.debug.isFirstIssue := false.B 136 io.out.bits.uop.debugInfo.tlbFirstReqTime := GTimer() // FIXME lyq: it will be always assigned 137 138 // send req to sbuffer to flush it if it is not empty 139 io.flush_sbuffer.valid := Mux(sbuffer_empty, false.B, true.B) 140 141 // do not accept tlb resp in the first cycle 142 // this limition is for hw prefetcher 143 // when !have_sent_first_tlb_req, tlb resp may come from hw prefetch 144 have_sent_first_tlb_req := true.B 145 146 when(io.dtlb.resp.fire && have_sent_first_tlb_req){ 147 paddr := io.dtlb.resp.bits.paddr(0) 148 // exception handling 149 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 150 "b00".U -> true.B, //b 151 "b01".U -> (in.src(0)(0) === 0.U), //h 152 "b10".U -> (in.src(0)(1,0) === 0.U), //w 153 "b11".U -> (in.src(0)(2,0) === 0.U) //d 154 )) 155 exceptionVec(loadAddrMisaligned) := !addrAligned && isLr 156 exceptionVec(storeAddrMisaligned) := !addrAligned && !isLr 157 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp(0).pf.st 158 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp(0).pf.ld 159 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp(0).af.st 160 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp(0).af.ld 161 162 when (!io.dtlb.resp.bits.miss) { 163 io.out.bits.uop.debugInfo.tlbRespTime := GTimer() 164 when (!addrAligned) { 165 // NOTE: when addrAligned, do not need to wait tlb actually 166 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 167 // if there are exceptions, no need to execute it 168 state := s_finish 169 out_valid := true.B 170 atom_override_xtval := true.B 171 } .otherwise { 172 state := s_pm 173 } 174 } 175 } 176 } 177 178 when (state === s_pm) { 179 val pmp = WireInit(io.pmpResp) 180 is_mmio := pmp.mmio 181 182 // NOTE: only handle load/store exception here, if other exception happens, don't send here 183 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 184 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 185 val exception_pa = pmp.st || pmp.ld 186 when (exception_va || exception_pa) { 187 state := s_finish 188 out_valid := true.B 189 atom_override_xtval := true.B 190 }.otherwise { 191 // if sbuffer has been flushed, go to query dcache, otherwise wait for sbuffer. 192 state := Mux(sbuffer_empty, s_cache_req, s_wait_flush_sbuffer_resp); 193 } 194 // update storeAccessFault bit 195 exceptionVec(loadAccessFault) := exceptionVec(loadAccessFault) || pmp.ld && isLr 196 exceptionVec(storeAccessFault) := exceptionVec(storeAccessFault) || pmp.st || pmp.ld && !isLr 197 } 198 199 when (state === s_wait_flush_sbuffer_resp) { 200 when (sbuffer_empty) { 201 state := s_cache_req 202 } 203 } 204 205 when (state === s_cache_req) { 206 val pipe_req = io.dcache.req.bits 207 pipe_req := DontCare 208 209 pipe_req.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 210 LSUOpType.lr_w -> M_XLR, 211 LSUOpType.sc_w -> M_XSC, 212 LSUOpType.amoswap_w -> M_XA_SWAP, 213 LSUOpType.amoadd_w -> M_XA_ADD, 214 LSUOpType.amoxor_w -> M_XA_XOR, 215 LSUOpType.amoand_w -> M_XA_AND, 216 LSUOpType.amoor_w -> M_XA_OR, 217 LSUOpType.amomin_w -> M_XA_MIN, 218 LSUOpType.amomax_w -> M_XA_MAX, 219 LSUOpType.amominu_w -> M_XA_MINU, 220 LSUOpType.amomaxu_w -> M_XA_MAXU, 221 222 LSUOpType.lr_d -> M_XLR, 223 LSUOpType.sc_d -> M_XSC, 224 LSUOpType.amoswap_d -> M_XA_SWAP, 225 LSUOpType.amoadd_d -> M_XA_ADD, 226 LSUOpType.amoxor_d -> M_XA_XOR, 227 LSUOpType.amoand_d -> M_XA_AND, 228 LSUOpType.amoor_d -> M_XA_OR, 229 LSUOpType.amomin_d -> M_XA_MIN, 230 LSUOpType.amomax_d -> M_XA_MAX, 231 LSUOpType.amominu_d -> M_XA_MINU, 232 LSUOpType.amomaxu_d -> M_XA_MAXU 233 )) 234 pipe_req.miss := false.B 235 pipe_req.probe := false.B 236 pipe_req.probe_need_data := false.B 237 pipe_req.source := AMO_SOURCE.U 238 pipe_req.addr := get_block_addr(paddr) 239 pipe_req.vaddr := get_block_addr(in.src(0)) // vaddr 240 pipe_req.word_idx := get_word(paddr) 241 pipe_req.amo_data := genWdata(in.src(1), in.uop.ctrl.fuOpType(1,0)) 242 pipe_req.amo_mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 243 244 io.dcache.req.valid := Mux( 245 io.dcache.req.bits.cmd === M_XLR, 246 !io.dcache.block_lr, // block lr to survive in lr storm 247 data_valid // wait until src(1) is ready 248 ) 249 250 when(io.dcache.req.fire){ 251 state := s_cache_resp 252 paddr_reg := paddr 253 data_reg := io.dcache.req.bits.amo_data 254 mask_reg := io.dcache.req.bits.amo_mask 255 fuop_reg := in.uop.ctrl.fuOpType 256 } 257 } 258 259 val dcache_resp_data = Reg(UInt()) 260 val dcache_resp_id = Reg(UInt()) 261 val dcache_resp_error = Reg(Bool()) 262 263 when (state === s_cache_resp) { 264 // when not miss 265 // everything is OK, simply send response back to sbuffer 266 // when miss and not replay 267 // wait for missQueue to handling miss and replaying our request 268 // when miss and replay 269 // req missed and fail to enter missQueue, manually replay it later 270 // TODO: add assertions: 271 // 1. add a replay delay counter? 272 // 2. when req gets into MissQueue, it should not miss any more 273 when(io.dcache.resp.fire()) { 274 when(io.dcache.resp.bits.miss) { 275 when(io.dcache.resp.bits.replay) { 276 state := s_cache_req 277 } 278 } .otherwise { 279 dcache_resp_data := io.dcache.resp.bits.data 280 dcache_resp_id := io.dcache.resp.bits.id 281 dcache_resp_error := io.dcache.resp.bits.error 282 state := s_cache_resp_latch 283 } 284 } 285 } 286 287 when (state === s_cache_resp_latch) { 288 is_lrsc_valid := dcache_resp_id 289 val rdataSel = LookupTree(paddr(2, 0), List( 290 "b000".U -> dcache_resp_data(63, 0), 291 "b001".U -> dcache_resp_data(63, 8), 292 "b010".U -> dcache_resp_data(63, 16), 293 "b011".U -> dcache_resp_data(63, 24), 294 "b100".U -> dcache_resp_data(63, 32), 295 "b101".U -> dcache_resp_data(63, 40), 296 "b110".U -> dcache_resp_data(63, 48), 297 "b111".U -> dcache_resp_data(63, 56) 298 )) 299 300 resp_data_wire := LookupTree(in.uop.ctrl.fuOpType, List( 301 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 302 LSUOpType.sc_w -> dcache_resp_data, 303 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 304 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 305 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 306 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 307 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 308 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 309 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 310 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 311 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 312 313 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 314 LSUOpType.sc_d -> dcache_resp_data, 315 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 316 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 317 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 318 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 319 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 320 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 321 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 322 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 323 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 324 )) 325 326 when (dcache_resp_error && io.csrCtrl.cache_error_enable) { 327 exceptionVec(loadAccessFault) := isLr 328 exceptionVec(storeAccessFault) := !isLr 329 assert(!exceptionVec(loadAccessFault)) 330 assert(!exceptionVec(storeAccessFault)) 331 } 332 333 resp_data := resp_data_wire 334 state := s_finish 335 out_valid := true.B 336 } 337 338 io.out.valid := out_valid 339 XSError((state === s_finish) =/= out_valid, "out_valid reg error\n") 340 io.out.bits := DontCare 341 io.out.bits.uop := in.uop 342 io.out.bits.uop.cf.exceptionVec := exceptionVec 343 io.out.bits.data := resp_data 344 io.out.bits.redirectValid := false.B 345 io.out.bits.debug.isMMIO := is_mmio 346 io.out.bits.debug.paddr := paddr 347 when (io.out.fire) { 348 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 349 state := s_invalid 350 out_valid := false.B 351 } 352 353 when (state === s_finish) { 354 data_valid := false.B 355 } 356 357 when (io.redirect.valid) { 358 atom_override_xtval := false.B 359 } 360 361 // atomic trigger 362 val csrCtrl = io.csrCtrl 363 val tdata = Reg(Vec(6, new MatchTriggerIO)) 364 val tEnable = RegInit(VecInit(Seq.fill(6)(false.B))) 365 val en = csrCtrl.trigger_enable 366 tEnable := VecInit(en(2), en (3), en(7), en(4), en(5), en(9)) 367 when(csrCtrl.mem_trigger.t.valid) { 368 tdata(csrCtrl.mem_trigger.t.bits.addr) := csrCtrl.mem_trigger.t.bits.tdata 369 } 370 val lTriggerMapping = Map(0 -> 2, 1 -> 3, 2 -> 5) 371 val sTriggerMapping = Map(0 -> 0, 1 -> 1, 2 -> 4) 372 373 val backendTriggerHitReg = Reg(Vec(6, Bool())) 374 backendTriggerHitReg := VecInit(Seq.fill(6)(false.B)) 375 376 when(state === s_cache_req){ 377 // store trigger 378 val store_hit = Wire(Vec(3, Bool())) 379 for (j <- 0 until 3) { 380 store_hit(j) := !tdata(sTriggerMapping(j)).select && TriggerCmp( 381 vaddr, 382 tdata(sTriggerMapping(j)).tdata2, 383 tdata(sTriggerMapping(j)).matchType, 384 tEnable(sTriggerMapping(j)) 385 ) 386 backendTriggerHitReg(sTriggerMapping(j)) := store_hit(j) 387 } 388 389 when(tdata(0).chain) { 390 backendTriggerHitReg(0) := store_hit(0) && store_hit(1) 391 backendTriggerHitReg(1) := store_hit(0) && store_hit(1) 392 } 393 394 when(!in.uop.cf.trigger.backendEn(0)) { 395 backendTriggerHitReg(4) := false.B 396 } 397 398 // load trigger 399 val load_hit = Wire(Vec(3, Bool())) 400 for (j <- 0 until 3) { 401 402 val addrHit = TriggerCmp( 403 vaddr, 404 tdata(lTriggerMapping(j)).tdata2, 405 tdata(lTriggerMapping(j)).matchType, 406 tEnable(lTriggerMapping(j)) 407 ) 408 load_hit(j) := addrHit && !tdata(lTriggerMapping(j)).select 409 backendTriggerHitReg(lTriggerMapping(j)) := load_hit(j) 410 } 411 when(tdata(2).chain) { 412 backendTriggerHitReg(2) := load_hit(0) && load_hit(1) 413 backendTriggerHitReg(3) := load_hit(0) && load_hit(1) 414 } 415 when(!in.uop.cf.trigger.backendEn(1)) { 416 backendTriggerHitReg(5) := false.B 417 } 418 } 419 420 // addr trigger do cmp at s_cache_req 421 // trigger result is used at s_finish 422 // thus we can delay it safely 423 io.out.bits.uop.cf.trigger.backendHit := VecInit(Seq.fill(6)(false.B)) 424 when(isLr){ 425 // enable load trigger 426 io.out.bits.uop.cf.trigger.backendHit(2) := backendTriggerHitReg(2) 427 io.out.bits.uop.cf.trigger.backendHit(3) := backendTriggerHitReg(3) 428 io.out.bits.uop.cf.trigger.backendHit(5) := backendTriggerHitReg(5) 429 }.otherwise{ 430 // enable store trigger 431 io.out.bits.uop.cf.trigger.backendHit(0) := backendTriggerHitReg(0) 432 io.out.bits.uop.cf.trigger.backendHit(1) := backendTriggerHitReg(1) 433 io.out.bits.uop.cf.trigger.backendHit(4) := backendTriggerHitReg(4) 434 } 435 436 if (env.EnableDifftest) { 437 val difftest = DifftestModule(new DiffAtomicEvent) 438 difftest.clock := clock 439 difftest.coreid := io.hartId 440 difftest.valid := state === s_cache_resp_latch 441 difftest.addr := paddr_reg 442 difftest.data := data_reg 443 difftest.mask := mask_reg 444 difftest.fuop := fuop_reg 445 difftest.out := resp_data_wire 446 } 447 448 if (env.EnableDifftest || env.AlwaysBasicDiff) { 449 val uop = io.out.bits.uop 450 val difftest = DifftestModule(new DiffLrScEvent) 451 difftest.clock := clock 452 difftest.coreid := io.hartId 453 difftest.valid := io.out.fire && 454 (uop.ctrl.fuOpType === LSUOpType.sc_d || uop.ctrl.fuOpType === LSUOpType.sc_w) 455 difftest.success := is_lrsc_valid 456 } 457} 458