1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.fu.FuConfig._ 26import xiangshan.backend.fu.fpu.FPU 27import xiangshan.backend.rob.RobLsqIO 28import xiangshan.cache._ 29import xiangshan.frontend.FtqPtr 30import xiangshan.ExceptionNO._ 31import xiangshan.cache.wpu.ReplayCarry 32import xiangshan.backend.rob.RobPtr 33import xiangshan.backend.Bundles.{MemExuOutput, DynInst} 34 35class LoadMisalignBuffer(implicit p: Parameters) extends XSModule 36 with HasCircularQueuePtrHelper 37 with HasLoadHelper 38{ 39 private val enqPortNum = LoadPipelineWidth 40 private val maxSplitNum = 2 41 42 require(maxSplitNum == 2) 43 44 private val LB = "b00".U(2.W) 45 private val LH = "b01".U(2.W) 46 private val LW = "b10".U(2.W) 47 private val LD = "b11".U(2.W) 48 49 // encode of how many bytes to shift or truncate 50 private val BYTE0 = "b000".U(3.W) 51 private val BYTE1 = "b001".U(3.W) 52 private val BYTE2 = "b010".U(3.W) 53 private val BYTE3 = "b011".U(3.W) 54 private val BYTE4 = "b100".U(3.W) 55 private val BYTE5 = "b101".U(3.W) 56 private val BYTE6 = "b110".U(3.W) 57 private val BYTE7 = "b111".U(3.W) 58 59 def getMask(sizeEncode: UInt) = LookupTree(sizeEncode, List( 60 LB -> 0x1.U, // lb 61 LH -> 0x3.U, // lh 62 LW -> 0xf.U, // lw 63 LD -> 0xff.U // ld 64 )) 65 66 def getShiftAndTruncateData(shiftEncode: UInt, truncateEncode: UInt, data: UInt) = { 67 val shiftData = LookupTree(shiftEncode, List( 68 BYTE0 -> data(63, 0), 69 BYTE1 -> data(63, 8), 70 BYTE2 -> data(63, 16), 71 BYTE3 -> data(63, 24), 72 BYTE4 -> data(63, 32), 73 BYTE5 -> data(63, 40), 74 BYTE6 -> data(63, 48), 75 BYTE7 -> data(63, 56) 76 )) 77 val truncateData = LookupTree(truncateEncode, List( 78 BYTE0 -> 0.U(XLEN.W), // can not truncate with 0 byte width 79 BYTE1 -> shiftData(7, 0), 80 BYTE2 -> shiftData(15, 0), 81 BYTE3 -> shiftData(23, 0), 82 BYTE4 -> shiftData(31, 0), 83 BYTE5 -> shiftData(39, 0), 84 BYTE6 -> shiftData(47, 0), 85 BYTE7 -> shiftData(55, 0) 86 )) 87 truncateData(XLEN - 1, 0) 88 } 89 90 def selectOldest[T <: LqWriteBundle](valid: Seq[Bool], bits: Seq[T]): (Seq[Bool], Seq[T]) = { 91 assert(valid.length == bits.length) 92 if (valid.length == 0 || valid.length == 1) { 93 (valid, bits) 94 } else if (valid.length == 2) { 95 val res = Seq.fill(2)(Wire(ValidIO(chiselTypeOf(bits(0))))) 96 for (i <- res.indices) { 97 res(i).valid := valid(i) 98 res(i).bits := bits(i) 99 } 100 val oldest = Mux(valid(0) && valid(1), 101 Mux(isAfter(bits(0).uop.robIdx, bits(1).uop.robIdx) || 102 (isNotBefore(bits(0).uop.robIdx, bits(1).uop.robIdx) && bits(0).uop.uopIdx > bits(1).uop.uopIdx), res(1), res(0)), 103 Mux(valid(0) && !valid(1), res(0), res(1))) 104 (Seq(oldest.valid), Seq(oldest.bits)) 105 } else { 106 val left = selectOldest(valid.take(valid.length / 2), bits.take(bits.length / 2)) 107 val right = selectOldest(valid.takeRight(valid.length - (valid.length / 2)), bits.takeRight(bits.length - (bits.length / 2))) 108 selectOldest(left._1 ++ right._1, left._2 ++ right._2) 109 } 110 } 111 112 val io = IO(new Bundle() { 113 val redirect = Flipped(Valid(new Redirect)) 114 val req = Vec(enqPortNum, Flipped(Valid(new LqWriteBundle))) 115 val rob = Flipped(new RobLsqIO) 116 val splitLoadReq = Decoupled(new LsPipelineBundle) 117 val splitLoadResp = Flipped(Valid(new LqWriteBundle)) 118 val writeBack = Decoupled(new MemExuOutput) 119 val overwriteExpBuf = Output(new XSBundle { 120 val valid = Bool() 121 val vaddr = UInt(VAddrBits.W) 122 }) 123 val flushLdExpBuff = Output(Bool()) 124 }) 125 126 io.rob.mmio := 0.U.asTypeOf(Vec(LoadPipelineWidth, Bool())) 127 io.rob.uop := 0.U.asTypeOf(Vec(LoadPipelineWidth, new DynInst)) 128 129 val req_valid = RegInit(false.B) 130 val req = Reg(new LqWriteBundle) 131 132 // enqueue 133 // s1: 134 val s1_req = VecInit(io.req.map(_.bits)) 135 val s1_valid = VecInit(io.req.map(x => x.valid)) 136 137 // s2: delay 1 cycle 138 val s2_req = RegNext(s1_req) 139 val s2_valid = (0 until enqPortNum).map(i => 140 RegNext(s1_valid(i)) && 141 !s2_req(i).uop.robIdx.needFlush(RegNext(io.redirect)) && 142 !s2_req(i).uop.robIdx.needFlush(io.redirect) 143 ) 144 val s2_miss_aligned = s2_req.map(x => x.uop.exceptionVec(loadAddrMisaligned)) 145 146 val s2_enqueue = Wire(Vec(enqPortNum, Bool())) 147 for (w <- 0 until enqPortNum) { 148 s2_enqueue(w) := s2_valid(w) && s2_miss_aligned(w) 149 } 150 151 when (req_valid && req.uop.robIdx.needFlush(io.redirect)) { 152 req_valid := s2_enqueue.asUInt.orR 153 } .elsewhen (s2_enqueue.asUInt.orR) { 154 req_valid := req_valid || true.B 155 } 156 157 val reqSel = selectOldest(s2_enqueue, s2_req) 158 159 when (req_valid) { 160 req := Mux( 161 reqSel._1(0) && (isAfter(req.uop.robIdx, reqSel._2(0).uop.robIdx) || (isNotBefore(req.uop.robIdx, reqSel._2(0).uop.robIdx) && req.uop.uopIdx > reqSel._2(0).uop.uopIdx)), 162 reqSel._2(0), 163 req) 164 } .elsewhen (s2_enqueue.asUInt.orR) { 165 req := reqSel._2(0) 166 } 167 168 val robMatch = req_valid && io.rob.pendingld && (io.rob.pendingPtr === req.uop.robIdx) 169 170 // buffer control: 171 // - split miss-aligned load into aligned loads 172 // - send split load to ldu and get result from ldu 173 // - merge them and write back to rob 174 val s_idle :: s_split :: s_req :: s_resp :: s_comb :: s_wb :: s_wait :: Nil = Enum(7) 175 val bufferState = RegInit(s_idle) 176 val splitLoadReqs = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new LsPipelineBundle)))) 177 val splitLoadResp = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new LqWriteBundle)))) 178 val unSentLoads = RegInit(0.U(maxSplitNum.W)) 179 val curPtr = RegInit(0.U(log2Ceil(maxSplitNum).W)) 180 181 // if there is exception or mmio in split load 182 val globalException = RegInit(false.B) 183 val globalMMIO = RegInit(false.B) 184 185 val hasException = ExceptionNO.selectByFu(io.splitLoadResp.bits.uop.exceptionVec, LduCfg).asUInt.orR 186 val isMMIO = io.splitLoadResp.bits.mmio 187 188 switch(bufferState) { 189 is (s_idle) { 190 when (robMatch) { 191 bufferState := s_split 192 } 193 } 194 195 is (s_split) { 196 bufferState := s_req 197 } 198 199 is (s_req) { 200 when (io.splitLoadReq.fire) { 201 bufferState := s_resp 202 } 203 } 204 205 is (s_resp) { 206 when (io.splitLoadResp.valid) { 207 val clearOh = UIntToOH(curPtr) 208 when (hasException || isMMIO) { 209 // commit directly when exception ocurs 210 // if any split load reaches mmio space, delegate to software loadAddrMisaligned exception 211 bufferState := s_wb 212 globalException := hasException 213 globalMMIO := isMMIO 214 } .elsewhen(io.splitLoadResp.bits.rep_info.need_rep || (unSentLoads & ~clearOh).orR) { 215 // need replay or still has unsent requests 216 bufferState := s_req 217 } .otherwise { 218 // merge the split load results 219 bufferState := s_comb 220 } 221 } 222 } 223 224 is (s_comb) { 225 bufferState := s_wb 226 } 227 228 is (s_wb) { 229 when(io.writeBack.fire) { 230 bufferState := s_wait 231 } 232 } 233 234 is (s_wait) { 235 when(io.rob.lcommit =/= 0.U || req.uop.robIdx.needFlush(io.redirect)) { 236 // rob commits the unaligned load or handled the exception, reset all state 237 bufferState := s_idle 238 req_valid := false.B 239 curPtr := 0.U 240 unSentLoads := 0.U 241 globalException := false.B 242 globalMMIO := false.B 243 } 244 } 245 } 246 247 val highAddress = LookupTree(req.uop.fuOpType(1, 0), List( 248 LB -> 0.U, 249 LH -> 1.U, 250 LW -> 3.U, 251 LD -> 7.U 252 )) + req.vaddr(4, 0) 253 // to see if (vaddr + opSize - 1) and vaddr are in the same 16 bytes region 254 val cross16BytesBoundary = req_valid && (highAddress(4) =/= req.vaddr(4)) 255 val aligned16BytesAddr = (req.vaddr >> 4) << 4// req.vaddr & ~("b1111".U) 256 val aligned16BytesSel = req.vaddr(3, 0) 257 258 // meta of 128 bit load 259 val new128Load = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 260 // meta of split loads 261 val lowAddrLoad = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 262 val highAddrLoad = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 263 val lowResultShift = RegInit(0.U(3.W)) // how many bytes should we shift right when got result 264 val lowResultWidth = RegInit(0.U(3.W)) // how many bytes should we take from result 265 val highResultShift = RegInit(0.U(3.W)) 266 val highResultWidth = RegInit(0.U(3.W)) 267 268 when (bufferState === s_split) { 269 when (!cross16BytesBoundary) { 270 // change this unaligned load into a 128 bits load 271 unSentLoads := 1.U 272 curPtr := 0.U 273 new128Load.vaddr := aligned16BytesAddr 274 // new128Load.mask := (getMask(req.uop.fuOpType(1, 0)) << aligned16BytesSel).asUInt 275 new128Load.mask := 0xffff.U 276 new128Load.uop := req.uop 277 new128Load.uop.exceptionVec(loadAddrMisaligned) := false.B 278 new128Load.is128bit := true.B 279 splitLoadReqs(0) := new128Load 280 } .otherwise { 281 // split this unaligned load into `maxSplitNum` aligned loads 282 unSentLoads := Fill(maxSplitNum, 1.U(1.W)) 283 curPtr := 0.U 284 lowAddrLoad.uop := req.uop 285 lowAddrLoad.uop.exceptionVec(loadAddrMisaligned) := false.B 286 highAddrLoad.uop := req.uop 287 highAddrLoad.uop.exceptionVec(loadAddrMisaligned) := false.B 288 289 switch (req.uop.fuOpType(1, 0)) { 290 is (LB) { 291 assert(false.B, "lb should not trigger miss align") 292 } 293 294 is (LH) { 295 lowAddrLoad.uop.fuOpType := LB 296 lowAddrLoad.vaddr := req.vaddr 297 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 298 lowResultShift := BYTE0 299 lowResultWidth := BYTE1 300 301 highAddrLoad.uop.fuOpType := LB 302 highAddrLoad.vaddr := req.vaddr + 1.U 303 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 304 highResultShift := BYTE0 305 highResultWidth := BYTE1 306 } 307 308 is (LW) { 309 switch (req.vaddr(1, 0)) { 310 is ("b00".U) { 311 assert(false.B, "should not trigger miss align") 312 } 313 314 is ("b01".U) { 315 lowAddrLoad.uop.fuOpType := LW 316 lowAddrLoad.vaddr := req.vaddr - 1.U 317 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 318 lowResultShift := BYTE1 319 lowResultWidth := BYTE3 320 321 highAddrLoad.uop.fuOpType := LB 322 highAddrLoad.vaddr := req.vaddr + 3.U 323 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 324 highResultShift := BYTE0 325 highResultWidth := BYTE1 326 } 327 328 is ("b10".U) { 329 lowAddrLoad.uop.fuOpType := LH 330 lowAddrLoad.vaddr := req.vaddr 331 lowAddrLoad.mask := 0x3.U << lowAddrLoad.vaddr(3, 0) 332 lowResultShift := BYTE0 333 lowResultWidth := BYTE2 334 335 highAddrLoad.uop.fuOpType := LH 336 highAddrLoad.vaddr := req.vaddr + 2.U 337 highAddrLoad.mask := 0x3.U << highAddrLoad.vaddr(3, 0) 338 highResultShift := BYTE0 339 highResultWidth := BYTE2 340 } 341 342 is ("b11".U) { 343 lowAddrLoad.uop.fuOpType := LB 344 lowAddrLoad.vaddr := req.vaddr 345 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 346 lowResultShift := BYTE0 347 lowResultWidth := BYTE1 348 349 highAddrLoad.uop.fuOpType := LW 350 highAddrLoad.vaddr := req.vaddr + 1.U 351 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 352 highResultShift := BYTE0 353 highResultWidth := BYTE3 354 } 355 } 356 } 357 358 is (LD) { 359 switch (req.vaddr(2, 0)) { 360 is ("b000".U) { 361 assert(false.B, "should not trigger miss align") 362 } 363 364 is ("b001".U) { 365 lowAddrLoad.uop.fuOpType := LD 366 lowAddrLoad.vaddr := req.vaddr - 1.U 367 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 368 lowResultShift := BYTE1 369 lowResultWidth := BYTE7 370 371 highAddrLoad.uop.fuOpType := LB 372 highAddrLoad.vaddr := req.vaddr + 7.U 373 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 374 highResultShift := BYTE0 375 highResultWidth := BYTE1 376 } 377 378 is ("b010".U) { 379 lowAddrLoad.uop.fuOpType := LD 380 lowAddrLoad.vaddr := req.vaddr - 2.U 381 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 382 lowResultShift := BYTE2 383 lowResultWidth := BYTE6 384 385 highAddrLoad.uop.fuOpType := LH 386 highAddrLoad.vaddr := req.vaddr + 6.U 387 highAddrLoad.mask := 0x3.U << highAddrLoad.vaddr(3, 0) 388 highResultShift := BYTE0 389 highResultWidth := BYTE2 390 } 391 392 is ("b011".U) { 393 lowAddrLoad.uop.fuOpType := LD 394 lowAddrLoad.vaddr := req.vaddr - 3.U 395 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 396 lowResultShift := BYTE3 397 lowResultWidth := BYTE5 398 399 highAddrLoad.uop.fuOpType := LW 400 highAddrLoad.vaddr := req.vaddr + 5.U 401 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 402 highResultShift := BYTE0 403 highResultWidth := BYTE3 404 } 405 406 is ("b100".U) { 407 lowAddrLoad.uop.fuOpType := LW 408 lowAddrLoad.vaddr := req.vaddr 409 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 410 lowResultShift := BYTE0 411 lowResultWidth := BYTE4 412 413 highAddrLoad.uop.fuOpType := LW 414 highAddrLoad.vaddr := req.vaddr + 4.U 415 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 416 highResultShift := BYTE0 417 highResultWidth := BYTE4 418 } 419 420 is ("b101".U) { 421 lowAddrLoad.uop.fuOpType := LW 422 lowAddrLoad.vaddr := req.vaddr - 1.U 423 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 424 lowResultShift := BYTE1 425 lowResultWidth := BYTE3 426 427 highAddrLoad.uop.fuOpType := LD 428 highAddrLoad.vaddr := req.vaddr + 3.U 429 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 430 highResultShift := BYTE0 431 highResultWidth := BYTE5 432 } 433 434 is ("b110".U) { 435 lowAddrLoad.uop.fuOpType := LH 436 lowAddrLoad.vaddr := req.vaddr 437 lowAddrLoad.mask := 0x3.U << lowAddrLoad.vaddr(3, 0) 438 lowResultShift := BYTE0 439 lowResultWidth := BYTE2 440 441 highAddrLoad.uop.fuOpType := LD 442 highAddrLoad.vaddr := req.vaddr + 2.U 443 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 444 highResultShift := BYTE0 445 highResultWidth := BYTE6 446 } 447 448 is ("b111".U) { 449 lowAddrLoad.uop.fuOpType := LB 450 lowAddrLoad.vaddr := req.vaddr 451 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 452 lowResultShift := BYTE0 453 lowResultWidth := BYTE1 454 455 highAddrLoad.uop.fuOpType := LD 456 highAddrLoad.vaddr := req.vaddr + 1.U 457 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 458 highResultShift := BYTE0 459 highResultWidth := BYTE7 460 } 461 } 462 } 463 } 464 465 splitLoadReqs(0) := lowAddrLoad 466 splitLoadReqs(1) := highAddrLoad 467 } 468 } 469 470 io.splitLoadReq.valid := req_valid && (bufferState === s_req) 471 io.splitLoadReq.bits := splitLoadReqs(curPtr) 472 473 when (io.splitLoadResp.valid) { 474 splitLoadResp(curPtr) := io.splitLoadResp.bits 475 when (isMMIO) { 476 unSentLoads := 0.U 477 splitLoadResp(curPtr).uop.exceptionVec := 0.U.asTypeOf(ExceptionVec()) 478 // delegate to software 479 splitLoadResp(curPtr).uop.exceptionVec(loadAddrMisaligned) := true.B 480 } .elsewhen (hasException) { 481 unSentLoads := 0.U 482 } .elsewhen (!io.splitLoadResp.bits.rep_info.need_rep) { 483 unSentLoads := unSentLoads & ~UIntToOH(curPtr) 484 curPtr := curPtr + 1.U 485 } 486 } 487 488 val combinedData = RegInit(0.U(XLEN.W)) 489 490 when (bufferState === s_comb) { 491 when (!cross16BytesBoundary) { 492 val shiftData = LookupTree(aligned16BytesSel, List( 493 "b0000".U -> splitLoadResp(0).data(63, 0), 494 "b0001".U -> splitLoadResp(0).data(71, 8), 495 "b0010".U -> splitLoadResp(0).data(79, 16), 496 "b0011".U -> splitLoadResp(0).data(87, 24), 497 "b0100".U -> splitLoadResp(0).data(95, 32), 498 "b0101".U -> splitLoadResp(0).data(103, 40), 499 "b0110".U -> splitLoadResp(0).data(111, 48), 500 "b0111".U -> splitLoadResp(0).data(119, 56), 501 "b1000".U -> splitLoadResp(0).data(127, 64), 502 "b1001".U -> splitLoadResp(0).data(127, 72), 503 "b1010".U -> splitLoadResp(0).data(127, 80), 504 "b1011".U -> splitLoadResp(0).data(127, 88), 505 "b1100".U -> splitLoadResp(0).data(127, 96), 506 "b1101".U -> splitLoadResp(0).data(127, 104), 507 "b1110".U -> splitLoadResp(0).data(127, 112), 508 "b1111".U -> splitLoadResp(0).data(127, 120) 509 )) 510 val truncateData = LookupTree(req.uop.fuOpType(1, 0), List( 511 LB -> shiftData(7, 0), // lb 512 LH -> shiftData(15, 0), // lh 513 LW -> shiftData(31, 0), // lw 514 LD -> shiftData(63, 0) // ld 515 )) 516 combinedData := rdataHelper(req.uop, truncateData(XLEN - 1, 0)) 517 } .otherwise { 518 val lowAddrResult = getShiftAndTruncateData(lowResultShift, lowResultWidth, splitLoadResp(0).data) 519 .asTypeOf(Vec(XLEN / 8, UInt(8.W))) 520 val highAddrResult = getShiftAndTruncateData(highResultShift, highResultWidth, splitLoadResp(1).data) 521 .asTypeOf(Vec(XLEN / 8, UInt(8.W))) 522 val catResult = Wire(Vec(XLEN / 8, UInt(8.W))) 523 (0 until XLEN / 8) .map { 524 case i => { 525 when (i.U < lowResultWidth) { 526 catResult(i) := lowAddrResult(i) 527 } .otherwise { 528 catResult(i) := highAddrResult(i.U - lowResultWidth) 529 } 530 } 531 } 532 combinedData := rdataHelper(req.uop, (catResult.asUInt)(XLEN - 1, 0)) 533 } 534 } 535 536 io.writeBack.valid := req_valid && (bufferState === s_wb) 537 io.writeBack.bits.uop := req.uop 538 io.writeBack.bits.uop.exceptionVec := Mux( 539 globalMMIO || globalException, 540 splitLoadResp(curPtr).uop.exceptionVec, 541 0.U.asTypeOf(ExceptionVec()) // TODO: is this ok? 542 ) 543 io.writeBack.bits.uop.flushPipe := Mux(globalMMIO || globalException, false.B, true.B) 544 io.writeBack.bits.uop.replayInst := false.B 545 io.writeBack.bits.data := combinedData 546 io.writeBack.bits.debug.isMMIO := globalMMIO 547 io.writeBack.bits.debug.isPerfCnt := false.B 548 io.writeBack.bits.debug.paddr := req.paddr 549 io.writeBack.bits.debug.vaddr := req.vaddr 550 551 val flush = req_valid && req.uop.robIdx.needFlush(io.redirect) 552 553 when (flush && (bufferState =/= s_idle)) { 554 bufferState := s_idle 555 req_valid := false.B 556 curPtr := 0.U 557 unSentLoads := 0.U 558 globalException := false.B 559 globalMMIO := false.B 560 } 561 562 // NOTE: spectial case (unaligned load cross page, page fault happens in next page) 563 // if exception happens in the higher page address part, overwrite the loadExceptionBuffer vaddr 564 val overwriteExpBuf = GatedValidRegNext(req_valid && cross16BytesBoundary && globalException && (curPtr === 1.U)) 565 val overwriteAddr = GatedRegNext(splitLoadResp(curPtr).vaddr) 566 567 io.overwriteExpBuf.valid := overwriteExpBuf 568 io.overwriteExpBuf.vaddr := overwriteAddr 569 570 // when no exception or mmio, flush loadExceptionBuffer at s_wb 571 val flushLdExpBuff = GatedValidRegNext(req_valid && (bufferState === s_wb) && !(globalMMIO || globalException)) 572 io.flushLdExpBuff := flushLdExpBuff 573 574 XSPerfAccumulate("alloc", RegNext(!req_valid) && req_valid) 575 XSPerfAccumulate("flush", flush) 576 XSPerfAccumulate("flush_idle", flush && (bufferState === s_idle)) 577 XSPerfAccumulate("flush_non_idle", flush && (bufferState =/= s_idle)) 578}