1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.fu.FuConfig._ 26import xiangshan.backend.fu.fpu.FPU 27import xiangshan.backend.rob.RobLsqIO 28import xiangshan.cache._ 29import xiangshan.frontend.FtqPtr 30import xiangshan.ExceptionNO._ 31import xiangshan.cache.wpu.ReplayCarry 32import xiangshan.backend.rob.RobPtr 33import xiangshan.backend.Bundles.{MemExuOutput, DynInst} 34 35class LoadMisalignBuffer(implicit p: Parameters) extends XSModule 36 with HasCircularQueuePtrHelper 37 with HasLoadHelper 38{ 39 private val enqPortNum = LoadPipelineWidth 40 private val maxSplitNum = 2 41 42 require(maxSplitNum == 2) 43 44 private val LB = "b00".U(2.W) 45 private val LH = "b01".U(2.W) 46 private val LW = "b10".U(2.W) 47 private val LD = "b11".U(2.W) 48 49 // encode of how many bytes to shift or truncate 50 private val BYTE0 = "b000".U(3.W) 51 private val BYTE1 = "b001".U(3.W) 52 private val BYTE2 = "b010".U(3.W) 53 private val BYTE3 = "b011".U(3.W) 54 private val BYTE4 = "b100".U(3.W) 55 private val BYTE5 = "b101".U(3.W) 56 private val BYTE6 = "b110".U(3.W) 57 private val BYTE7 = "b111".U(3.W) 58 59 def getMask(sizeEncode: UInt) = LookupTree(sizeEncode, List( 60 LB -> 0x1.U, // lb 61 LH -> 0x3.U, // lh 62 LW -> 0xf.U, // lw 63 LD -> 0xff.U // ld 64 )) 65 66 def getShiftAndTruncateData(shiftEncode: UInt, truncateEncode: UInt, data: UInt) = { 67 val shiftData = LookupTree(shiftEncode, List( 68 BYTE0 -> data(63, 0), 69 BYTE1 -> data(63, 8), 70 BYTE2 -> data(63, 16), 71 BYTE3 -> data(63, 24), 72 BYTE4 -> data(63, 32), 73 BYTE5 -> data(63, 40), 74 BYTE6 -> data(63, 48), 75 BYTE7 -> data(63, 56) 76 )) 77 val truncateData = LookupTree(truncateEncode, List( 78 BYTE0 -> 0.U(XLEN.W), // can not truncate with 0 byte width 79 BYTE1 -> shiftData(7, 0), 80 BYTE2 -> shiftData(15, 0), 81 BYTE3 -> shiftData(23, 0), 82 BYTE4 -> shiftData(31, 0), 83 BYTE5 -> shiftData(39, 0), 84 BYTE6 -> shiftData(47, 0), 85 BYTE7 -> shiftData(55, 0) 86 )) 87 truncateData(XLEN - 1, 0) 88 } 89 90 def selectOldest[T <: LqWriteBundle](valid: Seq[Bool], bits: Seq[T]): (Seq[Bool], Seq[T]) = { 91 assert(valid.length == bits.length) 92 if (valid.length == 0 || valid.length == 1) { 93 (valid, bits) 94 } else if (valid.length == 2) { 95 val res = Seq.fill(2)(Wire(ValidIO(chiselTypeOf(bits(0))))) 96 for (i <- res.indices) { 97 res(i).valid := valid(i) 98 res(i).bits := bits(i) 99 } 100 val oldest = Mux(valid(0) && valid(1), 101 Mux(isAfter(bits(0).uop.robIdx, bits(1).uop.robIdx) || 102 (isNotBefore(bits(0).uop.robIdx, bits(1).uop.robIdx) && bits(0).uop.uopIdx > bits(1).uop.uopIdx), res(1), res(0)), 103 Mux(valid(0) && !valid(1), res(0), res(1))) 104 (Seq(oldest.valid), Seq(oldest.bits)) 105 } else { 106 val left = selectOldest(valid.take(valid.length / 2), bits.take(bits.length / 2)) 107 val right = selectOldest(valid.takeRight(valid.length - (valid.length / 2)), bits.takeRight(bits.length - (bits.length / 2))) 108 selectOldest(left._1 ++ right._1, left._2 ++ right._2) 109 } 110 } 111 112 val io = IO(new Bundle() { 113 val redirect = Flipped(Valid(new Redirect)) 114 val req = Vec(enqPortNum, Flipped(Valid(new LqWriteBundle))) 115 val rob = Flipped(new RobLsqIO) 116 val splitLoadReq = Decoupled(new LsPipelineBundle) 117 val splitLoadResp = Flipped(Valid(new LqWriteBundle)) 118 val writeBack = Decoupled(new MemExuOutput) 119 val overwriteExpBuf = Output(new XSBundle { 120 val valid = Bool() 121 val vaddr = UInt(VAddrBits.W) 122 val gpaddr = UInt(GPAddrBits.W) 123 }) 124 val flushLdExpBuff = Output(Bool()) 125 }) 126 127 io.rob.mmio := 0.U.asTypeOf(Vec(LoadPipelineWidth, Bool())) 128 io.rob.uop := 0.U.asTypeOf(Vec(LoadPipelineWidth, new DynInst)) 129 130 val req_valid = RegInit(false.B) 131 val req = Reg(new LqWriteBundle) 132 133 // enqueue 134 // s1: 135 val s1_req = VecInit(io.req.map(_.bits)) 136 val s1_valid = VecInit(io.req.map(x => x.valid)) 137 138 // s2: delay 1 cycle 139 val s2_req = RegNext(s1_req) 140 val s2_valid = (0 until enqPortNum).map(i => 141 RegNext(s1_valid(i)) && 142 !s2_req(i).uop.robIdx.needFlush(RegNext(io.redirect)) && 143 !s2_req(i).uop.robIdx.needFlush(io.redirect) 144 ) 145 val s2_miss_aligned = s2_req.map(x => 146 x.uop.exceptionVec(loadAddrMisaligned) && !x.uop.exceptionVec(breakPoint) && !TriggerAction.isDmode(x.uop.trigger) 147 ) 148 149 val s2_enqueue = Wire(Vec(enqPortNum, Bool())) 150 for (w <- 0 until enqPortNum) { 151 s2_enqueue(w) := s2_valid(w) && s2_miss_aligned(w) 152 } 153 154 when (req_valid && req.uop.robIdx.needFlush(io.redirect)) { 155 req_valid := s2_enqueue.asUInt.orR 156 } .elsewhen (s2_enqueue.asUInt.orR) { 157 req_valid := req_valid || true.B 158 } 159 160 val reqSel = selectOldest(s2_enqueue, s2_req) 161 162 when (req_valid) { 163 req := Mux( 164 reqSel._1(0) && (isAfter(req.uop.robIdx, reqSel._2(0).uop.robIdx) || (isNotBefore(req.uop.robIdx, reqSel._2(0).uop.robIdx) && req.uop.uopIdx > reqSel._2(0).uop.uopIdx)), 165 reqSel._2(0), 166 req) 167 } .elsewhen (s2_enqueue.asUInt.orR) { 168 req := reqSel._2(0) 169 } 170 171 val robMatch = req_valid && io.rob.pendingld && (io.rob.pendingPtr === req.uop.robIdx) 172 173 // buffer control: 174 // - split miss-aligned load into aligned loads 175 // - send split load to ldu and get result from ldu 176 // - merge them and write back to rob 177 val s_idle :: s_split :: s_req :: s_resp :: s_comb :: s_wb :: s_wait :: Nil = Enum(7) 178 val bufferState = RegInit(s_idle) 179 val splitLoadReqs = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new LsPipelineBundle)))) 180 val splitLoadResp = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new LqWriteBundle)))) 181 val unSentLoads = RegInit(0.U(maxSplitNum.W)) 182 val curPtr = RegInit(0.U(log2Ceil(maxSplitNum).W)) 183 184 // if there is exception or mmio in split load 185 val globalException = RegInit(false.B) 186 val globalMMIO = RegInit(false.B) 187 188 val hasException = ExceptionNO.selectByFu(io.splitLoadResp.bits.uop.exceptionVec, LduCfg).asUInt.orR 189 val isMMIO = io.splitLoadResp.bits.mmio 190 191 switch(bufferState) { 192 is (s_idle) { 193 when (robMatch) { 194 bufferState := s_split 195 } 196 } 197 198 is (s_split) { 199 bufferState := s_req 200 } 201 202 is (s_req) { 203 when (io.splitLoadReq.fire) { 204 bufferState := s_resp 205 } 206 } 207 208 is (s_resp) { 209 when (io.splitLoadResp.valid) { 210 val clearOh = UIntToOH(curPtr) 211 when (hasException || isMMIO) { 212 // commit directly when exception ocurs 213 // if any split load reaches mmio space, delegate to software loadAddrMisaligned exception 214 bufferState := s_wb 215 globalException := hasException 216 globalMMIO := isMMIO 217 } .elsewhen(io.splitLoadResp.bits.rep_info.need_rep || (unSentLoads & ~clearOh).orR) { 218 // need replay or still has unsent requests 219 bufferState := s_req 220 } .otherwise { 221 // merge the split load results 222 bufferState := s_comb 223 } 224 } 225 } 226 227 is (s_comb) { 228 bufferState := s_wb 229 } 230 231 is (s_wb) { 232 when(io.writeBack.fire) { 233 bufferState := s_wait 234 } 235 } 236 237 is (s_wait) { 238 when(io.rob.lcommit =/= 0.U || req.uop.robIdx.needFlush(io.redirect)) { 239 // rob commits the unaligned load or handled the exception, reset all state 240 bufferState := s_idle 241 req_valid := false.B 242 curPtr := 0.U 243 unSentLoads := 0.U 244 globalException := false.B 245 globalMMIO := false.B 246 } 247 } 248 } 249 250 val highAddress = LookupTree(req.uop.fuOpType(1, 0), List( 251 LB -> 0.U, 252 LH -> 1.U, 253 LW -> 3.U, 254 LD -> 7.U 255 )) + req.vaddr(4, 0) 256 // to see if (vaddr + opSize - 1) and vaddr are in the same 16 bytes region 257 val cross16BytesBoundary = req_valid && (highAddress(4) =/= req.vaddr(4)) 258 val aligned16BytesAddr = (req.vaddr >> 4) << 4// req.vaddr & ~("b1111".U) 259 val aligned16BytesSel = req.vaddr(3, 0) 260 261 // meta of 128 bit load 262 val new128Load = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 263 // meta of split loads 264 val lowAddrLoad = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 265 val highAddrLoad = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 266 val lowResultShift = RegInit(0.U(3.W)) // how many bytes should we shift right when got result 267 val lowResultWidth = RegInit(0.U(3.W)) // how many bytes should we take from result 268 val highResultShift = RegInit(0.U(3.W)) 269 val highResultWidth = RegInit(0.U(3.W)) 270 271 when (bufferState === s_split) { 272 when (!cross16BytesBoundary) { 273 // change this unaligned load into a 128 bits load 274 unSentLoads := 1.U 275 curPtr := 0.U 276 new128Load.vaddr := aligned16BytesAddr 277 // new128Load.mask := (getMask(req.uop.fuOpType(1, 0)) << aligned16BytesSel).asUInt 278 new128Load.mask := 0xffff.U 279 new128Load.uop := req.uop 280 new128Load.uop.exceptionVec(loadAddrMisaligned) := false.B 281 new128Load.is128bit := true.B 282 splitLoadReqs(0) := new128Load 283 } .otherwise { 284 // split this unaligned load into `maxSplitNum` aligned loads 285 unSentLoads := Fill(maxSplitNum, 1.U(1.W)) 286 curPtr := 0.U 287 lowAddrLoad.uop := req.uop 288 lowAddrLoad.uop.exceptionVec(loadAddrMisaligned) := false.B 289 highAddrLoad.uop := req.uop 290 highAddrLoad.uop.exceptionVec(loadAddrMisaligned) := false.B 291 292 switch (req.uop.fuOpType(1, 0)) { 293 is (LB) { 294 assert(false.B, "lb should not trigger miss align") 295 } 296 297 is (LH) { 298 lowAddrLoad.uop.fuOpType := LB 299 lowAddrLoad.vaddr := req.vaddr 300 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 301 lowResultShift := BYTE0 302 lowResultWidth := BYTE1 303 304 highAddrLoad.uop.fuOpType := LB 305 highAddrLoad.vaddr := req.vaddr + 1.U 306 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 307 highResultShift := BYTE0 308 highResultWidth := BYTE1 309 } 310 311 is (LW) { 312 switch (req.vaddr(1, 0)) { 313 is ("b00".U) { 314 assert(false.B, "should not trigger miss align") 315 } 316 317 is ("b01".U) { 318 lowAddrLoad.uop.fuOpType := LW 319 lowAddrLoad.vaddr := req.vaddr - 1.U 320 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 321 lowResultShift := BYTE1 322 lowResultWidth := BYTE3 323 324 highAddrLoad.uop.fuOpType := LB 325 highAddrLoad.vaddr := req.vaddr + 3.U 326 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 327 highResultShift := BYTE0 328 highResultWidth := BYTE1 329 } 330 331 is ("b10".U) { 332 lowAddrLoad.uop.fuOpType := LH 333 lowAddrLoad.vaddr := req.vaddr 334 lowAddrLoad.mask := 0x3.U << lowAddrLoad.vaddr(3, 0) 335 lowResultShift := BYTE0 336 lowResultWidth := BYTE2 337 338 highAddrLoad.uop.fuOpType := LH 339 highAddrLoad.vaddr := req.vaddr + 2.U 340 highAddrLoad.mask := 0x3.U << highAddrLoad.vaddr(3, 0) 341 highResultShift := BYTE0 342 highResultWidth := BYTE2 343 } 344 345 is ("b11".U) { 346 lowAddrLoad.uop.fuOpType := LB 347 lowAddrLoad.vaddr := req.vaddr 348 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 349 lowResultShift := BYTE0 350 lowResultWidth := BYTE1 351 352 highAddrLoad.uop.fuOpType := LW 353 highAddrLoad.vaddr := req.vaddr + 1.U 354 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 355 highResultShift := BYTE0 356 highResultWidth := BYTE3 357 } 358 } 359 } 360 361 is (LD) { 362 switch (req.vaddr(2, 0)) { 363 is ("b000".U) { 364 assert(false.B, "should not trigger miss align") 365 } 366 367 is ("b001".U) { 368 lowAddrLoad.uop.fuOpType := LD 369 lowAddrLoad.vaddr := req.vaddr - 1.U 370 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 371 lowResultShift := BYTE1 372 lowResultWidth := BYTE7 373 374 highAddrLoad.uop.fuOpType := LB 375 highAddrLoad.vaddr := req.vaddr + 7.U 376 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 377 highResultShift := BYTE0 378 highResultWidth := BYTE1 379 } 380 381 is ("b010".U) { 382 lowAddrLoad.uop.fuOpType := LD 383 lowAddrLoad.vaddr := req.vaddr - 2.U 384 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 385 lowResultShift := BYTE2 386 lowResultWidth := BYTE6 387 388 highAddrLoad.uop.fuOpType := LH 389 highAddrLoad.vaddr := req.vaddr + 6.U 390 highAddrLoad.mask := 0x3.U << highAddrLoad.vaddr(3, 0) 391 highResultShift := BYTE0 392 highResultWidth := BYTE2 393 } 394 395 is ("b011".U) { 396 lowAddrLoad.uop.fuOpType := LD 397 lowAddrLoad.vaddr := req.vaddr - 3.U 398 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 399 lowResultShift := BYTE3 400 lowResultWidth := BYTE5 401 402 highAddrLoad.uop.fuOpType := LW 403 highAddrLoad.vaddr := req.vaddr + 5.U 404 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 405 highResultShift := BYTE0 406 highResultWidth := BYTE3 407 } 408 409 is ("b100".U) { 410 lowAddrLoad.uop.fuOpType := LW 411 lowAddrLoad.vaddr := req.vaddr 412 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 413 lowResultShift := BYTE0 414 lowResultWidth := BYTE4 415 416 highAddrLoad.uop.fuOpType := LW 417 highAddrLoad.vaddr := req.vaddr + 4.U 418 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 419 highResultShift := BYTE0 420 highResultWidth := BYTE4 421 } 422 423 is ("b101".U) { 424 lowAddrLoad.uop.fuOpType := LW 425 lowAddrLoad.vaddr := req.vaddr - 1.U 426 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 427 lowResultShift := BYTE1 428 lowResultWidth := BYTE3 429 430 highAddrLoad.uop.fuOpType := LD 431 highAddrLoad.vaddr := req.vaddr + 3.U 432 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 433 highResultShift := BYTE0 434 highResultWidth := BYTE5 435 } 436 437 is ("b110".U) { 438 lowAddrLoad.uop.fuOpType := LH 439 lowAddrLoad.vaddr := req.vaddr 440 lowAddrLoad.mask := 0x3.U << lowAddrLoad.vaddr(3, 0) 441 lowResultShift := BYTE0 442 lowResultWidth := BYTE2 443 444 highAddrLoad.uop.fuOpType := LD 445 highAddrLoad.vaddr := req.vaddr + 2.U 446 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 447 highResultShift := BYTE0 448 highResultWidth := BYTE6 449 } 450 451 is ("b111".U) { 452 lowAddrLoad.uop.fuOpType := LB 453 lowAddrLoad.vaddr := req.vaddr 454 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 455 lowResultShift := BYTE0 456 lowResultWidth := BYTE1 457 458 highAddrLoad.uop.fuOpType := LD 459 highAddrLoad.vaddr := req.vaddr + 1.U 460 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 461 highResultShift := BYTE0 462 highResultWidth := BYTE7 463 } 464 } 465 } 466 } 467 468 splitLoadReqs(0) := lowAddrLoad 469 splitLoadReqs(1) := highAddrLoad 470 } 471 } 472 473 io.splitLoadReq.valid := req_valid && (bufferState === s_req) 474 io.splitLoadReq.bits := splitLoadReqs(curPtr) 475 476 when (io.splitLoadResp.valid) { 477 splitLoadResp(curPtr) := io.splitLoadResp.bits 478 when (isMMIO) { 479 unSentLoads := 0.U 480 splitLoadResp(curPtr).uop.exceptionVec := 0.U.asTypeOf(ExceptionVec()) 481 // delegate to software 482 splitLoadResp(curPtr).uop.exceptionVec(loadAddrMisaligned) := true.B 483 } .elsewhen (hasException) { 484 unSentLoads := 0.U 485 } .elsewhen (!io.splitLoadResp.bits.rep_info.need_rep) { 486 unSentLoads := unSentLoads & ~UIntToOH(curPtr) 487 curPtr := curPtr + 1.U 488 } 489 } 490 491 val combinedData = RegInit(0.U(XLEN.W)) 492 493 when (bufferState === s_comb) { 494 when (!cross16BytesBoundary) { 495 val shiftData = LookupTree(aligned16BytesSel, List( 496 "b0000".U -> splitLoadResp(0).data(63, 0), 497 "b0001".U -> splitLoadResp(0).data(71, 8), 498 "b0010".U -> splitLoadResp(0).data(79, 16), 499 "b0011".U -> splitLoadResp(0).data(87, 24), 500 "b0100".U -> splitLoadResp(0).data(95, 32), 501 "b0101".U -> splitLoadResp(0).data(103, 40), 502 "b0110".U -> splitLoadResp(0).data(111, 48), 503 "b0111".U -> splitLoadResp(0).data(119, 56), 504 "b1000".U -> splitLoadResp(0).data(127, 64), 505 "b1001".U -> splitLoadResp(0).data(127, 72), 506 "b1010".U -> splitLoadResp(0).data(127, 80), 507 "b1011".U -> splitLoadResp(0).data(127, 88), 508 "b1100".U -> splitLoadResp(0).data(127, 96), 509 "b1101".U -> splitLoadResp(0).data(127, 104), 510 "b1110".U -> splitLoadResp(0).data(127, 112), 511 "b1111".U -> splitLoadResp(0).data(127, 120) 512 )) 513 val truncateData = LookupTree(req.uop.fuOpType(1, 0), List( 514 LB -> shiftData(7, 0), // lb 515 LH -> shiftData(15, 0), // lh 516 LW -> shiftData(31, 0), // lw 517 LD -> shiftData(63, 0) // ld 518 )) 519 combinedData := rdataHelper(req.uop, truncateData(XLEN - 1, 0)) 520 } .otherwise { 521 val lowAddrResult = getShiftAndTruncateData(lowResultShift, lowResultWidth, splitLoadResp(0).data) 522 .asTypeOf(Vec(XLEN / 8, UInt(8.W))) 523 val highAddrResult = getShiftAndTruncateData(highResultShift, highResultWidth, splitLoadResp(1).data) 524 .asTypeOf(Vec(XLEN / 8, UInt(8.W))) 525 val catResult = Wire(Vec(XLEN / 8, UInt(8.W))) 526 (0 until XLEN / 8) .map { 527 case i => { 528 when (i.U < lowResultWidth) { 529 catResult(i) := lowAddrResult(i) 530 } .otherwise { 531 catResult(i) := highAddrResult(i.U - lowResultWidth) 532 } 533 } 534 } 535 combinedData := rdataHelper(req.uop, (catResult.asUInt)(XLEN - 1, 0)) 536 } 537 } 538 539 io.writeBack.valid := req_valid && (bufferState === s_wb) 540 io.writeBack.bits.uop := req.uop 541 io.writeBack.bits.uop.exceptionVec := Mux( 542 globalMMIO || globalException, 543 splitLoadResp(curPtr).uop.exceptionVec, 544 0.U.asTypeOf(ExceptionVec()) // TODO: is this ok? 545 ) 546 io.writeBack.bits.uop.flushPipe := Mux(globalMMIO || globalException, false.B, true.B) 547 io.writeBack.bits.uop.replayInst := false.B 548 io.writeBack.bits.data := combinedData 549 io.writeBack.bits.debug.isMMIO := globalMMIO 550 io.writeBack.bits.debug.isPerfCnt := false.B 551 io.writeBack.bits.debug.paddr := req.paddr 552 io.writeBack.bits.debug.vaddr := req.vaddr 553 554 val flush = req_valid && req.uop.robIdx.needFlush(io.redirect) 555 556 when (flush && (bufferState =/= s_idle)) { 557 bufferState := s_idle 558 req_valid := false.B 559 curPtr := 0.U 560 unSentLoads := 0.U 561 globalException := false.B 562 globalMMIO := false.B 563 } 564 565 // NOTE: spectial case (unaligned load cross page, page fault happens in next page) 566 // if exception happens in the higher page address part, overwrite the loadExceptionBuffer vaddr 567 val overwriteExpBuf = GatedValidRegNext(req_valid && cross16BytesBoundary && globalException && (curPtr === 1.U)) 568 val overwriteVaddr = GatedRegNext(splitLoadResp(curPtr).vaddr) 569 val overwriteGpaddr = GatedRegNext(splitLoadResp(curPtr).gpaddr) 570 571 io.overwriteExpBuf.valid := overwriteExpBuf 572 io.overwriteExpBuf.vaddr := overwriteVaddr 573 io.overwriteExpBuf.gpaddr := overwriteGpaddr 574 575 // when no exception or mmio, flush loadExceptionBuffer at s_wb 576 val flushLdExpBuff = GatedValidRegNext(req_valid && (bufferState === s_wb) && !(globalMMIO || globalException)) 577 io.flushLdExpBuff := flushLdExpBuff 578 579 XSPerfAccumulate("alloc", RegNext(!req_valid) && req_valid) 580 XSPerfAccumulate("flush", flush) 581 XSPerfAccumulate("flush_idle", flush && (bufferState === s_idle)) 582 XSPerfAccumulate("flush_non_idle", flush && (bufferState =/= s_idle)) 583}