109c6f1ddSLingrui98/*************************************************************************************** 209c6f1ddSLingrui98* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 309c6f1ddSLingrui98* Copyright (c) 2020-2021 Peng Cheng Laboratory 409c6f1ddSLingrui98* 509c6f1ddSLingrui98* XiangShan is licensed under Mulan PSL v2. 609c6f1ddSLingrui98* You can use this software according to the terms and conditions of the Mulan PSL v2. 709c6f1ddSLingrui98* You may obtain a copy of Mulan PSL v2 at: 809c6f1ddSLingrui98* http://license.coscl.org.cn/MulanPSL2 909c6f1ddSLingrui98* 1009c6f1ddSLingrui98* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 1109c6f1ddSLingrui98* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 1209c6f1ddSLingrui98* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 1309c6f1ddSLingrui98* 1409c6f1ddSLingrui98* See the Mulan PSL v2 for more details. 1509c6f1ddSLingrui98***************************************************************************************/ 1609c6f1ddSLingrui98 1709c6f1ddSLingrui98package xiangshan.frontend 1809c6f1ddSLingrui98 1909c6f1ddSLingrui98import chipsalliance.rocketchip.config.Parameters 2009c6f1ddSLingrui98import chisel3._ 2109c6f1ddSLingrui98import chisel3.util._ 22bf358e08SLingrui98import chisel3.experimental.chiselName 2309c6f1ddSLingrui98import xiangshan._ 2409c6f1ddSLingrui98import utils._ 25*3c02ee8fSwakafaimport utility._ 2609c6f1ddSLingrui98 27bf358e08SLingrui98@chiselName 281ca0e4f3SYinan Xuclass Composer(implicit p: Parameters) extends BasePredictor with HasBPUConst with HasPerfEvents { 29bf358e08SLingrui98 val (components, resp) = getBPDComponents(io.in.bits.resp_in(0), p) 30c2d1ec7dSLingrui98 io.out := resp 31b60e4b0bSLingrui98 // shorter path for s1 pred 32b60e4b0bSLingrui98 val all_fast_pred = components.filter(_.is_fast_pred) 33b60e4b0bSLingrui98 require(all_fast_pred.length <= 1) 34b60e4b0bSLingrui98 if (all_fast_pred.length == 1) { 35b60e4b0bSLingrui98 val fast_pred = all_fast_pred(0) 36b60e4b0bSLingrui98 println("[composer] bypassing output of fast pred: " + fast_pred.name) 37b60e4b0bSLingrui98 io.out.s1 := fast_pred.io.out.s1 38b60e4b0bSLingrui98 } 3909c6f1ddSLingrui98 4009c6f1ddSLingrui98 var metas = 0.U(1.W) 4109c6f1ddSLingrui98 var meta_sz = 0 4209c6f1ddSLingrui98 for (c <- components) { 43c4b44470SGuokai Chen c.io.reset_vector := io.reset_vector 4409c6f1ddSLingrui98 c.io.in.valid := io.in.valid 4509c6f1ddSLingrui98 c.io.in.bits.s0_pc := io.in.bits.s0_pc 46dd6c0695SLingrui98 c.io.in.bits.folded_hist := io.in.bits.folded_hist 4786d9c530SLingrui98 c.io.in.bits.ghist := io.in.bits.ghist 4809c6f1ddSLingrui98 4909c6f1ddSLingrui98 c.io.s0_fire := io.s0_fire 5009c6f1ddSLingrui98 c.io.s1_fire := io.s1_fire 5109c6f1ddSLingrui98 c.io.s2_fire := io.s2_fire 52ba246ba1SLingrui98 c.io.s3_fire := io.s3_fire 5309c6f1ddSLingrui98 5485670bacSLingrui98 c.io.s2_redirect := io.s2_redirect 5585670bacSLingrui98 c.io.s3_redirect := io.s3_redirect 5685670bacSLingrui98 5709c6f1ddSLingrui98 c.io.redirect := io.redirect 586ee06c7aSSteve Gou c.io.ctrl := DelayN(io.ctrl, 1) 5909c6f1ddSLingrui98 6009c6f1ddSLingrui98 if (c.meta_size > 0) { 613e52bed1SLingrui98 metas = (metas << c.meta_size) | c.io.out.last_stage_meta(c.meta_size-1,0) 6209c6f1ddSLingrui98 } 6309c6f1ddSLingrui98 meta_sz = meta_sz + c.meta_size 6409c6f1ddSLingrui98 } 651bc6e9c8SLingrui98 println(s"total meta size: $meta_sz\n\n") 6609c6f1ddSLingrui98 67b60e4b0bSLingrui98 6809c6f1ddSLingrui98 io.in.ready := components.map(_.io.s1_ready).reduce(_ && _) 6909c6f1ddSLingrui98 7009c6f1ddSLingrui98 io.s1_ready := components.map(_.io.s1_ready).reduce(_ && _) 7109c6f1ddSLingrui98 io.s2_ready := components.map(_.io.s2_ready).reduce(_ && _) 7209c6f1ddSLingrui98 7309c6f1ddSLingrui98 require(meta_sz < MaxMetaLength) 743e52bed1SLingrui98 io.out.last_stage_meta := metas 7509c6f1ddSLingrui98 7609c6f1ddSLingrui98 var update_meta = io.update.bits.meta 7709c6f1ddSLingrui98 for (c <- components.reverse) { 7809c6f1ddSLingrui98 c.io.update := io.update 7909c6f1ddSLingrui98 c.io.update.bits.meta := update_meta 8009c6f1ddSLingrui98 update_meta = update_meta >> c.meta_size 8109c6f1ddSLingrui98 } 8209c6f1ddSLingrui98 8309c6f1ddSLingrui98 def extractMeta(meta: UInt, idx: Int): UInt = { 8409c6f1ddSLingrui98 var update_meta = meta 8509c6f1ddSLingrui98 var metas: Seq[UInt] = Nil 8609c6f1ddSLingrui98 for (c <- components.reverse) { 8709c6f1ddSLingrui98 metas = metas :+ update_meta 8809c6f1ddSLingrui98 update_meta = update_meta >> c.meta_size 8909c6f1ddSLingrui98 } 9009c6f1ddSLingrui98 metas(idx) 9109c6f1ddSLingrui98 } 92cd365d4cSrvcoresjw 93dd6c0695SLingrui98 override def getFoldedHistoryInfo = Some(components.map(_.getFoldedHistoryInfo.getOrElse(Set())).reduce(_++_)) 94dd6c0695SLingrui98 954813e060SLingrui98 override val perfEvents = components.map(_.getPerfEvents).reduce(_++_) 961ca0e4f3SYinan Xu generatePerfEvent() 9709c6f1ddSLingrui98} 98