1package xiangshan.frontend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.ALUOpType 8import xiangshan.backend.JumpOpType 9import chisel3.experimental.chiselName 10 11trait HasBPUParameter extends HasXSParameter { 12 val BPUDebug = true 13 val EnableCFICommitLog = true 14 val EnbaleCFIPredLog = true 15 val EnableBPUTimeRecord = EnableCFICommitLog || EnbaleCFIPredLog 16} 17 18class TableAddr(val idxBits: Int, val banks: Int) extends XSBundle with HasIFUConst { 19 def tagBits = VAddrBits - idxBits - instOffsetBits 20 21 val tag = UInt(tagBits.W) 22 val idx = UInt(idxBits.W) 23 val offset = UInt(instOffsetBits.W) 24 25 def fromUInt(x: UInt) = x.asTypeOf(UInt(VAddrBits.W)).asTypeOf(this) 26 def getTag(x: UInt) = fromUInt(x).tag 27 def getIdx(x: UInt) = fromUInt(x).idx 28 def getBank(x: UInt) = getIdx(x)(log2Up(banks) - 1, 0) 29 def getBankIdx(x: UInt) = getIdx(x)(idxBits - 1, log2Up(banks)) 30} 31 32class PredictorResponse extends XSBundle { 33 class UbtbResp extends XSBundle { 34 // the valid bits indicates whether a target is hit 35 val targets = Vec(PredictWidth, UInt(VAddrBits.W)) 36 val hits = Vec(PredictWidth, Bool()) 37 val takens = Vec(PredictWidth, Bool()) 38 val brMask = Vec(PredictWidth, Bool()) 39 val is_RVC = Vec(PredictWidth, Bool()) 40 } 41 class BtbResp extends XSBundle { 42 // the valid bits indicates whether a target is hit 43 val targets = Vec(PredictWidth, UInt(VAddrBits.W)) 44 val hits = Vec(PredictWidth, Bool()) 45 val types = Vec(PredictWidth, UInt(2.W)) 46 val isRVC = Vec(PredictWidth, Bool()) 47 } 48 class BimResp extends XSBundle { 49 val ctrs = Vec(PredictWidth, UInt(2.W)) 50 } 51 class TageResp extends XSBundle { 52 // the valid bits indicates whether a prediction is hit 53 val takens = Vec(PredictWidth, Bool()) 54 val hits = Vec(PredictWidth, Bool()) 55 } 56 class LoopResp extends XSBundle { 57 val exit = Vec(PredictWidth, Bool()) 58 } 59 60 val ubtb = new UbtbResp 61 val btb = new BtbResp 62 val bim = new BimResp 63 val tage = new TageResp 64 val loop = new LoopResp 65} 66 67trait PredictorUtils { 68 // circular shifting 69 def circularShiftLeft(source: UInt, len: Int, shamt: UInt): UInt = { 70 val res = Wire(UInt(len.W)) 71 val higher = source << shamt 72 val lower = source >> (len.U - shamt) 73 res := higher | lower 74 res 75 } 76 77 def circularShiftRight(source: UInt, len: Int, shamt: UInt): UInt = { 78 val res = Wire(UInt(len.W)) 79 val higher = source << (len.U - shamt) 80 val lower = source >> shamt 81 res := higher | lower 82 res 83 } 84 85 // To be verified 86 def satUpdate(old: UInt, len: Int, taken: Bool): UInt = { 87 val oldSatTaken = old === ((1 << len)-1).U 88 val oldSatNotTaken = old === 0.U 89 Mux(oldSatTaken && taken, ((1 << len)-1).U, 90 Mux(oldSatNotTaken && !taken, 0.U, 91 Mux(taken, old + 1.U, old - 1.U))) 92 } 93 94 def signedSatUpdate(old: SInt, len: Int, taken: Bool): SInt = { 95 val oldSatTaken = old === ((1 << (len-1))-1).S 96 val oldSatNotTaken = old === (-(1 << (len-1))).S 97 Mux(oldSatTaken && taken, ((1 << (len-1))-1).S, 98 Mux(oldSatNotTaken && !taken, (-(1 << (len-1))).S, 99 Mux(taken, old + 1.S, old - 1.S))) 100 } 101} 102abstract class BasePredictor extends XSModule 103 with HasBPUParameter with HasIFUConst with PredictorUtils { 104 val metaLen = 0 105 106 // An implementation MUST extend the IO bundle with a response 107 // and the special input from other predictors, as well as 108 // the metas to store in BRQ 109 abstract class Resp extends XSBundle {} 110 abstract class FromOthers extends XSBundle {} 111 abstract class Meta extends XSBundle {} 112 113 class DefaultBasePredictorIO extends XSBundle { 114 val flush = Input(Bool()) 115 val pc = Flipped(ValidIO(UInt(VAddrBits.W))) 116 val hist = Input(UInt(HistoryLength.W)) 117 val inMask = Input(UInt(PredictWidth.W)) 118 val update = Flipped(ValidIO(new CfiUpdateInfo)) 119 val outFire = Input(Bool()) 120 } 121 122 val io = new DefaultBasePredictorIO 123 124 val debug = false 125} 126 127class BPUStageIO extends XSBundle { 128 val pc = UInt(VAddrBits.W) 129 val mask = UInt(PredictWidth.W) 130 val resp = new PredictorResponse 131 // val target = UInt(VAddrBits.W) 132 val brInfo = Vec(PredictWidth, new BpuMeta) 133 // val saveHalfRVI = Bool() 134} 135 136 137abstract class BPUStage extends XSModule with HasBPUParameter with HasIFUConst { 138 class DefaultIO extends XSBundle { 139 val flush = Input(Bool()) 140 val in = Input(new BPUStageIO) 141 val inFire = Input(Bool()) 142 val pred = Output(new BranchPrediction) // to ifu 143 val out = Output(new BPUStageIO) // to the next stage 144 val outFire = Input(Bool()) 145 146 val debug_hist = Input(UInt((if (BPUDebug) (HistoryLength) else 0).W)) 147 // val debug_histPtr = Input(UInt((if (BPUDebug) (ExtHistoryLength) else 0).W)) 148 } 149 val io = IO(new DefaultIO) 150 151 def npc(pc: UInt, instCount: UInt) = pc + (instCount << instOffsetBits.U) 152 153 val inLatch = RegEnable(io.in, io.inFire) 154 155 // Each stage has its own logic to decide 156 // takens, notTakens and target 157 158 val takens = Wire(Vec(PredictWidth, Bool())) 159 // val notTakens = Wire(Vec(PredictWidth, Bool())) 160 val brMask = Wire(Vec(PredictWidth, Bool())) 161 val jalMask = Wire(Vec(PredictWidth, Bool())) 162 163 val targets = Wire(Vec(PredictWidth, UInt(VAddrBits.W))) 164 165 val firstBankHasHalfRVI = Wire(Bool()) 166 val lastBankHasHalfRVI = Wire(Bool()) 167 val lastBankHasInst = WireInit(inLatch.mask(PredictWidth-1, bankWidth).orR) 168 169 io.pred <> DontCare 170 io.pred.takens := takens.asUInt 171 io.pred.brMask := brMask.asUInt 172 io.pred.jalMask := jalMask.asUInt 173 io.pred.targets := targets 174 io.pred.firstBankHasHalfRVI := firstBankHasHalfRVI 175 io.pred.lastBankHasHalfRVI := lastBankHasHalfRVI 176 177 io.out <> DontCare 178 io.out.pc := inLatch.pc 179 io.out.mask := inLatch.mask 180 io.out.resp <> inLatch.resp 181 io.out.brInfo := inLatch.brInfo 182 (0 until PredictWidth).map(i => io.out.brInfo(i).sawNotTakenBranch := io.pred.sawNotTakenBr(i)) 183 184 if (BPUDebug) { 185 val jmpIdx = io.pred.jmpIdx 186 val taken = io.pred.taken 187 val target = Mux(taken, io.pred.targets(jmpIdx), snpc(inLatch.pc)) 188 XSDebug("in(%d): pc=%x, mask=%b\n", io.inFire, io.in.pc, io.in.mask) 189 XSDebug("inLatch: pc=%x, mask=%b\n", inLatch.pc, inLatch.mask) 190 XSDebug("out(%d): pc=%x, mask=%b, taken=%d, jmpIdx=%d, target=%x, firstHasHalfRVI=%d, lastHasHalfRVI=%d\n", 191 io.outFire, io.out.pc, io.out.mask, taken, jmpIdx, target, firstBankHasHalfRVI, lastBankHasHalfRVI) 192 XSDebug("flush=%d\n", io.flush) 193 val p = io.pred 194 } 195} 196 197@chiselName 198class BPUStage1 extends BPUStage { 199 200 // ubtb is accessed with inLatch pc in s1, 201 // so we use io.in instead of inLatch 202 val ubtbResp = io.in.resp.ubtb 203 // the read operation is already masked, so we do not need to mask here 204 takens := VecInit((0 until PredictWidth).map(i => ubtbResp.takens(i))) 205 // notTakens := VecInit((0 until PredictWidth).map(i => ubtbResp.hits(i) && !ubtbResp.takens(i) && ubtbResp.brMask(i))) 206 brMask := ubtbResp.brMask 207 jalMask := DontCare 208 targets := ubtbResp.targets 209 210 firstBankHasHalfRVI := Mux(lastBankHasInst, false.B, ubtbResp.hits(bankWidth-1) && !ubtbResp.is_RVC(bankWidth-1)) && HasCExtension.B 211 lastBankHasHalfRVI := ubtbResp.hits(PredictWidth-1) && !ubtbResp.is_RVC(PredictWidth-1) && HasCExtension.B 212 213 // resp and brInfo are from the components, 214 // so it does not need to be latched 215 io.out.resp <> io.in.resp 216 io.out.brInfo := io.in.brInfo 217 218 if (BPUDebug) { 219 XSDebug(io.outFire, "outPred using ubtb resp: hits:%b, takens:%b, notTakens:%b, isRVC:%b\n", 220 ubtbResp.hits.asUInt, ubtbResp.takens.asUInt, ~ubtbResp.takens.asUInt & brMask.asUInt, ubtbResp.is_RVC.asUInt) 221 } 222 if (EnableBPUTimeRecord) { 223 io.out.brInfo.map(_.debug_ubtb_cycle := GTimer()) 224 } 225} 226@chiselName 227class BPUStage2 extends BPUStage { 228 // Use latched response from s1 229 val btbResp = inLatch.resp.btb 230 val bimResp = inLatch.resp.bim 231 takens := VecInit((0 until PredictWidth).map(i => btbResp.hits(i) && (btbResp.types(i) === BTBtype.B && bimResp.ctrs(i)(1) || btbResp.types(i) =/= BTBtype.B))) 232 targets := btbResp.targets 233 brMask := VecInit((0 until PredictWidth).map(i => btbResp.types(i) === BTBtype.B && btbResp.hits(i))) 234 jalMask := DontCare 235 236 firstBankHasHalfRVI := Mux(lastBankHasInst, false.B, btbResp.hits(bankWidth-1) && !btbResp.isRVC(bankWidth-1) && inLatch.mask(bankWidth-1)) && HasCExtension.B 237 lastBankHasHalfRVI := btbResp.hits(PredictWidth-1) && !btbResp.isRVC(PredictWidth-1) && inLatch.mask(PredictWidth-1) && HasCExtension.B 238 239 if (BPUDebug) { 240 XSDebug(io.outFire, "outPred using btb&bim resp: hits:%b, ctrTakens:%b\n", 241 btbResp.hits.asUInt, VecInit(bimResp.ctrs.map(_(1))).asUInt) 242 } 243 if (EnableBPUTimeRecord) { 244 io.out.brInfo.map(_.debug_btb_cycle := GTimer()) 245 } 246} 247@chiselName 248class BPUStage3 extends BPUStage { 249 class S3IO extends XSBundle { 250 251 val predecode = Input(new Predecode) 252 val realMask = Input(UInt(PredictWidth.W)) 253 val prevHalf = Flipped(ValidIO(new PrevHalfInstr)) 254 val recover = Flipped(ValidIO(new CfiUpdateInfo)) 255 } 256 val s3IO = IO(new S3IO) 257 // TAGE has its own pipelines and the 258 // response comes directly from s3, 259 // so we do not use those from inLatch 260 val tageResp = io.in.resp.tage 261 val tageTakens = tageResp.takens 262 263 val loopResp = io.in.resp.loop.exit 264 265 // realMask is in it 266 val pdMask = s3IO.predecode.mask 267 val pdLastHalf = s3IO.predecode.lastHalf 268 val pds = s3IO.predecode.pd 269 270 val btbResp = WireInit(inLatch.resp.btb) 271 val btbHits = WireInit(btbResp.hits.asUInt) 272 val bimTakens = VecInit(inLatch.resp.bim.ctrs.map(_(1))) 273 274 val brs = pdMask & Reverse(Cat(pds.map(_.isBr))) 275 val jals = pdMask & Reverse(Cat(pds.map(_.isJal))) 276 val jalrs = pdMask & Reverse(Cat(pds.map(_.isJalr))) 277 val calls = pdMask & Reverse(Cat(pds.map(_.isCall))) 278 val rets = pdMask & Reverse(Cat(pds.map(_.isRet))) 279 val RVCs = pdMask & Reverse(Cat(pds.map(_.isRVC))) 280 281 val callIdx = PriorityEncoder(calls) 282 val retIdx = PriorityEncoder(rets) 283 284 val brPred = (if(EnableBPD) tageTakens else bimTakens).asUInt 285 val loopRes = (if (EnableLoop) loopResp else VecInit(Fill(PredictWidth, 0.U(1.W)))).asUInt 286 val prevHalfTaken = s3IO.prevHalf.valid && s3IO.prevHalf.bits.taken && HasCExtension.B 287 val prevHalfTakenMask = prevHalfTaken.asUInt 288 val brTakens = ((brs & brPred | prevHalfTakenMask) & ~loopRes) 289 // VecInit((0 until PredictWidth).map(i => brs(i) && (brPred(i) || (if (i == 0) prevHalfTaken else false.B)) && !loopRes(i))) 290 // we should provide btb resp as well 291 btbHits := btbResp.hits.asUInt | prevHalfTakenMask 292 293 // predict taken only if btb has a target, jal targets will be provided by IFU 294 takens := VecInit((0 until PredictWidth).map(i => (brTakens(i) || jalrs(i)) && btbHits(i) || jals(i))) 295 296 297 targets := inLatch.resp.btb.targets 298 299 brMask := WireInit(brs.asTypeOf(Vec(PredictWidth, Bool()))) 300 jalMask := WireInit(jals.asTypeOf(Vec(PredictWidth, Bool()))) 301 302 lastBankHasInst := s3IO.realMask(PredictWidth-1, bankWidth).orR 303 firstBankHasHalfRVI := Mux(lastBankHasInst, false.B, pdLastHalf(0)) && HasCExtension.B 304 lastBankHasHalfRVI := pdLastHalf(1) && HasCExtension.B 305 306 //RAS 307 if(EnableRAS){ 308 val ras = Module(new RAS) 309 ras.io <> DontCare 310 ras.io.pc.bits := bankAligned(inLatch.pc) 311 ras.io.pc.valid := io.outFire//predValid 312 ras.io.is_ret := rets.orR && (retIdx === io.pred.jmpIdx) 313 ras.io.callIdx.valid := calls.orR && (callIdx === io.pred.jmpIdx) 314 ras.io.callIdx.bits := callIdx 315 ras.io.isRVC := (calls & RVCs).orR //TODO: this is ugly 316 ras.io.isLastHalfRVI := s3IO.predecode.hasLastHalfRVI 317 ras.io.recover := s3IO.recover 318 319 for(i <- 0 until PredictWidth){ 320 io.out.brInfo(i).rasSp := ras.io.meta.rasSp 321 io.out.brInfo(i).rasTopCtr := ras.io.meta.rasTopCtr 322 io.out.brInfo(i).rasToqAddr := ras.io.meta.rasToqAddr 323 } 324 takens := VecInit((0 until PredictWidth).map(i => { 325 ((brTakens(i) || jalrs(i)) && btbHits(i)) || 326 jals(i) || 327 (ras.io.out.valid && rets(i)) || 328 (!ras.io.out.valid && rets(i) && btbHits(i)) 329 } 330 )) 331 332 for (i <- 0 until PredictWidth) { 333 when(rets(i) && ras.io.out.valid){ 334 targets(i) := ras.io.out.bits.target 335 } 336 } 337 } 338 339 340 // we should provide the prediction for the first half RVI of the end of a fetch packet 341 // branch taken information would be lost in the prediction of the next packet, 342 // so we preserve this information here 343 when (firstBankHasHalfRVI && btbResp.types(bankWidth-1) === BTBtype.B && btbHits(bankWidth-1) && HasCExtension.B) { 344 takens(bankWidth-1) := brPred(bankWidth-1) && !loopRes(bankWidth-1) 345 } 346 when (lastBankHasHalfRVI && btbResp.types(PredictWidth-1) === BTBtype.B && btbHits(PredictWidth-1) && HasCExtension.B) { 347 takens(PredictWidth-1) := brPred(PredictWidth-1) && !loopRes(PredictWidth-1) 348 } 349 350 // targets would be lost as well, since it is from btb 351 // unless it is a ret, which target is from ras 352 when (prevHalfTaken && !rets(0) && HasCExtension.B) { 353 targets(0) := s3IO.prevHalf.bits.target 354 } 355 356 // Wrap tage resp and tage meta in 357 // This is ugly 358 io.out.resp.tage <> io.in.resp.tage 359 io.out.resp.loop <> io.in.resp.loop 360 for (i <- 0 until PredictWidth) { 361 io.out.brInfo(i).tageMeta := io.in.brInfo(i).tageMeta 362 io.out.brInfo(i).specCnt := io.in.brInfo(i).specCnt 363 } 364 365 if (BPUDebug) { 366 XSDebug(io.inFire, "predecode: pc:%x, mask:%b\n", inLatch.pc, s3IO.predecode.mask) 367 for (i <- 0 until PredictWidth) { 368 val p = s3IO.predecode.pd(i) 369 XSDebug(io.inFire && s3IO.predecode.mask(i), "predecode(%d): brType:%d, br:%d, jal:%d, jalr:%d, call:%d, ret:%d, RVC:%d, excType:%d\n", 370 i.U, p.brType, p.isBr, p.isJal, p.isJalr, p.isCall, p.isRet, p.isRVC, p.excType) 371 } 372 XSDebug(p"brs:${Binary(brs)} jals:${Binary(jals)} jalrs:${Binary(jalrs)} calls:${Binary(calls)} rets:${Binary(rets)} rvcs:${Binary(RVCs)}\n") 373 XSDebug(p"callIdx:${callIdx} retIdx:${retIdx}\n") 374 XSDebug(p"brPred:${Binary(brPred)} loopRes:${Binary(loopRes)} prevHalfTaken:${prevHalfTaken} brTakens:${Binary(brTakens)}\n") 375 } 376 377 if (EnbaleCFIPredLog) { 378 val out = io.out 379 XSDebug(io.outFire, p"cfi_pred: fetchpc(${Hexadecimal(out.pc)}) mask(${out.mask}) brmask(${brMask.asUInt}) hist(${Hexadecimal(io.debug_hist)})\n") 380 } 381 382 if (EnableBPUTimeRecord) { 383 io.out.brInfo.map(_.debug_tage_cycle := GTimer()) 384 } 385} 386 387trait BranchPredictorComponents extends HasXSParameter { 388 val ubtb = Module(new MicroBTB) 389 val btb = Module(new BTB) 390 val bim = Module(new BIM) 391 val tage = (if(EnableBPD) { Module(new Tage) } 392 else { Module(new FakeTage) }) 393 val loop = Module(new LoopPredictor) 394 val preds = Seq(ubtb, btb, bim, tage, loop) 395 preds.map(_.io := DontCare) 396} 397 398class BPUReq extends XSBundle { 399 val pc = UInt(VAddrBits.W) 400 val hist = UInt(HistoryLength.W) 401 val inMask = UInt(PredictWidth.W) 402 // val histPtr = UInt(log2Up(ExtHistoryLength).W) // only for debug 403} 404 405// class CfiUpdateInfoWithHist extends XSBundle { 406// val ui = new CfiUpdateInfo 407// val hist = UInt(HistoryLength.W) 408// } 409 410// object CfiUpdateInfoWithHist { 411// def apply (brInfo: CfiUpdateInfo, hist: UInt) = { 412// val b = Wire(new CfiUpdateInfoWithHist) 413// b.ui <> brInfo 414// b.hist := hist 415// b 416// } 417// } 418 419abstract class BaseBPU extends XSModule with BranchPredictorComponents with HasBPUParameter{ 420 val io = IO(new Bundle() { 421 // from backend 422 val cfiUpdateInfo = Flipped(ValidIO(new CfiUpdateInfo)) 423 // val cfiUpdateInfo = Flipped(ValidIO(new CfiUpdateInfoWithHist)) 424 // from ifu, frontend redirect 425 val flush = Input(Vec(3, Bool())) 426 // from if1 427 val in = Input(new BPUReq) 428 val inFire = Input(Vec(4, Bool())) 429 // to if2/if3/if4 430 val out = Vec(3, Output(new BranchPrediction)) 431 // from if4 432 val predecode = Input(new Predecode) 433 val realMask = Input(UInt(PredictWidth.W)) 434 val prevHalf = Flipped(ValidIO(new PrevHalfInstr)) 435 // to if4, some bpu info used for updating 436 val bpuMeta = Output(Vec(PredictWidth, new BpuMeta)) 437 }) 438 439 def npc(pc: UInt, instCount: UInt) = pc + (instCount << 1.U) 440 441 preds.map(_.io.update <> io.cfiUpdateInfo) 442 // tage.io.update <> io.cfiUpdateInfo 443 444 val s1 = Module(new BPUStage1) 445 val s2 = Module(new BPUStage2) 446 val s3 = Module(new BPUStage3) 447 448 val s1_fire = io.inFire(0) 449 val s2_fire = io.inFire(1) 450 val s3_fire = io.inFire(2) 451 val s4_fire = io.inFire(3) 452 453 s1.io.flush := io.flush(0) 454 s2.io.flush := io.flush(1) 455 s3.io.flush := io.flush(2) 456 457 s1.io.in <> DontCare 458 s2.io.in <> s1.io.out 459 s3.io.in <> s2.io.out 460 461 s1.io.inFire := s1_fire 462 s2.io.inFire := s2_fire 463 s3.io.inFire := s3_fire 464 465 s1.io.outFire := s2_fire 466 s2.io.outFire := s3_fire 467 s3.io.outFire := s4_fire 468 469 io.out(0) <> s1.io.pred 470 io.out(1) <> s2.io.pred 471 io.out(2) <> s3.io.pred 472 473 io.bpuMeta := s3.io.out.brInfo 474 475 if (BPUDebug) { 476 XSDebug(io.inFire(3), "bpuMeta sent!\n") 477 for (i <- 0 until PredictWidth) { 478 val b = io.bpuMeta(i) 479 XSDebug(io.inFire(3), "brInfo(%d): ubtbWrWay:%d, ubtbHit:%d, btbWrWay:%d, btbHitJal:%d, bimCtr:%d, fetchIdx:%d\n", 480 i.U, b.ubtbWriteWay, b.ubtbHits, b.btbWriteWay, b.btbHitJal, b.bimCtr, b.fetchIdx) 481 val t = b.tageMeta 482 XSDebug(io.inFire(3), " tageMeta: pvder(%d):%d, altDiffers:%d, pvderU:%d, pvderCtr:%d, allocate(%d):%d\n", 483 t.provider.valid, t.provider.bits, t.altDiffers, t.providerU, t.providerCtr, t.allocate.valid, t.allocate.bits) 484 } 485 } 486 val debug_verbose = false 487} 488 489 490class FakeBPU extends BaseBPU { 491 io.out.foreach(i => { 492 // Provide not takens 493 i <> DontCare 494 i.takens := 0.U 495 }) 496 io.bpuMeta <> DontCare 497} 498@chiselName 499class BPU extends BaseBPU { 500 501 //**********************Stage 1****************************// 502 503 val s1_resp_in = Wire(new PredictorResponse) 504 val s1_brInfo_in = Wire(Vec(PredictWidth, new BpuMeta)) 505 506 s1_resp_in.tage := DontCare 507 s1_resp_in.loop := DontCare 508 s1_brInfo_in := DontCare 509 (0 until PredictWidth).foreach(i => s1_brInfo_in(i).fetchIdx := i.U) 510 511 val s1_inLatch = RegEnable(io.in, s1_fire) 512 ubtb.io.flush := io.flush(0) // TODO: fix this 513 ubtb.io.pc.valid := s2_fire 514 ubtb.io.pc.bits := s1_inLatch.pc 515 ubtb.io.inMask := s1_inLatch.inMask 516 517 518 519 // Wrap ubtb response into resp_in and brInfo_in 520 s1_resp_in.ubtb <> ubtb.io.out 521 for (i <- 0 until PredictWidth) { 522 s1_brInfo_in(i).ubtbWriteWay := ubtb.io.uBTBMeta.writeWay(i) 523 s1_brInfo_in(i).ubtbHits := ubtb.io.uBTBMeta.hits(i) 524 } 525 526 btb.io.flush := io.flush(0) // TODO: fix this 527 btb.io.pc.valid := s1_fire 528 btb.io.pc.bits := io.in.pc 529 btb.io.inMask := io.in.inMask 530 531 532 533 // Wrap btb response into resp_in and brInfo_in 534 s1_resp_in.btb <> btb.io.resp 535 for (i <- 0 until PredictWidth) { 536 s1_brInfo_in(i).btbWriteWay := btb.io.meta.writeWay(i) 537 s1_brInfo_in(i).btbHitJal := btb.io.meta.hitJal(i) 538 } 539 540 bim.io.flush := io.flush(0) // TODO: fix this 541 bim.io.pc.valid := s1_fire 542 bim.io.pc.bits := io.in.pc 543 bim.io.inMask := io.in.inMask 544 545 546 // Wrap bim response into resp_in and brInfo_in 547 s1_resp_in.bim <> bim.io.resp 548 for (i <- 0 until PredictWidth) { 549 s1_brInfo_in(i).bimCtr := bim.io.meta.ctrs(i) 550 } 551 552 553 s1.io.inFire := s1_fire 554 s1.io.in.pc := io.in.pc 555 s1.io.in.mask := io.in.inMask 556 s1.io.in.resp <> s1_resp_in 557 s1.io.in.brInfo <> s1_brInfo_in 558 559 val s1_hist = RegEnable(io.in.hist, enable=s1_fire) 560 val s2_hist = RegEnable(s1_hist, enable=s2_fire) 561 val s3_hist = RegEnable(s2_hist, enable=s3_fire) 562 563 s1.io.debug_hist := s1_hist 564 s2.io.debug_hist := s2_hist 565 s3.io.debug_hist := s3_hist 566 567 //**********************Stage 2****************************// 568 tage.io.flush := io.flush(1) // TODO: fix this 569 tage.io.pc.valid := s2_fire 570 tage.io.pc.bits := s2.io.in.pc // PC from s1 571 tage.io.hist := s1_hist // The inst is from s1 572 tage.io.inMask := s2.io.in.mask 573 tage.io.s3Fire := s3_fire // Tell tage to march 1 stage 574 tage.io.bim <> s1.io.out.resp.bim // Use bim results from s1 575 576 //**********************Stage 3****************************// 577 // Wrap tage response and meta into s3.io.in.bits 578 // This is ugly 579 580 loop.io.flush := io.flush(2) 581 loop.io.pc.valid := s3_fire 582 loop.io.pc.bits := s3.io.in.pc 583 loop.io.inMask := s3.io.in.mask 584 loop.io.outFire := s4_fire 585 loop.io.respIn.taken := s3.io.pred.taken 586 loop.io.respIn.jmpIdx := s3.io.pred.jmpIdx 587 588 589 s3.io.in.resp.tage <> tage.io.resp 590 s3.io.in.resp.loop <> loop.io.resp 591 for (i <- 0 until PredictWidth) { 592 s3.io.in.brInfo(i).tageMeta := tage.io.meta(i) 593 s3.io.in.brInfo(i).specCnt := loop.io.meta.specCnts(i) 594 } 595 596 s3.s3IO.predecode <> io.predecode 597 598 s3.s3IO.realMask := io.realMask 599 600 s3.s3IO.prevHalf := io.prevHalf 601 602 s3.s3IO.recover.valid <> io.cfiUpdateInfo.valid 603 s3.s3IO.recover.bits <> io.cfiUpdateInfo.bits 604 605 if (BPUDebug) { 606 if (debug_verbose) { 607 val uo = ubtb.io.out 608 XSDebug("debug: ubtb hits:%b, takens:%b, notTakens:%b\n", uo.hits.asUInt, uo.takens.asUInt, ~uo.takens.asUInt & uo.brMask.asUInt) 609 val bio = bim.io.resp 610 XSDebug("debug: bim takens:%b\n", VecInit(bio.ctrs.map(_(1))).asUInt) 611 val bo = btb.io.resp 612 XSDebug("debug: btb hits:%b\n", bo.hits.asUInt) 613 } 614 } 615 616 617 618 if (EnableCFICommitLog) { 619 val buValid = io.cfiUpdateInfo.valid && !io.cfiUpdateInfo.bits.isReplay 620 val buinfo = io.cfiUpdateInfo.bits 621 val pd = buinfo.pd 622 val tage_cycle = buinfo.bpuMeta.debug_tage_cycle 623 XSDebug(buValid, p"cfi_update: isBr(${pd.isBr}) pc(${Hexadecimal(buinfo.pc)}) taken(${buinfo.taken}) mispred(${buinfo.isMisPred}) cycle($tage_cycle) hist(${Hexadecimal(buinfo.bpuMeta.predHist.asUInt)})\n") 624 } 625 626} 627 628object BPU{ 629 def apply(enableBPU: Boolean = true) = { 630 if(enableBPU) { 631 val BPU = Module(new BPU) 632 BPU 633 } 634 else { 635 val FakeBPU = Module(new FakeBPU) 636 FakeBPU 637 } 638 } 639} 640