1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import difftest._ 23import freechips.rocketchip.util.SRAMAnnotation 24import xiangshan._ 25import utils._ 26import utility._ 27import xiangshan.backend.fu.{PMPChecker, PMPReqBundle, PMPConfig => XSPMPConfig} 28import xiangshan.backend.rob.RobPtr 29import xiangshan.backend.fu.util.HasCSRConst 30import freechips.rocketchip.rocket.PMPConfig 31 32/** TLB module 33 * support block request and non-block request io at the same time 34 * return paddr at next cycle, then go for pmp/pma check 35 * @param Width: The number of requestors 36 * @param Block: Blocked or not for each requestor ports 37 * @param q: TLB Parameters, like entry number, each TLB has its own parameters 38 * @param p: XiangShan Paramemters, like XLEN 39 */ 40 41class TLB(Width: Int, nRespDups: Int = 1, Block: Seq[Boolean], q: TLBParameters)(implicit p: Parameters) extends TlbModule 42 with HasCSRConst 43 with HasPerfEvents 44{ 45 val io = IO(new TlbIO(Width, nRespDups, q)) 46 47 val req = io.requestor.map(_.req) 48 val resp = io.requestor.map(_.resp) 49 val ptw = io.ptw 50 val pmp = io.pmp 51 val refill_to_mem = io.refill_to_mem 52 53 /** Sfence.vma & Svinval 54 * Sfence.vma will 1. flush old entries 2. flush inflight 3. flush pipe 55 * Svinval will 1. flush old entries 2. flush inflight 56 * So, Svinval will not flush pipe, which means 57 * it should not drop reqs from pipe and should return right resp 58 */ 59 val sfence = DelayN(io.sfence, q.fenceDelay) 60 val csr = io.csr 61 val satp = DelayN(io.csr.satp, q.fenceDelay) 62 val vsatp = DelayN(io.csr.vsatp, q.fenceDelay) 63 val hgatp = DelayN(io.csr.hgatp, q.fenceDelay) 64 65 val flush_mmu = DelayN(sfence.valid || csr.satp.changed || csr.vsatp.changed || csr.hgatp.changed, q.fenceDelay) 66 val mmu_flush_pipe = DelayN(sfence.valid && sfence.bits.flushPipe, q.fenceDelay) // for svinval, won't flush pipe 67 val flush_pipe = io.flushPipe 68 69 val req_in = req 70 val req_out = req.map(a => RegEnable(a.bits, a.fire())) 71 val req_out_v = (0 until Width).map(i => ValidHold(req_in(i).fire && !req_in(i).bits.kill, resp(i).fire, flush_pipe(i))) 72 73 val isHyperInst = (0 until Width).map(i => req_out_v(i) && req_out(i).hyperinst) 74 75 // ATTENTION: csr and flush from backend are delayed. csr should not be later than flush. 76 // because, csr will influence tlb behavior. 77 val ifecth = if (q.fetchi) true.B else false.B 78 val mode_tmp = if (q.useDmode) csr.priv.dmode else csr.priv.imode 79 val mode = (0 until Width).map(i => Mux(isHyperInst(i), csr.priv.spvp, mode_tmp)) 80 val virt = csr.priv.virt 81 val sum = (0 until Width).map(i => Mux(virt || isHyperInst(i), io.csr.priv.vsum, io.csr.priv.sum)) 82 val mxr = (0 until Width).map(i => Mux(virt || isHyperInst(i), io.csr.priv.vmxr || io.csr.priv.mxr, io.csr.priv.mxr)) 83 val req_in_s2xlate = (0 until Width).map(i => MuxCase(noS2xlate, Seq( 84 (!(virt || req_in(i).bits.hyperinst)) -> noS2xlate, 85 (csr.vsatp.mode =/= 0.U && csr.hgatp.mode =/= 0.U) -> allStage, 86 (csr.vsatp.mode === 0.U) -> onlyStage2, 87 (csr.hgatp.mode === 0.U) -> onlyStage1 88 ))) 89 val req_out_s2xlate = (0 until Width).map(i => MuxCase(noS2xlate, Seq( 90 (!(virt || isHyperInst(i))) -> noS2xlate, 91 (csr.vsatp.mode =/= 0.U && csr.hgatp.mode =/= 0.U) -> allStage, 92 (csr.vsatp.mode === 0.U) -> onlyStage2, 93 (csr.hgatp.mode === 0.U) -> onlyStage1 94 ))) 95 val need_gpa = RegInit(false.B) 96 val need_gpa_vpn = Reg(UInt(vpnLen.W)) 97 val need_gpa_gvpn = Reg(UInt(vpnLen.W)) 98 val hasGpf = Wire(Vec(Width, Bool())) 99 100 // val vmEnable = satp.mode === 8.U // && (mode < ModeM) // FIXME: fix me when boot xv6/linux... 101 val vmEnable = (0 until Width).map(i => if (EnbaleTlbDebug) (satp.mode === 8.U) 102 else (satp.mode === 8.U) && (mode(i) < ModeM)) 103 val s2xlateEnable = (0 until Width).map(i => (isHyperInst(i) || virt) && (vsatp.mode === 8.U || hgatp.mode === 8.U) && (mode(i) < ModeM)) 104 val portTranslateEnable = (0 until Width).map(i => (vmEnable(i) || s2xlateEnable(i)) && RegNext(!req(i).bits.no_translate)) 105 106 107 val refill = (0 until Width).map(i => ptw.resp.fire && !(need_gpa && need_gpa_vpn === ptw.resp.bits.getVpn) && !flush_mmu && (vmEnable(i) || ptw.resp.bits.s2xlate =/= noS2xlate)) 108 refill_to_mem := DontCare 109 val entries = Module(new TlbStorageWrapper(Width, q, nRespDups)) 110 entries.io.base_connect(sfence, csr, satp) 111 if (q.outReplace) { io.replace <> entries.io.replace } 112 for (i <- 0 until Width) { 113 entries.io.r_req_apply(io.requestor(i).req.valid, get_pn(req_in(i).bits.vaddr), i, req_in_s2xlate(i)) 114 entries.io.w_apply(refill(i), ptw.resp.bits) 115 resp(i).bits.debug.isFirstIssue := RegNext(req(i).bits.debug.isFirstIssue) 116 resp(i).bits.debug.robIdx := RegNext(req(i).bits.debug.robIdx) 117 } 118 119 // read TLB, get hit/miss, paddr, perm bits 120 val readResult = (0 until Width).map(TLBRead(_)) 121 val hitVec = readResult.map(_._1) 122 val missVec = readResult.map(_._2) 123 val pmp_addr = readResult.map(_._3) 124 val perm = readResult.map(_._4) 125 val g_perm = readResult.map(_._5) 126 // check pmp use paddr (for timing optization, use pmp_addr here) 127 // check permisson 128 (0 until Width).foreach{i => 129 pmp_check(pmp_addr(i), req_out(i).size, req_out(i).cmd, i) 130 for (d <- 0 until nRespDups) { 131 perm_check(perm(i)(d), req_out(i).cmd, i, d, g_perm(i)(d), req_out(i).hlvx, req_out_s2xlate(i)) 132 } 133 hasGpf(i) := resp(i).bits.excp(0).gpf.ld || resp(i).bits.excp(0).gpf.st || resp(i).bits.excp(0).gpf.instr 134 } 135 136 // handle block or non-block io 137 // for non-block io, just return the above result, send miss to ptw 138 // for block io, hold the request, send miss to ptw, 139 // when ptw back, return the result 140 (0 until Width) foreach {i => 141 if (Block(i)) handle_block(i) 142 else handle_nonblock(i) 143 } 144 io.ptw.resp.ready := true.B 145 146 /************************ main body above | method/log/perf below ****************************/ 147 def TLBRead(i: Int) = { 148 val (e_hit, e_ppn, e_perm, e_g_perm, e_s2xlate) = entries.io.r_resp_apply(i) 149 val (p_hit, p_ppn, p_perm, p_gvpn, p_g_perm, p_s2xlate) = ptw_resp_bypass(get_pn(req_in(i).bits.vaddr), req_in_s2xlate(i)) 150 val enable = portTranslateEnable(i) 151 val isOnlys2xlate = req_out_s2xlate(i) === onlyStage2 152 val resp_gpa_refill = RegInit(false.B) 153 val need_gpa_vpn_hit = RegEnable(need_gpa_vpn === get_pn(req_in(i).bits.vaddr), req_in(i).fire()) 154 when (io.requestor(i).resp.valid && hasGpf(i) && need_gpa === false.B && !need_gpa_vpn_hit && !isOnlys2xlate) { 155 need_gpa := true.B 156 need_gpa_vpn := get_pn(req_out(i).vaddr) 157 resp_gpa_refill := false.B 158 } 159 when (ptw.resp.fire && need_gpa && need_gpa_vpn === ptw.resp.bits.getVpn) { 160 need_gpa_gvpn := Mux(ptw.resp.bits.s2xlate === onlyStage2, Cat(ptw.resp.bits.s1.entry.tag, ptw.resp.bits.s1.ppn_low(OHToUInt(ptw.resp.bits.s1.pteidx))), ptw.resp.bits.s2.entry.tag) 161 resp_gpa_refill := true.B 162 } 163 164 when (hasGpf(i) && resp_gpa_refill && need_gpa_vpn_hit){ 165 need_gpa := false.B 166 } 167 168 val hit = e_hit || p_hit 169 val miss = (!hit && enable) || hasGpf(i) && !(resp_gpa_refill && need_gpa_vpn_hit) && !isOnlys2xlate 170 hit.suggestName(s"hit_read_${i}") 171 miss.suggestName(s"miss_read_${i}") 172 173 val vaddr = SignExt(req_out(i).vaddr, PAddrBits) 174 resp(i).bits.miss := miss 175 resp(i).bits.ptwBack := ptw.resp.fire 176 resp(i).bits.memidx := RegNext(req_in(i).bits.memidx) 177 178 val ppn = WireInit(VecInit(Seq.fill(nRespDups)(0.U(ppnLen.W)))) 179 val perm = WireInit(VecInit(Seq.fill(nRespDups)(0.U.asTypeOf(new TlbPermBundle)))) 180 val gvpn = WireInit(VecInit(Seq.fill(nRespDups)(0.U(vpnLen.W)))) 181 val g_perm = WireInit(VecInit(Seq.fill(nRespDups)(0.U.asTypeOf(new TlbPermBundle)))) 182 val r_s2xlate = WireInit(VecInit(Seq.fill(nRespDups)(0.U(2.W)))) 183 for (d <- 0 until nRespDups) { 184 ppn(d) := Mux(p_hit, p_ppn, e_ppn(d)) 185 perm(d) := Mux(p_hit, p_perm, e_perm(d)) 186 gvpn(d) := Mux(hasGpf(i), need_gpa_gvpn, 0.U) 187 g_perm(d) := Mux(p_hit, p_g_perm, e_g_perm(d)) 188 r_s2xlate(d) := Mux(p_hit, p_s2xlate, e_s2xlate(d)) 189 val paddr = Cat(ppn(d), get_off(req_out(i).vaddr)) 190 val gpaddr = Cat(gvpn(d), get_off(req_out(i).vaddr)) 191 resp(i).bits.paddr(d) := Mux(enable, paddr, vaddr) 192 resp(i).bits.gpaddr(d) := Mux(r_s2xlate(d) === onlyStage2, vaddr, gpaddr) 193 } 194 195 XSDebug(req_out_v(i), p"(${i.U}) hit:${hit} miss:${miss} ppn:${Hexadecimal(ppn(0))} perm:${perm(0)}\n") 196 197 val pmp_paddr = resp(i).bits.paddr(0) 198 199 (hit, miss, pmp_paddr, perm, g_perm) 200 } 201 202 def pmp_check(addr: UInt, size: UInt, cmd: UInt, idx: Int): Unit = { 203 pmp(idx).valid := resp(idx).valid 204 pmp(idx).bits.addr := addr 205 pmp(idx).bits.size := size 206 pmp(idx).bits.cmd := cmd 207 } 208 209 def perm_check(perm: TlbPermBundle, cmd: UInt, idx: Int, nDups: Int, g_perm: TlbPermBundle, hlvx: Bool, s2xlate: UInt) = { 210 // for timing optimization, pmp check is divided into dynamic and static 211 // dynamic: superpage (or full-connected reg entries) -> check pmp when translation done 212 // static: 4K pages (or sram entries) -> check pmp with pre-checked results 213 val hasS2xlate = s2xlate =/= noS2xlate 214 val onlyS2 = s2xlate === onlyStage2 215 val af = perm.af || (hasS2xlate && g_perm.af) 216 217 // Stage 1 perm check 218 val pf = perm.pf 219 val ldUpdate = !perm.a && TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd) // update A/D through exception 220 val stUpdate = (!perm.a || !perm.d) && (TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd)) // update A/D through exception 221 val instrUpdate = !perm.a && TlbCmd.isExec(cmd) // update A/D through exception 222 val modeCheck = !(mode(idx) === ModeU && !perm.u || mode(idx) === ModeS && perm.u && (!sum(idx) || ifecth)) 223 val ldPermFail = !(modeCheck && Mux(hlvx, perm.x, perm.r || mxr(idx) && perm.x)) 224 val stPermFail = !(modeCheck && perm.w) 225 val instrPermFail = !(modeCheck && perm.x) 226 val ldPf = (ldPermFail || pf) && (TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd)) 227 val stPf = (stPermFail || pf) && (TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd)) 228 val instrPf = (instrPermFail || pf) && TlbCmd.isExec(cmd) 229 val s1_valid = portTranslateEnable(idx) && !onlyS2 230 231 // Stage 2 perm check 232 val gpf = g_perm.pf 233 val g_ldUpdate = !g_perm.a && TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd) 234 val g_stUpdate = (!g_perm.a || !g_perm.d) && (TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd)) 235 val g_instrUpdate = !g_perm.a && TlbCmd.isExec(cmd) 236 val g_ldPermFail = !Mux(hlvx, g_perm.x, (g_perm.r || io.csr.priv.mxr && g_perm.x)) 237 val g_stPermFail = !g_perm.w 238 val g_instrPermFail = !g_perm.x 239 val ldGpf = (g_ldPermFail || gpf) && (TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd)) 240 val stGpf = (g_stPermFail || gpf) && (TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd)) 241 val instrGpf = (g_instrPermFail || gpf) && TlbCmd.isExec(cmd) 242 val s2_valid = hasS2xlate && portTranslateEnable(idx) 243 244 val fault_valid = s1_valid || s2_valid 245 246 // when pf and gpf can't happens simultaneously 247 val hasPf = (ldPf || ldUpdate || stPf || stUpdate || instrPf || instrUpdate) && s1_valid && !af 248 resp(idx).bits.excp(nDups).pf.ld := (ldPf || ldUpdate) && s1_valid && !af 249 resp(idx).bits.excp(nDups).pf.st := (stPf || stUpdate) && s1_valid && !af 250 resp(idx).bits.excp(nDups).pf.instr := (instrPf || instrUpdate) && s1_valid && !af 251 // NOTE: pf need && with !af, page fault has higher priority than access fault 252 // but ptw may also have access fault, then af happens, the translation is wrong. 253 // In this case, pf has lower priority than af 254 255 resp(idx).bits.excp(nDups).gpf.ld := (ldGpf || g_ldUpdate) && s2_valid && !af && !hasPf 256 resp(idx).bits.excp(nDups).gpf.st := (stGpf || g_stUpdate) && s2_valid && !af && !hasPf 257 resp(idx).bits.excp(nDups).gpf.instr := (instrGpf || g_instrUpdate) && s2_valid && !af && !hasPf 258 259 resp(idx).bits.excp(nDups).af.ld := af && TlbCmd.isRead(cmd) && fault_valid 260 resp(idx).bits.excp(nDups).af.st := af && TlbCmd.isWrite(cmd) && fault_valid 261 resp(idx).bits.excp(nDups).af.instr := af && TlbCmd.isExec(cmd) && fault_valid 262 263 264 } 265 266 def handle_nonblock(idx: Int): Unit = { 267 io.requestor(idx).resp.valid := req_out_v(idx) 268 io.requestor(idx).req.ready := io.requestor(idx).resp.ready // should always be true 269 XSError(!io.requestor(idx).resp.ready, s"${q.name} port ${idx} is non-block, resp.ready must be true.B") 270 271 val req_need_gpa = hasGpf(idx) 272 val req_s2xlate = Wire(UInt(2.W)) 273 req_s2xlate := MuxCase(noS2xlate, Seq( 274 (!(virt || req_out(idx).hyperinst)) -> noS2xlate, 275 (vsatp.mode =/= 0.U && hgatp.mode =/= 0.U) -> allStage, 276 (vsatp.mode === 0.U) -> onlyStage2, 277 (hgatp.mode === 0.U || req_need_gpa) -> onlyStage1 278 )) 279 val ptw_s2xlate = ptw.resp.bits.s2xlate 280 val has_s2xlate = ptw_s2xlate =/= noS2xlate 281 val onlyS2 = ptw_s2xlate === onlyStage2 282 val ptw_s1_hit = ptw.resp.bits.s1.hit(get_pn(req_out(idx).vaddr), Mux(has_s2xlate, io.csr.vsatp.asid, io.csr.satp.asid), io.csr.hgatp.asid, true, false, has_s2xlate) 283 val ptw_s2_hit = ptw.resp.bits.s2.hit(get_pn(req_out(idx).vaddr), io.csr.hgatp.asid) 284 val ptw_just_back = ptw.resp.fire && req_s2xlate === ptw_s2xlate && Mux(onlyS2, ptw_s2_hit, ptw_s1_hit) 285 val ptw_already_back = RegNext(ptw.resp.fire) && RegNext(ptw.resp.bits).hit(get_pn(req_out(idx).vaddr), asid = io.csr.satp.asid, allType = true) 286 io.ptw.req(idx).valid := req_out_v(idx) && (missVec(idx)) && !(ptw_just_back || ptw_already_back) // TODO: remove the regnext, timing 287 io.tlbreplay(idx) := req_out_v(idx) && missVec(idx) && (ptw_just_back || ptw_already_back) 288 when (io.requestor(idx).req_kill && RegNext(io.requestor(idx).req.fire)) { 289 io.ptw.req(idx).valid := false.B 290 io.tlbreplay(idx) := true.B 291 } 292 io.ptw.req(idx).bits.vpn := get_pn(req_out(idx).vaddr) 293 io.ptw.req(idx).bits.s2xlate := RegNext(req_s2xlate) 294 io.ptw.req(idx).bits.memidx := req_out(idx).memidx 295 } 296 297 def handle_block(idx: Int): Unit = { 298 // three valid: 1.if exist a entry; 2.if sent to ptw; 3.unset resp.valid 299 io.requestor(idx).req.ready := !req_out_v(idx) || io.requestor(idx).resp.fire 300 // req_out_v for if there is a request, may long latency, fixme 301 302 // miss request entries 303 val req_need_gpa = hasGpf(idx) 304 val miss_req_vpn = get_pn(req_out(idx).vaddr) 305 val miss_req_memidx = req_out(idx).memidx 306 val miss_req_s2xlate = Wire(UInt(2.W)) 307 miss_req_s2xlate := MuxCase(noS2xlate, Seq( 308 (!(virt || req_out(idx).hyperinst)) -> noS2xlate, 309 (vsatp.mode =/= 0.U && hgatp.mode =/= 0.U) -> allStage, 310 (vsatp.mode === 0.U) -> onlyStage2, 311 (hgatp.mode === 0.U || req_need_gpa) -> onlyStage1 312 )) 313 val miss_req_s2xlate_reg = RegEnable(miss_req_s2xlate, io.ptw.req(idx).fire()) 314 val hasS2xlate = miss_req_s2xlate_reg =/= noS2xlate 315 val onlyS2 = miss_req_s2xlate_reg === onlyStage2 316 val hit_s1 = io.ptw.resp.bits.s1.hit(miss_req_vpn, Mux(hasS2xlate, io.csr.vsatp.asid, io.csr.satp.asid), io.csr.hgatp.asid, allType = true, false, hasS2xlate) 317 val hit_s2 = io.ptw.resp.bits.s2.hit(miss_req_vpn, io.csr.hgatp.asid) 318 val hit = Mux(onlyS2, hit_s2, hit_s1) && io.ptw.resp.valid && miss_req_s2xlate_reg === io.ptw.resp.bits.s2xlate 319 320 val new_coming = RegNext(req_in(idx).fire && !req_in(idx).bits.kill && !flush_pipe(idx), false.B) 321 val miss_wire = new_coming && missVec(idx) 322 val miss_v = ValidHoldBypass(miss_wire, resp(idx).fire, flush_pipe(idx)) 323 val miss_req_v = ValidHoldBypass(miss_wire || (miss_v && flush_mmu && !mmu_flush_pipe), 324 io.ptw.req(idx).fire || resp(idx).fire, flush_pipe(idx)) 325 326 // when ptw resp, check if hit, reset miss_v, resp to lsu/ifu 327 resp(idx).valid := req_out_v(idx) && !(miss_v && portTranslateEnable(idx)) 328 when (io.ptw.resp.fire && hit && req_out_v(idx) && portTranslateEnable(idx)) { 329 val stage1 = io.ptw.resp.bits.s1 330 val stage2 = io.ptw.resp.bits.s2 331 val s2xlate = io.ptw.resp.bits.s2xlate 332 resp(idx).valid := true.B 333 resp(idx).bits.miss := false.B 334 val s1_paddr = Cat(stage1.genPPN(get_pn(req_out(idx).vaddr)), get_off(req_out(idx).vaddr)) 335 val s2_paddr = Cat(stage2.genPPNS2(get_pn(req_out(idx).vaddr)), get_off(req_out(idx).vaddr)) 336 for (d <- 0 until nRespDups) { 337 resp(idx).bits.paddr(d) := Mux(s2xlate =/= noS2xlate, s2_paddr, s1_paddr) 338 resp(idx).bits.gpaddr(d) := s1_paddr 339 perm_check(stage1, req_out(idx).cmd, idx, d, stage2, req_out(idx).hlvx, s2xlate) 340 } 341 pmp_check(resp(idx).bits.paddr(0), req_out(idx).size, req_out(idx).cmd, idx) 342 343 // NOTE: the unfiltered req would be handled by Repeater 344 } 345 assert(RegNext(!resp(idx).valid || resp(idx).ready, true.B), "when tlb resp valid, ready should be true, must") 346 assert(RegNext(req_out_v(idx) || !(miss_v || miss_req_v), true.B), "when not req_out_v, should not set miss_v/miss_req_v") 347 348 val ptw_req = io.ptw.req(idx) 349 ptw_req.valid := miss_req_v 350 ptw_req.bits.vpn := miss_req_vpn 351 ptw_req.bits.s2xlate := miss_req_s2xlate 352 ptw_req.bits.memidx := miss_req_memidx 353 354 io.tlbreplay(idx) := false.B 355 356 // NOTE: when flush pipe, tlb should abandon last req 357 // however, some outside modules like icache, dont care flushPipe, and still waiting for tlb resp 358 // just resp valid and raise page fault to go through. The pipe(ifu) will abandon it. 359 if (!q.outsideRecvFlush) { 360 when (req_out_v(idx) && flush_pipe(idx) && portTranslateEnable(idx)) { 361 resp(idx).valid := true.B 362 for (d <- 0 until nRespDups) { 363 resp(idx).bits.excp(d).pf.ld := true.B // sfence happened, pf for not to use this addr 364 resp(idx).bits.excp(d).pf.st := true.B 365 resp(idx).bits.excp(d).pf.instr := true.B 366 } 367 } 368 } 369 } 370 371 // when ptw resp, tlb at refill_idx maybe set to miss by force. 372 // Bypass ptw resp to check. 373 def ptw_resp_bypass(vpn: UInt, s2xlate: UInt) = { 374 val hasS2xlate = s2xlate =/= noS2xlate 375 val onlyS2 = s2xlate === onlyStage2 376 val onlyS1 = s2xlate === onlyStage1 377 val s2xlate_hit = s2xlate === ptw.resp.bits.s2xlate 378 val normal_hit = ptw.resp.bits.s1.hit(vpn, Mux(hasS2xlate, io.csr.vsatp.asid, io.csr.satp.asid), io.csr.hgatp.asid, true, false, hasS2xlate) 379 val onlyS2_hit = ptw.resp.bits.s2.hit(vpn, io.csr.hgatp.asid) 380 val p_hit = RegNext(Mux(onlyS2, onlyS2_hit, normal_hit) && io.ptw.resp.fire && s2xlate_hit) 381 val ppn_s1 = ptw.resp.bits.s1.genPPN(vpn) 382 val ppn_s2 = ptw.resp.bits.s2.genPPNS2(vpn) 383 val p_ppn = RegEnable(Mux(hasS2xlate, ppn_s2, ppn_s1), io.ptw.resp.fire) 384 val p_perm = RegEnable(ptwresp_to_tlbperm(ptw.resp.bits.s1), io.ptw.resp.fire) 385 val p_gvpn = RegEnable(Mux(onlyS1, Cat(ptw.resp.bits.s1.entry.tag, ptw.resp.bits.s1.ppn_low(OHToUInt(ptw.resp.bits.s1.pteidx))), ptw.resp.bits.s2.entry.tag), io.ptw.resp.fire) 386 val p_g_perm = RegEnable(hptwresp_to_tlbperm(ptw.resp.bits.s2), io.ptw.resp.fire) 387 val p_s2xlate = RegEnable(ptw.resp.bits.s2xlate, io.ptw.resp.fire) 388 (p_hit, p_ppn, p_perm, p_gvpn, p_g_perm, p_s2xlate) 389 } 390 391 // assert 392 for(i <- 0 until Width) { 393 TimeOutAssert(req_out_v(i) && !resp(i).valid, timeOutThreshold, s"{q.name} port{i} long time no resp valid.") 394 } 395 396 // perf event 397 val result_ok = req_in.map(a => RegNext(a.fire)) 398 val perfEvents = 399 Seq( 400 ("access", PopCount((0 until Width).map{i => if (Block(i)) io.requestor(i).req.fire else portTranslateEnable(i) && result_ok(i) })), 401 ("miss ", PopCount((0 until Width).map{i => if (Block(i)) portTranslateEnable(i) && result_ok(i) && missVec(i) else ptw.req(i).fire })), 402 ) 403 generatePerfEvent() 404 405 // perf log 406 for (i <- 0 until Width) { 407 if (Block(i)) { 408 XSPerfAccumulate(s"access${i}",result_ok(i) && portTranslateEnable(i)) 409 XSPerfAccumulate(s"miss${i}", result_ok(i) && missVec(i)) 410 } else { 411 XSPerfAccumulate("first_access" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i) && RegNext(req(i).bits.debug.isFirstIssue)) 412 XSPerfAccumulate("access" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i)) 413 XSPerfAccumulate("first_miss" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i) && missVec(i) && RegNext(req(i).bits.debug.isFirstIssue)) 414 XSPerfAccumulate("miss" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i) && missVec(i)) 415 } 416 } 417 XSPerfAccumulate("ptw_resp_count", ptw.resp.fire) 418 XSPerfAccumulate("ptw_resp_pf_count", ptw.resp.fire && ptw.resp.bits.s1.pf) 419 420 // Log 421 for(i <- 0 until Width) { 422 XSDebug(req(i).valid, p"req(${i.U}): (${req(i).valid} ${req(i).ready}) ${req(i).bits}\n") 423 XSDebug(resp(i).valid, p"resp(${i.U}): (${resp(i).valid} ${resp(i).ready}) ${resp(i).bits}\n") 424 } 425 426 XSDebug(io.sfence.valid, p"Sfence: ${io.sfence}\n") 427 XSDebug(ParallelOR(req_out_v) || ptw.resp.valid, p"vmEnable:${vmEnable} hit:${Binary(VecInit(hitVec).asUInt)} miss:${Binary(VecInit(missVec).asUInt)}\n") 428 for (i <- ptw.req.indices) { 429 XSDebug(ptw.req(i).fire, p"L2TLB req:${ptw.req(i).bits}\n") 430 } 431 XSDebug(ptw.resp.valid, p"L2TLB resp:${ptw.resp.bits} (v:${ptw.resp.valid}r:${ptw.resp.ready}) \n") 432 433 println(s"${q.name}: page: ${q.NWays} ${q.Associative} ${q.Replacer.get}") 434 435 if (env.EnableDifftest) { 436 for (i <- 0 until Width) { 437 val pf = io.requestor(i).resp.bits.excp(0).pf.instr || io.requestor(i).resp.bits.excp(0).pf.st || io.requestor(i).resp.bits.excp(0).pf.ld 438 val gpf = io.requestor(i).resp.bits.excp(0).gpf.instr || io.requestor(i).resp.bits.excp(0).gpf.st || io.requestor(i).resp.bits.excp(0).gpf.ld 439 val af = io.requestor(i).resp.bits.excp(0).af.instr || io.requestor(i).resp.bits.excp(0).af.st || io.requestor(i).resp.bits.excp(0).af.ld 440 val difftest = DifftestModule(new DiffL1TLBEvent) 441 difftest.coreid := io.hartId 442 difftest.valid := RegNext(io.requestor(i).req.fire) && !io.requestor(i).req_kill && io.requestor(i).resp.fire && !io.requestor(i).resp.bits.miss && !pf && !af && !gpf && portTranslateEnable(i) 443 if (!Seq("itlb", "ldtlb", "sttlb").contains(q.name)) { 444 difftest.valid := false.B 445 } 446 difftest.index := TLBDiffId(p(XSCoreParamsKey).HartId).U 447 difftest.satp := io.csr.satp 448 difftest.vpn := RegNext(get_pn(req_in(i).bits.vaddr)) 449 difftest.ppn := get_pn(io.requestor(i).resp.bits.paddr(0)) 450 difftest.satp := Cat(io.csr.satp.mode, io.csr.satp.asid, io.csr.satp.ppn) 451 difftest.vsatp := Cat(io.csr.vsatp.mode, io.csr.vsatp.asid, io.csr.vsatp.ppn) 452 difftest.hgatp := Cat(io.csr.hgatp.mode, io.csr.hgatp.asid, io.csr.hgatp.ppn) 453 val req_need_gpa = gpf 454 val req_s2xlate = Wire(UInt(2.W)) 455 req_s2xlate := MuxCase(noS2xlate, Seq( 456 (!(virt || RegNext(req_in(i).bits.hyperinst))) -> noS2xlate, 457 (vsatp.mode =/= 0.U && hgatp.mode =/= 0.U) -> allStage, 458 (vsatp.mode === 0.U) -> onlyStage2, 459 (hgatp.mode === 0.U || req_need_gpa) -> onlyStage1 460 )) 461 difftest.s2xlate := req_s2xlate 462 } 463 } 464} 465 466object TLBDiffId { 467 var i: Int = 0 468 var lastHartId: Int = -1 469 def apply(hartId: Int): Int = { 470 if (lastHartId != hartId) { 471 i = 0 472 lastHartId = hartId 473 } 474 i += 1 475 i - 1 476 } 477} 478 479class TLBNonBlock(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends TLB(Width, nRespDups, Seq.fill(Width)(false), q) 480class TLBBLock(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends TLB(Width, nRespDups, Seq.fill(Width)(true), q) 481 482class TlbReplace(Width: Int, q: TLBParameters)(implicit p: Parameters) extends TlbModule { 483 val io = IO(new TlbReplaceIO(Width, q)) 484 485 if (q.Associative == "fa") { 486 val re = ReplacementPolicy.fromString(q.Replacer, q.NWays) 487 re.access(io.page.access.map(_.touch_ways)) 488 io.page.refillIdx := re.way 489 } else { // set-acco && plru 490 val re = ReplacementPolicy.fromString(q.Replacer, q.NSets, q.NWays) 491 re.access(io.page.access.map(_.sets), io.page.access.map(_.touch_ways)) 492 io.page.refillIdx := { if (q.NWays == 1) 0.U else re.way(io.page.chosen_set) } 493 } 494} 495