fix(TLB): explicitly specify the signal width again when truncated (#4588)

Similar to https://github.com/OpenXiangShan/XiangShan/pull/4471

fix(TLB): onlyStage1 req should use s1_paddr rather than s2_paddr (#4587)

In the previous design, `s2_paddr` was used whenever virtualization was
enabled (`s2xlate =/= noS2xlate`). This was incorrec

fix(TLB): onlyStage1 req should use s1_paddr rather than s2_paddr (#4587)

In the previous design, `s2_paddr` was used whenever virtualization was
enabled (`s2xlate =/= noS2xlate`). This was incorrect — we should use
`s2_paddr` only when `onlyStage2` or `allStage` is active, and use
`s1_paddr` when in `onlyStage1` or `noS2xlate` mode. This commit fixes
that bug.

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Revert "fix(TLB): should always send onlyS1 req when req_need_gpa (#4… (#4551)

…513)"

This reverts commit 6d07e62cded1f9718c229f7c38d297fed2c95cb8.

At the same time, this commit also fixes a bug w

Revert "fix(TLB): should always send onlyS1 req when req_need_gpa (#4… (#4551)

…513)"

This reverts commit 6d07e62cded1f9718c229f7c38d297fed2c95cb8.

At the same time, this commit also fixes a bug where a onlyS1 request
was issued when `req_need_gpa` was active. In fact, even when
`req_need_gpa` is active, it is necessary to determine whether to issue
allStage, onlyS1, or onlyS2 based on the values of the vsatp or hgatp
registers. The previous approach in
https://github.com/OpenXiangShan/XiangShan/pull/4513 was incorrect, and
the details are as follows:

The process of two-stage address translation:

vaddr -> VS-L2 -> G-L2 -> G-L1 -> G-L0 (G-Stage for VS-Stage)
-> VS-L1 -> G-L2 -> G-L1 -> G-L0 (G-Stage for VS-Stage)
-> VS-L0 -> G-L2 -> G-L1 -> G-L0 (G-Stage for VS-Stage)
-> gpaddr -> G-L1 -> G-L0 -> paddr (last G-Stage)

When a page fault occurs at "G-Stage for VS-Stage" in the diagram, the
corresponding VS-Stage result before the arrow is the gpaddr value to be
written to the *tval register.

However, for example, the required gpaddr comes from VS-L0. Although the
first G-Stage query result for VS-L0 is not needed, it is clear that two
G-Stage requests are required before this, after VS-L2 and VS-L1, in
order to obtain the correct VS-L0 memory access address. If the L1 TLB
directly issues an onlyS1 request, then any G-Stage requests will be
ignored, which is unreasonable.

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fix(TLB): should always send onlyS1 req when req_need_gpa (#4513)

`req_need_gpa` indicates that the request needs to access the guest
physical address (GPA) where a GPF occurred by querying the L2 T

fix(TLB): should always send onlyS1 req when req_need_gpa (#4513)

`req_need_gpa` indicates that the request needs to access the guest
physical address (GPA) where a GPF occurred by querying the L2 TLB. When
`req_need_gpa` is valid, it is sufficient to send an onlyStage1 request
to obtain the guest physical address.

In the original design, multiple cases in the `MuxCase` could be valid
at the same time. For example, when both `csr.vsatp.mode =/= 0.U` and
`csr.hgatp.mode =/= 0.U` are valid, an allStage request would be sent
directly, without considering the `req_need_gpa` condition. This commit
fixes that bug.

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fix(TLB): explicitly specify the signal width when truncated (#4471)

Similar to https://github.com/OpenXiangShan/XiangShan/pull/4455, ppn_s1
has a width of 44 bits, ppn_s2 has a width of 38 bits, an

fix(TLB): explicitly specify the signal width when truncated (#4471)

Similar to https://github.com/OpenXiangShan/XiangShan/pull/4455, ppn_s1
has a width of 44 bits, ppn_s2 has a width of 38 bits, and both of them
need to finally assign to a 36-bits signal `ppn(d)`.

The original code does not result in a functional error, but the
designer should be aware of the bit-widths of these signals and whether
they can be directly truncated during assignment. Therefore this PR was
committed.

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fix(MMU): incorrect check for pre af/pf/gpf (#4358)

Pre af/pf/gpf means the exceptions before real translating, such as high
bits exception. There is some mistakes in choosing the translation mode,

fix(MMU): incorrect check for pre af/pf/gpf (#4358)

Pre af/pf/gpf means the exceptions before real translating, such as high
bits exception. There is some mistakes in choosing the translation mode,
which may causes problems in which different mode are used for Non-virt
S-stage and Virt VS-Stage.

This patch fixes the problems by smallest changes. There is too many
debts in L1TLB.

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fix(MMU): Unify latency in different CSR bundles (#4389)

In the previous design, since we don't flush pipeline after modifying
`satp`, we need to set whether or not increase the delay for different

fix(MMU): Unify latency in different CSR bundles (#4389)

In the previous design, since we don't flush pipeline after modifying
`satp`, we need to set whether or not increase the delay for different
signals in the csr bundle, such as priv and satp, respectively.

Currently, CSR will add send redirect signal to refresh the pipeline
after modifying `satp`, so we can unify latency in different CSR bundles
to fenceDelay.

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fix(TLB): onlyS1 scene should not consider G-stage access fault (#4266)

fix(TLB): avoid refill when one cycle before need_gpa (#3985)

In previous design, refill.valid will be false when `need_gpa` is true.
However, need_gpa is a reg so we add signal `need_gpa_wire` whi

fix(TLB): avoid refill when one cycle before need_gpa (#3985)

In previous design, refill.valid will be false when `need_gpa` is true.
However, need_gpa is a reg so we add signal `need_gpa_wire` which will
be true one cycle before need_gpa. refill.valid will be false either
need_gpa or need_gpa_wire is true.

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feat(pointer masking): support Ssnpm & Smnpm & Smmpm (#3921)

feat(pointer masking): support Ssnpm & Smnpm & Smmpm

fix(TLB): avoid freeze when GPF occurs (#3964)

L1TLB does not store gpaddr, but gpaddr is needed when a guest page
fault occurs. In that situation, L1TLB needs to send a PTW request to
get the gpa

fix(TLB): avoid freeze when GPF occurs (#3964)

L1TLB does not store gpaddr, but gpaddr is needed when a guest page
fault occurs. In that situation, L1TLB needs to send a PTW request to
get the gpaddr, which we called it getGpa. The getGpa mechanism could
only handle one GPF TLB request (the first one) and expects the
corresponding TLB entry is still in L1TLB.

L1TLB replacement uses PLRU (Pseudo-LRU) algorithm, which may replace
intems that are not necessarily the least recently used. We found an
case that L1TLB replace that GPF TLB entry, although that GPF TLB entry
is accessed recently. This results in a deadlock in getGpa mechanism,
which eventually causes the entire core to freeze. To solve this
problem, we decides to prevent any unrelated ptw refills when getGpa
mechanism is working (need_gpa).

After solve such problem, we identified that under certain conditions,
as other PTW response is never refilled, other TLB requests keep
replying which trigger PTW requests and occupy the L2TLB request path,
preventing the GPF PTW request from responding, ultimately leading to a
processor freeze. To resolve this, we decides to prevent any unrelated
ptw request when need_gpa.

This patch also changes the code style of some combinational logic
signals. Using when/otherwise is clearer and easier to understand than
complex logical expression.

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docs: add acknowledgements (#3861)

fix(TLB): incorrect tval2 info when IGPF occurs (#3871)

In PR #3822, the gpaddr generating logic is modified for cross-page
handleing. But that modification doesn't consider that the fullva of
iTL

fix(TLB): incorrect tval2 info when IGPF occurs (#3871)

In PR #3822, the gpaddr generating logic is modified for cross-page
handleing. But that modification doesn't consider that the fullva of
iTLB is always zero and should not be used, which causes the wrong
htval/mtval2 when instruction guest page fault occurs. This patch fixes
this.

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fix(misalign): fix gpaddr of misalign loads when onlyStage2 (#3822)

For onlyStage2 situations, gpaddr is equal to vaddr. Therefore, for
cross-page requests, we need to pass gpaddr out correctly (se

fix(misalign): fix gpaddr of misalign loads when onlyStage2 (#3822)

For onlyStage2 situations, gpaddr is equal to vaddr. Therefore, for
cross-page requests, we need to pass gpaddr out correctly (see comments)
Also, in previous design, we would set gpaddr offset to all zero when
cross-page in loadmisalign buffer. This has been removed and all gpaddrs
are generated in tlb.

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fix(misalign): Should use offset of original vaddr to generate gpaddr

For example, a `ld` instruction on address 0x81000ffb will be splited into two loads:
1. ld 0x81000ff8. vaddr = 0x81000ff8, full

fix(misalign): Should use offset of original vaddr to generate gpaddr

For example, a `ld` instruction on address 0x81000ffb will be splited into two loads:
1. ld 0x81000ff8. vaddr = 0x81000ff8, fullva = 0x80000ffb
2. ld 0x81001000. vaddr = 0x81001000, fullva = 0x80000ffb

When load 1 trigger a guest page fault, we should use offset of original vaddr to generate gpaddr in TLB, and and when load 2 trigger a guest page fault, we should just use offset of after-splitted vaddr(all zero) in misalignbuffer.

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fix(PTW, RVH): modify the logic of checking high bits of gpaddr (#3679)

- In PTW, use a reg to store gvpn to check the high bits.
- The len of gvpn(wire type) is wrong. It should be ptePPNLen.

fix(pbmt): fix assignment bug in tlb (#3770)

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condi

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condition is
not satisfied for prefetch and redirected requests, resulting in stuck.
This commit fixes this bug.

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fix(tlb): overwrite resp information when high address exception happens (#3674)

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retain

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retained. And for exceptions detected after address translation, the
48-bit vaddr needs to be zero-extended or sign-extended according to
different modes(`GenExceptionVa`), and then write to *tval.

Also fix some connection bugs.

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fix(TLB): fix exception judgement condition (#3629)

A TLB query requires two cycles, the first (s0) to receive the req and
the second (s1) to return the result. pre exception checking will be
done

fix(TLB): fix exception judgement condition (#3629)

A TLB query requires two cycles, the first (s0) to receive the req and
the second (s1) to return the result. pre exception checking will be
done on the first cycle, so should use `vmenable` and `s2xlateEnable` of
the first cycle.

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feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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chore(MMU): Remove timeout assertion (#3603)

With CHI enabled and CMN connected, a transaction may last over
timeoutThreshold. So this commit removes it (also since L2 Cache will
detect timeout)

fix(TLB, RVH): fix the bug that pf happens because s1 is nonleaf (#3580)