xref: /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala (revision ca2f90a69ce970d90edc8b017b309154608dfe8c)
16d5ddbceSLemover/***************************************************************************************
26d5ddbceSLemover* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3f320e0f0SYinan Xu* Copyright (c) 2020-2021 Peng Cheng Laboratory
46d5ddbceSLemover*
56d5ddbceSLemover* XiangShan is licensed under Mulan PSL v2.
66d5ddbceSLemover* You can use this software according to the terms and conditions of the Mulan PSL v2.
76d5ddbceSLemover* You may obtain a copy of Mulan PSL v2 at:
86d5ddbceSLemover*          http://license.coscl.org.cn/MulanPSL2
96d5ddbceSLemover*
106d5ddbceSLemover* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
116d5ddbceSLemover* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
126d5ddbceSLemover* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
136d5ddbceSLemover*
146d5ddbceSLemover* See the Mulan PSL v2 for more details.
156d5ddbceSLemover***************************************************************************************/
166d5ddbceSLemover
176d5ddbceSLemoverpackage xiangshan.cache.mmu
186d5ddbceSLemover
196d5ddbceSLemoverimport chipsalliance.rocketchip.config.Parameters
206d5ddbceSLemoverimport chisel3._
21a0301c0dSLemoverimport chisel3.internal.naming.chiselName
226d5ddbceSLemoverimport chisel3.util._
23a0301c0dSLemoverimport freechips.rocketchip.util.SRAMAnnotation
246d5ddbceSLemoverimport xiangshan._
256d5ddbceSLemoverimport utils._
26b6982e83SLemoverimport xiangshan.backend.fu.{PMPChecker, PMPReqBundle}
279aca92b9SYinan Xuimport xiangshan.backend.rob.RobPtr
286d5ddbceSLemoverimport xiangshan.backend.fu.util.HasCSRConst
296d5ddbceSLemover
30a0301c0dSLemover
31a0301c0dSLemover@chiselName
32a0301c0dSLemoverclass TLB(Width: Int, q: TLBParameters)(implicit p: Parameters) extends TlbModule with HasCSRConst {
33a0301c0dSLemover  val io = IO(new TlbIO(Width, q))
34a0301c0dSLemover
35a0301c0dSLemover  require(q.superAssociative == "fa")
36a0301c0dSLemover  if (q.sameCycle) {
37a0301c0dSLemover    require(q.normalAssociative == "fa")
38a0301c0dSLemover  }
396d5ddbceSLemover
406d5ddbceSLemover  val req = io.requestor.map(_.req)
416d5ddbceSLemover  val resp = io.requestor.map(_.resp)
426d5ddbceSLemover  val ptw = io.ptw
43b6982e83SLemover  val pmp = io.pmp
446d5ddbceSLemover
456d5ddbceSLemover  val sfence = io.sfence
466d5ddbceSLemover  val csr = io.csr
476d5ddbceSLemover  val satp = csr.satp
486d5ddbceSLemover  val priv = csr.priv
49a0301c0dSLemover  val ifecth = if (q.fetchi) true.B else false.B
50a0301c0dSLemover  val mode = if (q.useDmode) priv.dmode else priv.imode
516d5ddbceSLemover  // val vmEnable = satp.mode === 8.U // && (mode < ModeM) // FIXME: fix me when boot xv6/linux...
526d5ddbceSLemover  val vmEnable = if (EnbaleTlbDebug) (satp.mode === 8.U)
536d5ddbceSLemover  else (satp.mode === 8.U && (mode < ModeM))
546d5ddbceSLemover
55a0301c0dSLemover  val reqAddr = req.map(_.bits.vaddr.asTypeOf((new VaBundle).cloneType))
56a0301c0dSLemover  val vpn = reqAddr.map(_.vpn)
576d5ddbceSLemover  val cmd = req.map(_.bits.cmd)
586d5ddbceSLemover  val valid = req.map(_.valid)
596d5ddbceSLemover
606d5ddbceSLemover  def widthMapSeq[T <: Seq[Data]](f: Int => T) = (0 until Width).map(f)
61a0301c0dSLemover
626d5ddbceSLemover  def widthMap[T <: Data](f: Int => T) = (0 until Width).map(f)
636d5ddbceSLemover
646d5ddbceSLemover  // Normal page && Super page
65a0301c0dSLemover  val normalPage = TlbStorage(
66a0301c0dSLemover    name = "normal",
67a0301c0dSLemover    associative = q.normalAssociative,
68a0301c0dSLemover    sameCycle = q.sameCycle,
69a0301c0dSLemover    ports = Width,
70a0301c0dSLemover    nSets = q.normalNSets,
71a0301c0dSLemover    nWays = q.normalNWays,
72a0301c0dSLemover    sramSinglePort = sramSinglePort,
73a0301c0dSLemover    normalPage = true,
74a0301c0dSLemover    superPage = false
756d5ddbceSLemover  )
76a0301c0dSLemover  val superPage = TlbStorage(
77a0301c0dSLemover    name = "super",
78a0301c0dSLemover    associative = q.superAssociative,
79a0301c0dSLemover    sameCycle = q.sameCycle,
80a0301c0dSLemover    ports = Width,
81a0301c0dSLemover    nSets = q.superNSets,
82a0301c0dSLemover    nWays = q.superNWays,
83a0301c0dSLemover    sramSinglePort = sramSinglePort,
84a0301c0dSLemover    normalPage = q.normalAsVictim,
85a0301c0dSLemover    superPage = true,
866d5ddbceSLemover  )
876d5ddbceSLemover
88a0301c0dSLemover
896d5ddbceSLemover  for (i <- 0 until Width) {
90a0301c0dSLemover    normalPage.r_req_apply(
91a0301c0dSLemover      valid = io.requestor(i).req.valid,
92a0301c0dSLemover      vpn = vpn(i),
9345f497a4Shappy-lx      asid = csr.satp.asid,
94a0301c0dSLemover      i = i
956d5ddbceSLemover    )
96a0301c0dSLemover    superPage.r_req_apply(
97a0301c0dSLemover      valid = io.requestor(i).req.valid,
98a0301c0dSLemover      vpn = vpn(i),
9945f497a4Shappy-lx      asid = csr.satp.asid,
100a0301c0dSLemover      i = i
101a0301c0dSLemover    )
102a0301c0dSLemover  }
1036d5ddbceSLemover
104a0301c0dSLemover  normalPage.victim.in <> superPage.victim.out
105a0301c0dSLemover  normalPage.victim.out <> superPage.victim.in
106a0301c0dSLemover  normalPage.sfence <> io.sfence
107a0301c0dSLemover  superPage.sfence <> io.sfence
10845f497a4Shappy-lx  normalPage.csr <> io.csr
10945f497a4Shappy-lx  superPage.csr <> io.csr
110149086eaSLemover
111a0301c0dSLemover  def TLBNormalRead(i: Int) = {
1123889e11eSLemover    val (normal_hit, normal_ppn, normal_perm) = normalPage.r_resp_apply(i)
1133889e11eSLemover    val (super_hit, super_ppn, super_perm) = superPage.r_resp_apply(i)
114a0301c0dSLemover    assert(!(normal_hit && super_hit && vmEnable && RegNext(req(i).valid, init = false.B)))
1156d5ddbceSLemover
116a0301c0dSLemover    val hit = normal_hit || super_hit
117a0301c0dSLemover    val ppn = Mux(normal_hit, normal_ppn, super_ppn)
118a0301c0dSLemover    val perm = Mux(normal_hit, normal_perm, super_perm)
119a0301c0dSLemover
120a0301c0dSLemover    val pf = perm.pf && hit
121b6982e83SLemover    val af = perm.af && hit
122a0301c0dSLemover    val cmdReg = if (!q.sameCycle) RegNext(cmd(i)) else cmd(i)
123a0301c0dSLemover    val validReg = if (!q.sameCycle) RegNext(valid(i)) else valid(i)
124a0301c0dSLemover    val offReg = if (!q.sameCycle) RegNext(reqAddr(i).off) else reqAddr(i).off
125b6982e83SLemover    val sizeReg = if (!q.sameCycle) RegNext(req(i).bits.size) else req(i).bits.size
126a0301c0dSLemover
127a0301c0dSLemover    /** *************** next cycle when two cycle is false******************* */
128a0301c0dSLemover    val miss = !hit && vmEnable
1296d5ddbceSLemover    hit.suggestName(s"hit_${i}")
1306d5ddbceSLemover    miss.suggestName(s"miss_${i}")
1316d5ddbceSLemover
132a0301c0dSLemover    XSDebug(validReg, p"(${i.U}) hit:${hit} miss:${miss} ppn:${Hexadecimal(ppn)} perm:${perm}\n")
1336d5ddbceSLemover
134a0301c0dSLemover    val paddr = Cat(ppn, offReg)
1356d5ddbceSLemover    val vaddr = SignExt(req(i).bits.vaddr, PAddrBits)
1366d5ddbceSLemover
1376d5ddbceSLemover    req(i).ready := resp(i).ready
1386d5ddbceSLemover    resp(i).valid := validReg
139a0301c0dSLemover    resp(i).bits.paddr := Mux(vmEnable, paddr, if (!q.sameCycle) RegNext(vaddr) else vaddr)
1406d5ddbceSLemover    resp(i).bits.miss := miss
1416d5ddbceSLemover    resp(i).bits.ptwBack := io.ptw.resp.fire()
1426d5ddbceSLemover
143b6982e83SLemover    pmp(i).valid := resp(i).valid
144b6982e83SLemover    pmp(i).bits.addr := resp(i).bits.paddr
145b6982e83SLemover    pmp(i).bits.size := sizeReg
146b6982e83SLemover    pmp(i).bits.cmd := cmdReg
147b6982e83SLemover
148a79fef67Swakafa    val ldUpdate = hit && !perm.a && TlbCmd.isRead(cmdReg) && !TlbCmd.isAmo(cmdReg) // update A/D through exception
149a79fef67Swakafa    val stUpdate = hit && (!perm.a || !perm.d) && (TlbCmd.isWrite(cmdReg) || TlbCmd.isAmo(cmdReg)) // update A/D through exception
150a79fef67Swakafa    val instrUpdate = hit && !perm.a && TlbCmd.isExec(cmdReg) // update A/D through exception
1516d5ddbceSLemover    val modeCheck = !(mode === ModeU && !perm.u || mode === ModeS && perm.u && (!priv.sum || ifecth))
152a79fef67Swakafa    val ldPermFail = !(modeCheck && (perm.r || priv.mxr && perm.x))
153a79fef67Swakafa    val stPermFail = !(modeCheck && perm.w)
154a79fef67Swakafa    val instrPermFail = !(modeCheck && perm.x)
155a79fef67Swakafa    val ldPf = (ldPermFail || pf) && (TlbCmd.isRead(cmdReg) && !TlbCmd.isAmo(cmdReg))
156a79fef67Swakafa    val stPf = (stPermFail || pf) && (TlbCmd.isWrite(cmdReg) || TlbCmd.isAmo(cmdReg))
157*ca2f90a6SLemover    val fault_valid = vmEnable && hit
158a79fef67Swakafa    val instrPf = (instrPermFail || pf) && TlbCmd.isExec(cmdReg)
159*ca2f90a6SLemover    resp(i).bits.excp.pf.ld := (ldPf || ldUpdate) && fault_valid && !af
160*ca2f90a6SLemover    resp(i).bits.excp.pf.st := (stPf || stUpdate) && fault_valid && !af
161*ca2f90a6SLemover    resp(i).bits.excp.pf.instr := (instrPf || instrUpdate) && fault_valid && !af
162b6982e83SLemover    // NOTE: pf need && with !af, page fault has higher priority than access fault
163b6982e83SLemover    // but ptw may also have access fault, then af happens, the translation is wrong.
164b6982e83SLemover    // In this case, pf has lower priority than af
1656d5ddbceSLemover
166*ca2f90a6SLemover    resp(i).bits.excp.af.ld := af && TlbCmd.isRead(cmdReg) && fault_valid
167*ca2f90a6SLemover    resp(i).bits.excp.af.st := af && TlbCmd.isWrite(cmdReg) && fault_valid
168*ca2f90a6SLemover    resp(i).bits.excp.af.instr := af && TlbCmd.isExec(cmdReg) && fault_valid
1696d5ddbceSLemover
1703889e11eSLemover    (hit, miss, validReg)
1716d5ddbceSLemover  }
1726d5ddbceSLemover
1736d5ddbceSLemover  val readResult = (0 until Width).map(TLBNormalRead(_))
174a0301c0dSLemover  val hitVec = readResult.map(_._1)
175a0301c0dSLemover  val missVec = readResult.map(_._2)
1763889e11eSLemover  val validRegVec = readResult.map(_._3)
1776d5ddbceSLemover
178149086eaSLemover  // replacement
179a0301c0dSLemover  def get_access(one_hot: UInt, valid: Bool): Valid[UInt] = {
180149086eaSLemover    val res = Wire(Valid(UInt(log2Up(one_hot.getWidth).W)))
181a0301c0dSLemover    res.valid := Cat(one_hot).orR && valid
182149086eaSLemover    res.bits := OHToUInt(one_hot)
183149086eaSLemover    res
184149086eaSLemover  }
185a0301c0dSLemover
186a0301c0dSLemover  val normal_refill_idx = if (q.outReplace) {
1873889e11eSLemover    io.replace.normalPage.access <> normalPage.access
1883889e11eSLemover    io.replace.normalPage.chosen_set := get_set_idx(io.ptw.resp.bits.entry.tag, q.normalNSets)
189a0301c0dSLemover    io.replace.normalPage.refillIdx
190a0301c0dSLemover  } else if (q.normalAssociative == "fa") {
191a0301c0dSLemover    val re = ReplacementPolicy.fromString(q.normalReplacer, q.normalNWays)
1923889e11eSLemover    re.access(normalPage.access.map(_.touch_ways)) // normalhitVecVec.zipWithIndex.map{ case (hv, i) => get_access(hv, validRegVec(i))})
193a0301c0dSLemover    re.way
194a0301c0dSLemover  } else { // set-acco && plru
195a0301c0dSLemover    val re = ReplacementPolicy.fromString(q.normalReplacer, q.normalNSets, q.normalNWays)
1963889e11eSLemover    re.access(normalPage.access.map(_.sets), normalPage.access.map(_.touch_ways))
1973889e11eSLemover    re.way(get_set_idx(io.ptw.resp.bits.entry.tag, q.normalNSets))
198149086eaSLemover  }
199a0301c0dSLemover
200a0301c0dSLemover  val super_refill_idx = if (q.outReplace) {
2013889e11eSLemover    io.replace.superPage.access <> superPage.access
202a0301c0dSLemover    io.replace.superPage.chosen_set := DontCare
203a0301c0dSLemover    io.replace.superPage.refillIdx
204149086eaSLemover  } else {
205a0301c0dSLemover    val re = ReplacementPolicy.fromString(q.superReplacer, q.superNWays)
2063889e11eSLemover    re.access(superPage.access.map(_.touch_ways))
207a0301c0dSLemover    re.way
208149086eaSLemover  }
209149086eaSLemover
21045f497a4Shappy-lx  val refill = ptw.resp.fire() && !sfence.valid && !satp.changed
211a0301c0dSLemover  normalPage.w_apply(
212a0301c0dSLemover    valid = { if (q.normalAsVictim) false.B
213a0301c0dSLemover    else refill && ptw.resp.bits.entry.level.get === 2.U },
214a0301c0dSLemover    wayIdx = normal_refill_idx,
215a0301c0dSLemover    data = ptw.resp.bits
216a0301c0dSLemover  )
217a0301c0dSLemover  superPage.w_apply(
218a0301c0dSLemover    valid = { if (q.normalAsVictim) refill
219a0301c0dSLemover    else refill && ptw.resp.bits.entry.level.get =/= 2.U },
220a0301c0dSLemover    wayIdx = super_refill_idx,
221a0301c0dSLemover    data = ptw.resp.bits
222a0301c0dSLemover  )
223a0301c0dSLemover
2246d5ddbceSLemover  for (i <- 0 until Width) {
2256d5ddbceSLemover    io.ptw.req(i).valid := validRegVec(i) && missVec(i) && !RegNext(refill)
2266d5ddbceSLemover    io.ptw.req(i).bits.vpn := RegNext(reqAddr(i).vpn)
2276d5ddbceSLemover  }
2286d5ddbceSLemover  io.ptw.resp.ready := true.B
2296d5ddbceSLemover
230a0301c0dSLemover  if (!q.shouldBlock) {
2316d5ddbceSLemover    for (i <- 0 until Width) {
2326d5ddbceSLemover      XSPerfAccumulate("first_access" + Integer.toString(i, 10), validRegVec(i) && vmEnable && RegNext(req(i).bits.debug.isFirstIssue))
2336d5ddbceSLemover      XSPerfAccumulate("access" + Integer.toString(i, 10), validRegVec(i) && vmEnable)
2346d5ddbceSLemover    }
2356d5ddbceSLemover    for (i <- 0 until Width) {
2366d5ddbceSLemover      XSPerfAccumulate("first_miss" + Integer.toString(i, 10), validRegVec(i) && vmEnable && missVec(i) && RegNext(req(i).bits.debug.isFirstIssue))
2376d5ddbceSLemover      XSPerfAccumulate("miss" + Integer.toString(i, 10), validRegVec(i) && vmEnable && missVec(i))
2386d5ddbceSLemover    }
2396d5ddbceSLemover  } else {
2406d5ddbceSLemover    // NOTE: ITLB is blocked, so every resp will be valid only when hit
2416d5ddbceSLemover    // every req will be ready only when hit
242a0301c0dSLemover    for (i <- 0 until Width) {
243a0301c0dSLemover      XSPerfAccumulate(s"access${i}", io.requestor(i).req.fire() && vmEnable)
244a0301c0dSLemover      XSPerfAccumulate(s"miss${i}", ptw.req(i).fire())
245a0301c0dSLemover    }
246a0301c0dSLemover
2476d5ddbceSLemover  }
2486d5ddbceSLemover  //val reqCycleCnt = Reg(UInt(16.W))
2496d5ddbceSLemover  //reqCycleCnt := reqCycleCnt + BoolStopWatch(ptw.req(0).fire(), ptw.resp.fire || sfence.valid)
2506d5ddbceSLemover  //XSPerfAccumulate("ptw_req_count", ptw.req.fire())
2516d5ddbceSLemover  //XSPerfAccumulate("ptw_req_cycle", Mux(ptw.resp.fire(), reqCycleCnt, 0.U))
2526d5ddbceSLemover  XSPerfAccumulate("ptw_resp_count", ptw.resp.fire())
2536d5ddbceSLemover  XSPerfAccumulate("ptw_resp_pf_count", ptw.resp.fire() && ptw.resp.bits.pf)
2546d5ddbceSLemover
2556d5ddbceSLemover  // Log
2566d5ddbceSLemover  for(i <- 0 until Width) {
2576d5ddbceSLemover    XSDebug(req(i).valid, p"req(${i.U}): (${req(i).valid} ${req(i).ready}) ${req(i).bits}\n")
2586d5ddbceSLemover    XSDebug(resp(i).valid, p"resp(${i.U}): (${resp(i).valid} ${resp(i).ready}) ${resp(i).bits}\n")
2596d5ddbceSLemover  }
2606d5ddbceSLemover
2616d5ddbceSLemover  XSDebug(sfence.valid, p"Sfence: ${sfence}\n")
2626d5ddbceSLemover  XSDebug(ParallelOR(valid)|| ptw.resp.valid, p"CSR: ${csr}\n")
263a0301c0dSLemover  XSDebug(ParallelOR(valid) || ptw.resp.valid, p"vmEnable:${vmEnable} hit:${Binary(VecInit(hitVec).asUInt)} miss:${Binary(VecInit(missVec).asUInt)}\n")
2646d5ddbceSLemover  for (i <- ptw.req.indices) {
2656d5ddbceSLemover    XSDebug(ptw.req(i).fire(), p"PTW req:${ptw.req(i).bits}\n")
2666d5ddbceSLemover  }
2676d5ddbceSLemover  XSDebug(ptw.resp.valid, p"PTW resp:${ptw.resp.bits} (v:${ptw.resp.valid}r:${ptw.resp.ready}) \n")
2686d5ddbceSLemover
269a0301c0dSLemover  println(s"${q.name}: normal page: ${q.normalNWays} ${q.normalAssociative} ${q.normalReplacer.get} super page: ${q.superNWays} ${q.superAssociative} ${q.superReplacer.get}")
270a0301c0dSLemover
2716d5ddbceSLemover//   // NOTE: just for simple tlb debug, comment it after tlb's debug
2726d5ddbceSLemover  // assert(!io.ptw.resp.valid || io.ptw.resp.bits.entry.tag === io.ptw.resp.bits.entry.ppn, "Simple tlb debug requires vpn === ppn")
273cd365d4cSrvcoresjw  val perfinfo = IO(new Bundle(){
274cd365d4cSrvcoresjw    val perfEvents = Output(new PerfEventsBundle(2))
275cd365d4cSrvcoresjw  })
276cd365d4cSrvcoresjw    if(!q.shouldBlock) {
277cd365d4cSrvcoresjw      val perfEvents = Seq(
278cd365d4cSrvcoresjw        ("access         ", PopCount((0 until Width).map(i => vmEnable && validRegVec(i)))                                         ),
279cd365d4cSrvcoresjw        ("miss           ", PopCount((0 until Width).map(i => vmEnable && validRegVec(i) && missVec(i)))                           ),
280cd365d4cSrvcoresjw        )
281cd365d4cSrvcoresjw      for (((perf_out,(perf_name,perf)),i) <- perfinfo.perfEvents.perf_events.zip(perfEvents).zipWithIndex) {
282cd365d4cSrvcoresjw        perf_out.incr_step := RegNext(perf)
283cd365d4cSrvcoresjw      }
284cd365d4cSrvcoresjw    } else {
285cd365d4cSrvcoresjw      val perfEvents = Seq(
286cd365d4cSrvcoresjw        ("access         ", PopCount((0 until Width).map(i => io.requestor(i).req.fire()))                           ),
287cd365d4cSrvcoresjw        ("miss           ", PopCount((0 until Width).map(i => ptw.req(i).fire()))                                    ),
288cd365d4cSrvcoresjw      )
289cd365d4cSrvcoresjw      for (((perf_out,(perf_name,perf)),i) <- perfinfo.perfEvents.perf_events.zip(perfEvents).zipWithIndex) {
290cd365d4cSrvcoresjw        perf_out.incr_step := RegNext(perf)
291cd365d4cSrvcoresjw      }
292cd365d4cSrvcoresjw    }
2936d5ddbceSLemover}
2946d5ddbceSLemover
295a0301c0dSLemoverclass TlbReplace(Width: Int, q: TLBParameters)(implicit p: Parameters) extends TlbModule {
296a0301c0dSLemover  val io = IO(new TlbReplaceIO(Width, q))
297a0301c0dSLemover
298a0301c0dSLemover  if (q.normalAssociative == "fa") {
299a0301c0dSLemover    val re = ReplacementPolicy.fromString(q.normalReplacer, q.normalNWays)
3003889e11eSLemover    re.access(io.normalPage.access.map(_.touch_ways))
301a0301c0dSLemover    io.normalPage.refillIdx := re.way
302a0301c0dSLemover  } else { // set-acco && plru
303a0301c0dSLemover    val re = ReplacementPolicy.fromString(q.normalReplacer, q.normalNSets, q.normalNWays)
3043889e11eSLemover    re.access(io.normalPage.access.map(_.sets), io.normalPage.access.map(_.touch_ways))
305a0301c0dSLemover    io.normalPage.refillIdx := { if (q.normalNWays == 1) 0.U else re.way(io.normalPage.chosen_set) }
306a0301c0dSLemover  }
307a0301c0dSLemover
308a0301c0dSLemover  if (q.superAssociative == "fa") {
309a0301c0dSLemover    val re = ReplacementPolicy.fromString(q.superReplacer, q.superNWays)
3103889e11eSLemover    re.access(io.superPage.access.map(_.touch_ways))
311a0301c0dSLemover    io.superPage.refillIdx := re.way
312a0301c0dSLemover  } else { // set-acco && plru
313a0301c0dSLemover    val re = ReplacementPolicy.fromString(q.superReplacer, q.superNSets, q.superNWays)
3143889e11eSLemover    re.access(io.superPage.access.map(_.sets), io.superPage.access.map(_.touch_ways))
315a0301c0dSLemover    io.superPage.refillIdx := { if (q.superNWays == 1) 0.U else re.way(io.superPage.chosen_set) }
316a0301c0dSLemover  }
317a0301c0dSLemover}
318a0301c0dSLemover
3196d5ddbceSLemoverobject TLB {
3206d5ddbceSLemover  def apply
3216d5ddbceSLemover  (
3226d5ddbceSLemover    in: Seq[BlockTlbRequestIO],
3236d5ddbceSLemover    sfence: SfenceBundle,
3246d5ddbceSLemover    csr: TlbCsrBundle,
3256d5ddbceSLemover    width: Int,
326a0301c0dSLemover    shouldBlock: Boolean,
327a0301c0dSLemover    q: TLBParameters
3286d5ddbceSLemover  )(implicit p: Parameters) = {
3296d5ddbceSLemover    require(in.length == width)
3306d5ddbceSLemover
331a0301c0dSLemover    val tlb = Module(new TLB(width, q))
3326d5ddbceSLemover
3336d5ddbceSLemover    tlb.io.sfence <> sfence
3346d5ddbceSLemover    tlb.io.csr <> csr
335a0301c0dSLemover    tlb.suggestName(s"tlb_${q.name}")
3366d5ddbceSLemover
3376d5ddbceSLemover    if (!shouldBlock) { // dtlb
3386d5ddbceSLemover      for (i <- 0 until width) {
3396d5ddbceSLemover        tlb.io.requestor(i) <> in(i)
3406d5ddbceSLemover        // tlb.io.requestor(i).req.valid := in(i).req.valid
3416d5ddbceSLemover        // tlb.io.requestor(i).req.bits := in(i).req.bits
3426d5ddbceSLemover        // in(i).req.ready := tlb.io.requestor(i).req.ready
3436d5ddbceSLemover
3446d5ddbceSLemover        // in(i).resp.valid := tlb.io.requestor(i).resp.valid
3456d5ddbceSLemover        // in(i).resp.bits := tlb.io.requestor(i).resp.bits
3466d5ddbceSLemover        // tlb.io.requestor(i).resp.ready := in(i).resp.ready
3476d5ddbceSLemover      }
3486d5ddbceSLemover    } else { // itlb
349d57bda64SJinYue      //require(width == 1)
350d57bda64SJinYue      (0 until width).map{ i =>
351d57bda64SJinYue        tlb.io.requestor(i).req.valid := in(i).req.valid
352d57bda64SJinYue        tlb.io.requestor(i).req.bits := in(i).req.bits
353d57bda64SJinYue        in(i).req.ready := !tlb.io.requestor(i).resp.bits.miss && in(i).resp.ready && tlb.io.requestor(i).req.ready
3546d5ddbceSLemover
355d57bda64SJinYue        in(i).resp.valid := tlb.io.requestor(i).resp.valid && !tlb.io.requestor(i).resp.bits.miss
356d57bda64SJinYue        in(i).resp.bits := tlb.io.requestor(i).resp.bits
357d57bda64SJinYue        tlb.io.requestor(i).resp.ready := in(i).resp.ready
358d57bda64SJinYue      }
3596d5ddbceSLemover    }
3606d5ddbceSLemover    tlb.io.ptw
3616d5ddbceSLemover  }
3626d5ddbceSLemover}
363