1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import chisel3.internal.naming.chiselName 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 27import freechips.rocketchip.tilelink._ 28 29/* ptw cache caches the page table of all the three layers 30 * ptw cache resp at next cycle 31 * the cache should not be blocked 32 * when miss queue if full, just block req outside 33 */ 34class PtwCacheIO()(implicit p: Parameters) extends PtwBundle { 35 val req = Flipped(DecoupledIO(new Bundle { 36 val vpn = UInt(vpnLen.W) 37 val source = UInt(bSourceWidth.W) 38 })) 39 val req_isFirst = Input(Bool()) // only for perf counter 40 val resp = DecoupledIO(new Bundle { 41 val source = UInt(bSourceWidth.W) 42 val vpn = UInt(vpnLen.W) 43 val hit = Bool() 44 val prefetch = Bool() // is the entry fetched by prefetch 45 val toFsm = new Bundle { 46 val l1Hit = Bool() 47 val l2Hit = Bool() 48 val ppn = UInt(ppnLen.W) 49 } 50 val toTlb = new PtwEntry(tagLen = vpnLen, hasPerm = true, hasLevel = true) 51 }) 52 val refill = Flipped(ValidIO(new Bundle { 53 val ptes = UInt(blockBits.W) 54 val vpn = UInt(vpnLen.W) 55 val level = UInt(log2Up(Level).W) 56 val prefetch = Bool() // is the req a prefetch req 57 val addr_low = UInt((log2Up(l2tlbParams.blockBytes) - log2Up(XLEN/8)).W) 58 })) 59 val sfence = Input(new SfenceBundle) 60} 61 62 63@chiselName 64class PtwCache()(implicit p: Parameters) extends XSModule with HasPtwConst { 65 val io = IO(new PtwCacheIO) 66 67 val ecc = Code.fromString(l2tlbParams.ecc) 68 val l2EntryType = new PTWEntriesWithEcc(ecc, num = PtwL2SectorSize, tagLen = PtwL2TagLen, level = 1, hasPerm = false) 69 val l3EntryType = new PTWEntriesWithEcc(ecc, num = PtwL3SectorSize, tagLen = PtwL3TagLen, level = 2, hasPerm = true) 70 71 // TODO: four caches make the codes dirty, think about how to deal with it 72 73 val sfence = io.sfence 74 val refill = io.refill.bits 75 76 val first_valid = io.req.valid 77 val first_fire = first_valid && io.req.ready 78 val first_req = io.req.bits 79 val second_ready = Wire(Bool()) 80 val second_valid = ValidHold(first_fire && !sfence.valid, io.resp.fire(), sfence.valid) 81 val second_req = RegEnable(first_req, first_fire) 82 // NOTE: if ptw cache resp may be blocked, hard to handle refill 83 // when miss queue is full, please to block itlb and dtlb input 84 val second_isFirst = RegEnable(io.req_isFirst, first_fire) // only for perf counter 85 86 // when refill, refuce to accept new req 87 val rwHarzad = if (sramSinglePort) io.refill.valid else false.B 88 io.req.ready := !rwHarzad && second_ready 89 // NOTE: when write, don't ready, whe 90 // when replay, just come in, out make sure resp.fire() 91 92 // l1: level 0 non-leaf pte 93 val l1 = Reg(Vec(l2tlbParams.l1Size, new PtwEntry(tagLen = PtwL1TagLen))) 94 val l1v = RegInit(0.U(l2tlbParams.l1Size.W)) 95 val l1g = Reg(UInt(l2tlbParams.l1Size.W)) 96 97 // l2: level 1 non-leaf pte 98 val l2 = Module(new SRAMTemplate( 99 l2EntryType, 100 set = l2tlbParams.l2nSets, 101 way = l2tlbParams.l2nWays, 102 singlePort = sramSinglePort 103 )) 104 val l2v = RegInit(0.U((l2tlbParams.l2nSets * l2tlbParams.l2nWays).W)) 105 val l2g = Reg(UInt((l2tlbParams.l2nSets * l2tlbParams.l2nWays).W)) 106 def getl2vSet(vpn: UInt) = { 107 require(log2Up(l2tlbParams.l2nWays) == log2Down(l2tlbParams.l2nWays)) 108 val set = genPtwL2SetIdx(vpn) 109 require(set.getWidth == log2Up(l2tlbParams.l2nSets)) 110 val l2vVec = l2v.asTypeOf(Vec(l2tlbParams.l2nSets, UInt(l2tlbParams.l2nWays.W))) 111 l2vVec(set) 112 } 113 114 // l3: level 2 leaf pte of 4KB pages 115 val l3 = Module(new SRAMTemplate( 116 l3EntryType, 117 set = l2tlbParams.l3nSets, 118 way = l2tlbParams.l3nWays, 119 singlePort = sramSinglePort 120 )) 121 val l3v = RegInit(0.U((l2tlbParams.l3nSets * l2tlbParams.l3nWays).W)) 122 val l3g = Reg(UInt((l2tlbParams.l3nSets * l2tlbParams.l3nWays).W)) 123 def getl3vSet(vpn: UInt) = { 124 require(log2Up(l2tlbParams.l3nWays) == log2Down(l2tlbParams.l3nWays)) 125 val set = genPtwL3SetIdx(vpn) 126 require(set.getWidth == log2Up(l2tlbParams.l3nSets)) 127 val l3vVec = l3v.asTypeOf(Vec(l2tlbParams.l3nSets, UInt(l2tlbParams.l3nWays.W))) 128 l3vVec(set) 129 } 130 131 // sp: level 0/1 leaf pte of 1GB/2MB super pages 132 val sp = Reg(Vec(l2tlbParams.spSize, new PtwEntry(tagLen = SPTagLen, hasPerm = true, hasLevel = true))) 133 val spv = RegInit(0.U(l2tlbParams.spSize.W)) 134 val spg = Reg(UInt(l2tlbParams.spSize.W)) 135 136 // Access Perf 137 val l1AccessPerf = Wire(Vec(l2tlbParams.l1Size, Bool())) 138 val l2AccessPerf = Wire(Vec(l2tlbParams.l2nWays, Bool())) 139 val l3AccessPerf = Wire(Vec(l2tlbParams.l3nWays, Bool())) 140 val spAccessPerf = Wire(Vec(l2tlbParams.spSize, Bool())) 141 l1AccessPerf.map(_ := false.B) 142 l2AccessPerf.map(_ := false.B) 143 l3AccessPerf.map(_ := false.B) 144 spAccessPerf.map(_ := false.B) 145 146 // l1 147 val ptwl1replace = ReplacementPolicy.fromString(l2tlbParams.l1Replacer, l2tlbParams.l1Size) 148 val (l1Hit, l1HitPPN, l1Pre) = { 149 val hitVecT = l1.zipWithIndex.map { case (e, i) => e.hit(first_req.vpn) && l1v(i) } 150 val hitVec = hitVecT.map(RegEnable(_, first_fire)) 151 val hitPPN = ParallelPriorityMux(hitVec zip l1.map(_.ppn)) 152 val hitPre = ParallelPriorityMux(hitVec zip l1.map(_.prefetch)) 153 val hit = ParallelOR(hitVec) && second_valid 154 155 when (hit) { ptwl1replace.access(OHToUInt(hitVec)) } 156 157 l1AccessPerf.zip(hitVec).map{ case (l, h) => l := h && RegNext(first_fire)} 158 for (i <- 0 until l2tlbParams.l1Size) { 159 XSDebug(first_fire, p"[l1] l1(${i.U}) ${l1(i)} hit:${l1(i).hit(first_req.vpn)}\n") 160 } 161 XSDebug(first_fire, p"[l1] l1v:${Binary(l1v)} hitVecT:${Binary(VecInit(hitVecT).asUInt)}\n") 162 XSDebug(second_valid, p"[l1] l1Hit:${hit} l1HitPPN:0x${Hexadecimal(hitPPN)} hitVec:${VecInit(hitVec).asUInt}\n") 163 164 VecInit(hitVecT).suggestName(s"l1_hitVecT") 165 VecInit(hitVec).suggestName(s"l1_hitVec") 166 167 (hit, hitPPN, hitPre) 168 } 169 170 // l2 171 val ptwl2replace = ReplacementPolicy.fromString(l2tlbParams.l2Replacer,l2tlbParams.l2nWays,l2tlbParams.l2nSets) 172 val (l2Hit, l2HitPPN, l2Pre, l2eccError) = { 173 val ridx = genPtwL2SetIdx(first_req.vpn) 174 val vidx = RegEnable(VecInit(getl2vSet(first_req.vpn).asBools), first_fire) 175 l2.io.r.req.valid := first_fire 176 l2.io.r.req.bits.apply(setIdx = ridx) 177 val ramDatas = l2.io.r.resp.data 178 // val hitVec = VecInit(ramDatas.map{wayData => wayData.hit(first_req.vpn) }) 179 val hitVec = VecInit(ramDatas.zip(vidx).map { case (wayData, v) => wayData.entries.hit(second_req.vpn) && v }) 180 val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas) 181 val hitWayData = hitWayEntry.entries 182 val hitWayEcc = hitWayEntry.ecc 183 val hit = ParallelOR(hitVec) && second_valid 184 val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l2nWays).map(_.U)) 185 186 val eccError = ecc.decode(Cat(hitWayEcc, hitWayData.asUInt())).error 187 188 ridx.suggestName(s"l2_ridx") 189 vidx.suggestName(s"l2_vidx") 190 ramDatas.suggestName(s"l2_ramDatas") 191 hitVec.suggestName(s"l2_hitVec") 192 hitWayData.suggestName(s"l2_hitWayData") 193 hitWay.suggestName(s"l2_hitWay") 194 195 when (hit) { ptwl2replace.access(genPtwL2SetIdx(second_req.vpn), hitWay) } 196 197 l2AccessPerf.zip(hitVec).map{ case (l, h) => l := h && RegNext(first_fire) } 198 XSDebug(first_fire, p"[l2] ridx:0x${Hexadecimal(ridx)}\n") 199 for (i <- 0 until l2tlbParams.l2nWays) { 200 XSDebug(RegNext(first_fire), p"[l2] ramDatas(${i.U}) ${ramDatas(i)} l2v:${vidx(i)} hit:${ramDatas(i).entries.hit(second_req.vpn)}\n") 201 } 202 XSDebug(second_valid, p"[l2] l2Hit:${hit} l2HitPPN:0x${Hexadecimal(hitWayData.ppns(genPtwL2SectorIdx(second_req.vpn)))} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} vidx:${Binary(vidx.asUInt)}\n") 203 204 (hit && !eccError, hitWayData.ppns(genPtwL2SectorIdx(second_req.vpn)), hitWayData.prefetch, hit && eccError) 205 } 206 207 // l3 208 val ptwl3replace = ReplacementPolicy.fromString(l2tlbParams.l3Replacer,l2tlbParams.l3nWays,l2tlbParams.l3nSets) 209 val (l3Hit, l3HitData, l3Pre, l3eccError) = { 210 val ridx = genPtwL3SetIdx(first_req.vpn) 211 val vidx = RegEnable(VecInit(getl3vSet(first_req.vpn).asBools), first_fire) 212 l3.io.r.req.valid := first_fire 213 l3.io.r.req.bits.apply(setIdx = ridx) 214 val ramDatas = l3.io.r.resp.data 215 val hitVec = VecInit(ramDatas.zip(vidx).map{ case (wayData, v) => wayData.entries.hit(second_req.vpn) && v }) 216 val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas) 217 val hitWayData = hitWayEntry.entries 218 val hitWayEcc = hitWayEntry.ecc 219 val hit = ParallelOR(hitVec) && second_valid 220 val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l3nWays).map(_.U)) 221 222 val eccError = ecc.decode(Cat(hitWayEcc, hitWayData.asUInt())).error 223 224 when (hit) { ptwl3replace.access(genPtwL3SetIdx(second_req.vpn), hitWay) } 225 226 l3AccessPerf.zip(hitVec).map{ case (l, h) => l := h && RegNext(first_fire) } 227 XSDebug(first_fire, p"[l3] ridx:0x${Hexadecimal(ridx)}\n") 228 for (i <- 0 until l2tlbParams.l3nWays) { 229 XSDebug(RegNext(first_fire), p"[l3] ramDatas(${i.U}) ${ramDatas(i)} l3v:${vidx(i)} hit:${ramDatas(i).entries.hit(second_req.vpn)}\n") 230 } 231 XSDebug(second_valid, p"[l3] l3Hit:${hit} l3HitData:${hitWayData} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} vidx:${Binary(vidx.asUInt)}\n") 232 233 ridx.suggestName(s"l3_ridx") 234 vidx.suggestName(s"l3_vidx") 235 ramDatas.suggestName(s"l3_ramDatas") 236 hitVec.suggestName(s"l3_hitVec") 237 hitWay.suggestName(s"l3_hitWay") 238 239 (hit && !eccError, hitWayData, hitWayData.prefetch, hit && eccError) 240 } 241 val l3HitPPN = l3HitData.ppns(genPtwL3SectorIdx(second_req.vpn)) 242 val l3HitPerm = l3HitData.perms.getOrElse(0.U.asTypeOf(Vec(PtwL3SectorSize, new PtePermBundle)))(genPtwL3SectorIdx(second_req.vpn)) 243 244 // super page 245 val spreplace = ReplacementPolicy.fromString(l2tlbParams.spReplacer, l2tlbParams.spSize) 246 val (spHit, spHitData, spPre) = { 247 val hitVecT = sp.zipWithIndex.map { case (e, i) => e.hit(first_req.vpn) && spv(i) } 248 val hitVec = hitVecT.map(RegEnable(_, first_fire)) 249 val hitData = ParallelPriorityMux(hitVec zip sp) 250 val hit = ParallelOR(hitVec) && second_valid 251 252 when (hit) { spreplace.access(OHToUInt(hitVec)) } 253 254 spAccessPerf.zip(hitVec).map{ case (s, h) => s := h && RegNext(first_fire) } 255 for (i <- 0 until l2tlbParams.spSize) { 256 XSDebug(first_fire, p"[sp] sp(${i.U}) ${sp(i)} hit:${sp(i).hit(first_req.vpn)} spv:${spv(i)}\n") 257 } 258 XSDebug(second_valid, p"[sp] spHit:${hit} spHitData:${hitData} hitVec:${Binary(VecInit(hitVec).asUInt)}\n") 259 260 VecInit(hitVecT).suggestName(s"sp_hitVecT") 261 VecInit(hitVec).suggestName(s"sp_hitVec") 262 263 (hit, hitData, hitData.prefetch) 264 } 265 val spHitPerm = spHitData.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)) 266 val spHitLevel = spHitData.level.getOrElse(0.U) 267 268 val resp = Wire(io.resp.bits.cloneType) 269 val resp_latch = RegEnable(resp, io.resp.valid && !io.resp.ready) 270 val resp_latch_valid = ValidHold(io.resp.valid && !io.resp.ready, io.resp.fire(), sfence.valid) 271 second_ready := !second_valid || io.resp.fire() 272 resp.source := second_req.source 273 resp.vpn := second_req.vpn 274 resp.hit := l3Hit || spHit 275 resp.prefetch := l3Pre && l3Hit || spPre && spHit 276 resp.toFsm.l1Hit := l1Hit 277 resp.toFsm.l2Hit := l2Hit 278 resp.toFsm.ppn := Mux(l2Hit, l2HitPPN, l1HitPPN) 279 resp.toTlb.tag := second_req.vpn 280 resp.toTlb.ppn := Mux(l3Hit, l3HitPPN, spHitData.ppn) 281 resp.toTlb.perm.map(_ := Mux(l3Hit, l3HitPerm, spHitPerm)) 282 resp.toTlb.level.map(_ := Mux(l3Hit, 2.U, spHitLevel)) 283 resp.toTlb.prefetch := from_pre(second_req.source) 284 285 io.resp.valid := second_valid 286 io.resp.bits := Mux(resp_latch_valid, resp_latch, resp) 287 assert(!(l3Hit && spHit), "normal page and super page both hit") 288 289 // refill Perf 290 val l1RefillPerf = Wire(Vec(l2tlbParams.l1Size, Bool())) 291 val l2RefillPerf = Wire(Vec(l2tlbParams.l2nWays, Bool())) 292 val l3RefillPerf = Wire(Vec(l2tlbParams.l3nWays, Bool())) 293 val spRefillPerf = Wire(Vec(l2tlbParams.spSize, Bool())) 294 l1RefillPerf.map(_ := false.B) 295 l2RefillPerf.map(_ := false.B) 296 l3RefillPerf.map(_ := false.B) 297 spRefillPerf.map(_ := false.B) 298 299 // refill 300 l2.io.w.req <> DontCare 301 l3.io.w.req <> DontCare 302 l2.io.w.req.valid := false.B 303 l3.io.w.req.valid := false.B 304 305 def get_part(data: UInt, index: UInt): UInt = { 306 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 307 inner_data(index) 308 } 309 310 val memRdata = refill.ptes 311 val memSelData = get_part(memRdata, refill.addr_low) 312 val memPtes = (0 until (l2tlbParams.blockBytes/(XLEN/8))).map(i => memRdata((i+1)*XLEN-1, i*XLEN).asTypeOf(new PteBundle)) 313 val memPte = memSelData.asTypeOf(new PteBundle) 314 315 memPte.suggestName("memPte") 316 317 // TODO: handle sfenceLatch outsize 318 when (io.refill.valid && !memPte.isPf(refill.level) && !sfence.valid ) { 319 when (refill.level === 0.U && !memPte.isLeaf()) { 320 // val refillIdx = LFSR64()(log2Up(l2tlbParams.l1Size)-1,0) // TODO: may be LRU 321 val refillIdx = replaceWrapper(l1v, ptwl1replace.way) 322 refillIdx.suggestName(s"PtwL1RefillIdx") 323 val rfOH = UIntToOH(refillIdx) 324 l1(refillIdx).refill(refill.vpn, memSelData, 0.U, refill.prefetch) 325 ptwl1replace.access(refillIdx) 326 l1v := l1v | rfOH 327 l1g := (l1g & ~rfOH) | Mux(memPte.perm.g, rfOH, 0.U) 328 329 for (i <- 0 until l2tlbParams.l1Size) { 330 l1RefillPerf(i) := i.U === refillIdx 331 } 332 333 XSDebug(p"[l1 refill] refillIdx:${refillIdx} refillEntry:${l1(refillIdx).genPtwEntry(refill.vpn, memSelData, 0.U, refill.prefetch)}\n") 334 XSDebug(p"[l1 refill] l1v:${Binary(l1v)}->${Binary(l1v | rfOH)} l1g:${Binary(l1g)}->${Binary((l1g & ~rfOH) | Mux(memPte.perm.g, rfOH, 0.U))}\n") 335 336 refillIdx.suggestName(s"l1_refillIdx") 337 rfOH.suggestName(s"l1_rfOH") 338 } 339 340 when (refill.level === 1.U && !memPte.isLeaf()) { 341 val refillIdx = genPtwL2SetIdx(refill.vpn) 342 val victimWay = replaceWrapper(RegEnable(VecInit(getl2vSet(refill.vpn).asBools).asUInt, first_fire), ptwl2replace.way(refillIdx)) 343 val victimWayOH = UIntToOH(victimWay) 344 val rfvOH = UIntToOH(Cat(refillIdx, victimWay)) 345 val wdata = Wire(l2EntryType) 346 wdata.entries := wdata.entries.genEntries(vpn = refill.vpn, data = memRdata, levelUInt = 1.U, refill.prefetch) 347 wdata.ecc := ecc.encode(wdata.entries.asUInt()) >> wdata.entries.getWidth 348 l2.io.w.apply( 349 valid = true.B, 350 setIdx = refillIdx, 351 data = wdata, 352 waymask = victimWayOH 353 ) 354 ptwl2replace.access(refillIdx, victimWay) 355 l2v := l2v | rfvOH 356 l2g := l2g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U) 357 358 for (i <- 0 until l2tlbParams.l2nWays) { 359 l2RefillPerf(i) := i.U === victimWay 360 } 361 362 XSDebug(p"[l2 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n") 363 XSDebug(p"[l2 refill] refilldata:0x${ 364 (new PtwEntries(num = PtwL2SectorSize, tagLen = PtwL2TagLen, level = 1, hasPerm = false)).genEntries( 365 vpn = refill.vpn, data = memRdata, levelUInt = 1.U, refill.prefetch) 366 }\n") 367 XSDebug(p"[l2 refill] l2v:${Binary(l2v)} -> ${Binary(l2v | rfvOH)}\n") 368 XSDebug(p"[l2 refill] l2g:${Binary(l2g)} -> ${Binary(l2g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n") 369 370 refillIdx.suggestName(s"l2_refillIdx") 371 victimWay.suggestName(s"l2_victimWay") 372 victimWayOH.suggestName(s"l2_victimWayOH") 373 rfvOH.suggestName(s"l2_rfvOH") 374 } 375 376 when (refill.level === 2.U && memPte.isLeaf()) { 377 val refillIdx = genPtwL3SetIdx(refill.vpn) 378 val victimWay = replaceWrapper(RegEnable(VecInit(getl3vSet(refill.vpn).asBools).asUInt, first_fire), ptwl3replace.way(refillIdx)) 379 val victimWayOH = UIntToOH(victimWay) 380 val rfvOH = UIntToOH(Cat(refillIdx, victimWay)) 381 val wdata = Wire(l3EntryType) 382 wdata.entries := wdata.entries.genEntries(vpn = refill.vpn, data = memRdata, levelUInt = 2.U, refill.prefetch) 383 wdata.ecc := ecc.encode(wdata.entries.asUInt()) >> wdata.entries.getWidth 384 l3.io.w.apply( 385 valid = true.B, 386 setIdx = refillIdx, 387 data = wdata, 388 waymask = victimWayOH 389 ) 390 ptwl3replace.access(refillIdx, victimWay) 391 l3v := l3v | rfvOH 392 l3g := l3g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U) 393 394 for (i <- 0 until l2tlbParams.l3nWays) { 395 l3RefillPerf(i) := i.U === victimWay 396 } 397 398 XSDebug(p"[l3 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n") 399 XSDebug(p"[l3 refill] refilldata:0x${ 400 (new PtwEntries(num = PtwL3SectorSize, tagLen = PtwL3TagLen, level = 2, hasPerm = true)).genEntries( 401 vpn = refill.vpn, data = memRdata, levelUInt = 2.U, refill.prefetch) 402 }\n") 403 XSDebug(p"[l3 refill] l3v:${Binary(l3v)} -> ${Binary(l3v | rfvOH)}\n") 404 XSDebug(p"[l3 refill] l3g:${Binary(l3g)} -> ${Binary(l3g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n") 405 406 refillIdx.suggestName(s"l3_refillIdx") 407 victimWay.suggestName(s"l3_victimWay") 408 victimWayOH.suggestName(s"l3_victimWayOH") 409 rfvOH.suggestName(s"l3_rfvOH") 410 } 411 when ((refill.level === 0.U || refill.level === 1.U) && memPte.isLeaf()) { 412 val refillIdx = spreplace.way// LFSR64()(log2Up(l2tlbParams.spSize)-1,0) // TODO: may be LRU 413 val rfOH = UIntToOH(refillIdx) 414 sp(refillIdx).refill(refill.vpn, memSelData, refill.level, refill.prefetch) 415 spreplace.access(refillIdx) 416 spv := spv | rfOH 417 spg := spg & ~rfOH | Mux(memPte.perm.g, rfOH, 0.U) 418 419 for (i <- 0 until l2tlbParams.spSize) { 420 spRefillPerf(i) := i.U === refillIdx 421 } 422 423 XSDebug(p"[sp refill] refillIdx:${refillIdx} refillEntry:${sp(refillIdx).genPtwEntry(refill.vpn, memSelData, refill.level, refill.prefetch)}\n") 424 XSDebug(p"[sp refill] spv:${Binary(spv)}->${Binary(spv | rfOH)} spg:${Binary(spg)}->${Binary(spg & ~rfOH | Mux(memPte.perm.g, rfOH, 0.U))}\n") 425 426 refillIdx.suggestName(s"sp_refillIdx") 427 rfOH.suggestName(s"sp_rfOH") 428 } 429 } 430 431 val l2eccFlush = RegNext(l2eccError, init = false.B) 432 val l3eccFlush = RegNext(l3eccError, init = false.B) 433 val eccVpn = RegNext(second_req.vpn) 434 435 assert(!l2eccFlush) 436 assert(!l3eccFlush) 437 when (l2eccFlush) { 438 val flushSetIdxOH = UIntToOH(genPtwL2SetIdx(eccVpn)) 439 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l2nWays, a.asUInt) }).asUInt 440 l2v := l2v & ~flushMask 441 l2g := l2g & ~flushMask 442 } 443 444 when (l3eccFlush) { 445 val flushSetIdxOH = UIntToOH(genPtwL3SetIdx(eccVpn)) 446 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l3nWays, a.asUInt) }).asUInt 447 l3v := l3v & ~flushMask 448 l3g := l3g & ~flushMask 449 } 450 451 // sfence 452 when (sfence.valid) { 453 when (sfence.bits.rs1/*va*/) { 454 when (sfence.bits.rs2) { 455 // all va && all asid 456 l1v := 0.U 457 l2v := 0.U 458 l3v := 0.U 459 spv := 0.U 460 } .otherwise { 461 // all va && specific asid except global 462 l1v := l1v & l1g 463 l2v := l2v & l2g 464 l3v := l3v & l3g 465 spv := spv & spg 466 } 467 } .otherwise { 468 // val flushMask = UIntToOH(genTlbL2Idx(sfence.bits.addr(sfence.bits.addr.getWidth-1, offLen))) 469 val flushSetIdxOH = UIntToOH(genPtwL3SetIdx(sfence.bits.addr(sfence.bits.addr.getWidth-1, offLen))) 470 // val flushMask = VecInit(flushSetIdxOH.asBools.map(Fill(l2tlbParams.l3nWays, _.asUInt))).asUInt 471 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l3nWays, a.asUInt) }).asUInt 472 flushSetIdxOH.suggestName(s"sfence_nrs1_flushSetIdxOH") 473 flushMask.suggestName(s"sfence_nrs1_flushMask") 474 when (sfence.bits.rs2) { 475 // specific leaf of addr && all asid 476 l3v := l3v & ~flushMask 477 l3g := l3g & ~flushMask 478 } .otherwise { 479 // specific leaf of addr && specific asid 480 l3v := l3v & (~flushMask | l3g) 481 } 482 spv := 0.U 483 } 484 } 485 486 // Perf Count 487 val resp_l3 = DataHoldBypass(l3Hit, io.resp.valid && !resp_latch_valid).asBool() 488 val resp_sp = DataHoldBypass(spHit, io.resp.valid && !resp_latch_valid).asBool() 489 val resp_l1_pre = DataHoldBypass(l1Pre, io.resp.valid && !resp_latch_valid).asBool() 490 val resp_l2_pre = DataHoldBypass(l2Pre, io.resp.valid && !resp_latch_valid).asBool() 491 val resp_l3_pre = DataHoldBypass(l3Pre, io.resp.valid && !resp_latch_valid).asBool() 492 val resp_sp_pre = DataHoldBypass(spPre, io.resp.valid && !resp_latch_valid).asBool() 493 val base_valid_access_0 = !from_pre(io.resp.bits.source) && io.resp.fire() 494 XSPerfAccumulate("access", base_valid_access_0) 495 XSPerfAccumulate("l1_hit", base_valid_access_0 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 496 XSPerfAccumulate("l2_hit", base_valid_access_0 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 497 XSPerfAccumulate("l3_hit", base_valid_access_0 && resp_l3) 498 XSPerfAccumulate("sp_hit", base_valid_access_0 && resp_sp) 499 XSPerfAccumulate("pte_hit",base_valid_access_0 && io.resp.bits.hit) 500 501 XSPerfAccumulate("l1_hit_pre", base_valid_access_0 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 502 XSPerfAccumulate("l2_hit_pre", base_valid_access_0 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 503 XSPerfAccumulate("l3_hit_pre", base_valid_access_0 && resp_l3_pre && resp_l3) 504 XSPerfAccumulate("sp_hit_pre", base_valid_access_0 && resp_sp_pre && resp_sp) 505 XSPerfAccumulate("pte_hit_pre",base_valid_access_0 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 506 507 val base_valid_access_1 = from_pre(io.resp.bits.source) && io.resp.fire() 508 XSPerfAccumulate("pre_access", base_valid_access_1) 509 XSPerfAccumulate("pre_l1_hit", base_valid_access_1 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 510 XSPerfAccumulate("pre_l2_hit", base_valid_access_1 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 511 XSPerfAccumulate("pre_l3_hit", base_valid_access_1 && resp_l3) 512 XSPerfAccumulate("pre_sp_hit", base_valid_access_1 && resp_sp) 513 XSPerfAccumulate("pre_pte_hit",base_valid_access_1 && io.resp.bits.hit) 514 515 XSPerfAccumulate("pre_l1_hit_pre", base_valid_access_1 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 516 XSPerfAccumulate("pre_l2_hit_pre", base_valid_access_1 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 517 XSPerfAccumulate("pre_l3_hit_pre", base_valid_access_1 && resp_l3_pre && resp_l3) 518 XSPerfAccumulate("pre_sp_hit_pre", base_valid_access_1 && resp_sp_pre && resp_sp) 519 XSPerfAccumulate("pre_pte_hit_pre",base_valid_access_1 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 520 521 val base_valid_access_2 = second_isFirst && !from_pre(io.resp.bits.source) && io.resp.fire() 522 XSPerfAccumulate("access_first", base_valid_access_2) 523 XSPerfAccumulate("l1_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 524 XSPerfAccumulate("l2_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 525 XSPerfAccumulate("l3_hit_first", base_valid_access_2 && resp_l3) 526 XSPerfAccumulate("sp_hit_first", base_valid_access_2 && resp_sp) 527 XSPerfAccumulate("pte_hit_first",base_valid_access_2 && io.resp.bits.hit) 528 529 XSPerfAccumulate("l1_hit_pre_first", base_valid_access_2 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 530 XSPerfAccumulate("l2_hit_pre_first", base_valid_access_2 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 531 XSPerfAccumulate("l3_hit_pre_first", base_valid_access_2 && resp_l3_pre && resp_l3) 532 XSPerfAccumulate("sp_hit_pre_first", base_valid_access_2 && resp_sp_pre && resp_sp) 533 XSPerfAccumulate("pte_hit_pre_first",base_valid_access_2 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 534 535 val base_valid_access_3 = second_isFirst && from_pre(io.resp.bits.source) && io.resp.fire() 536 XSPerfAccumulate("pre_access_first", base_valid_access_3) 537 XSPerfAccumulate("pre_l1_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 538 XSPerfAccumulate("pre_l2_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 539 XSPerfAccumulate("pre_l3_hit_first", base_valid_access_3 && resp_l3) 540 XSPerfAccumulate("pre_sp_hit_first", base_valid_access_3 && resp_sp) 541 XSPerfAccumulate("pre_pte_hit_first", base_valid_access_3 && io.resp.bits.hit) 542 543 XSPerfAccumulate("pre_l1_hit_pre_first", base_valid_access_3 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 544 XSPerfAccumulate("pre_l2_hit_pre_first", base_valid_access_3 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 545 XSPerfAccumulate("pre_l3_hit_pre_first", base_valid_access_3 && resp_l3_pre && resp_l3) 546 XSPerfAccumulate("pre_sp_hit_pre_first", base_valid_access_3 && resp_sp_pre && resp_sp) 547 XSPerfAccumulate("pre_pte_hit_pre_first",base_valid_access_3 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 548 549 XSPerfAccumulate("rwHarzad", io.req.valid && !io.req.ready) 550 XSPerfAccumulate("out_blocked", io.resp.valid && !io.resp.ready) 551 l1AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L1AccessIndex${i}", l) } 552 l2AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L2AccessIndex${i}", l) } 553 l3AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L3AccessIndex${i}", l) } 554 spAccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPAccessIndex${i}", l) } 555 l1RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L1RefillIndex${i}", l) } 556 l2RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L2RefillIndex${i}", l) } 557 l3RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L3RefillIndex${i}", l) } 558 spRefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPRefillIndex${i}", l) } 559 560 XSPerfAccumulate("l1Refill", Cat(l1RefillPerf).orR) 561 XSPerfAccumulate("l2Refill", Cat(l2RefillPerf).orR) 562 XSPerfAccumulate("l3Refill", Cat(l3RefillPerf).orR) 563 XSPerfAccumulate("spRefill", Cat(spRefillPerf).orR) 564 XSPerfAccumulate("l1Refill_pre", Cat(l1RefillPerf).orR && refill.prefetch) 565 XSPerfAccumulate("l2Refill_pre", Cat(l2RefillPerf).orR && refill.prefetch) 566 XSPerfAccumulate("l3Refill_pre", Cat(l3RefillPerf).orR && refill.prefetch) 567 XSPerfAccumulate("spRefill_pre", Cat(spRefillPerf).orR && refill.prefetch) 568 569 // debug 570 XSDebug(sfence.valid, p"[sfence] original v and g vector:\n") 571 XSDebug(sfence.valid, p"[sfence] l1v:${Binary(l1v)}\n") 572 XSDebug(sfence.valid, p"[sfence] l2v:${Binary(l2v)}\n") 573 XSDebug(sfence.valid, p"[sfence] l3v:${Binary(l3v)}\n") 574 XSDebug(sfence.valid, p"[sfence] l3g:${Binary(l3g)}\n") 575 XSDebug(sfence.valid, p"[sfence] spv:${Binary(spv)}\n") 576 XSDebug(RegNext(sfence.valid), p"[sfence] new v and g vector:\n") 577 XSDebug(RegNext(sfence.valid), p"[sfence] l1v:${Binary(l1v)}\n") 578 XSDebug(RegNext(sfence.valid), p"[sfence] l2v:${Binary(l2v)}\n") 579 XSDebug(RegNext(sfence.valid), p"[sfence] l3v:${Binary(l3v)}\n") 580 XSDebug(RegNext(sfence.valid), p"[sfence] l3g:${Binary(l3g)}\n") 581 XSDebug(RegNext(sfence.valid), p"[sfence] spv:${Binary(spv)}\n") 582} 583