xref: /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala (revision ac4d321d18df4775b9ddda83e77cf526a0b1ca67) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.cache.mmu
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import xiangshan._
23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants}
24import utils._
25import utility._
26import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
27import freechips.rocketchip.tilelink._
28
29/* ptw cache caches the page table of all the three layers
30 * ptw cache resp at next cycle
31 * the cache should not be blocked
32 * when miss queue if full, just block req outside
33 */
34
35class PageCachePerPespBundle(implicit p: Parameters) extends PtwBundle {
36  val hit = Bool()
37  val pre = Bool()
38  val ppn = if (HasHExtension) UInt((vpnLen max ppnLen).W) else UInt(ppnLen.W)
39  val perm = new PtePermBundle()
40  val ecc = Bool()
41  val level = UInt(2.W)
42  val v = Bool()
43
44  def apply(hit: Bool, pre: Bool, ppn: UInt, perm: PtePermBundle = 0.U.asTypeOf(new PtePermBundle()),
45            ecc: Bool = false.B, level: UInt = 0.U, valid: Bool = true.B) {
46    this.hit := hit && !ecc
47    this.pre := pre
48    this.ppn := ppn
49    this.perm := perm
50    this.ecc := ecc && hit
51    this.level := level
52    this.v := valid
53  }
54}
55
56class PageCacheMergePespBundle(implicit p: Parameters) extends PtwBundle {
57  assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!")
58  val hit = Bool()
59  val pre = Bool()
60  val ppn = Vec(tlbcontiguous, if(HasHExtension) UInt((vpnLen max ppnLen).W) else UInt(ppnLen.W))
61  val perm = Vec(tlbcontiguous, new PtePermBundle())
62  val ecc = Bool()
63  val level = UInt(2.W)
64  val v = Vec(tlbcontiguous, Bool())
65
66  def apply(hit: Bool, pre: Bool, ppn: Vec[UInt], perm: Vec[PtePermBundle] = Vec(tlbcontiguous, 0.U.asTypeOf(new PtePermBundle())),
67            ecc: Bool = false.B, level: UInt = 0.U, valid: Vec[Bool] = Vec(tlbcontiguous, true.B)) {
68    this.hit := hit && !ecc
69    this.pre := pre
70    this.ppn := ppn
71    this.perm := perm
72    this.ecc := ecc && hit
73    this.level := level
74    this.v := valid
75  }
76}
77
78class PageCacheRespBundle(implicit p: Parameters) extends PtwBundle {
79  val l1 = new PageCachePerPespBundle
80  val l2 = new PageCachePerPespBundle
81  val l3 = new PageCacheMergePespBundle
82  val sp = new PageCachePerPespBundle
83}
84
85class PtwCacheReq(implicit p: Parameters) extends PtwBundle {
86  val req_info = new L2TlbInnerBundle()
87  val isFirst = Bool()
88  val bypassed = Vec(3, Bool())
89  val isHptwReq = Bool()
90  val hptwId = UInt(log2Up(l2tlbParams.llptwsize).W)
91}
92
93class PtwCacheIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst {
94  val req = Flipped(DecoupledIO(new PtwCacheReq()))
95  val resp = DecoupledIO(new Bundle {
96    val req_info = new L2TlbInnerBundle()
97    val isFirst = Bool()
98    val hit = Bool()
99    val prefetch = Bool() // is the entry fetched by prefetch
100    val bypassed = Bool()
101    val toFsm = new Bundle {
102      val l1Hit = Bool()
103      val l2Hit = Bool()
104      val ppn = if(HasHExtension) UInt((vpnLen.max(ppnLen)).W) else UInt(ppnLen.W)
105      val stage1Hit = Bool() // find stage 1 pte in cache, but need to search stage 2 pte in cache at PTW
106    }
107    val toTlb = new PtwMergeResp()
108    val isHptwReq = Bool()
109    val toHptw = new Bundle {
110      val l1Hit = Bool()
111      val l2Hit = Bool()
112      val ppn = UInt(ppnLen.W)
113      val id = UInt(log2Up(l2tlbParams.llptwsize).W)
114      val resp = new HptwResp() // used if hit
115      val bypassed = Bool()
116    }
117  })
118  val refill = Flipped(ValidIO(new Bundle {
119    val ptes = UInt(blockBits.W)
120    val levelOH = new Bundle {
121      // NOTE: levelOH has (Level+1) bits, each stands for page cache entries
122      val sp = Bool()
123      val l3 = Bool()
124      val l2 = Bool()
125      val l1 = Bool()
126      def apply(levelUInt: UInt, valid: Bool) = {
127        sp := RegNext((levelUInt === 0.U || levelUInt === 1.U) && valid, false.B)
128        l3 := RegNext((levelUInt === 2.U) & valid, false.B)
129        l2 := RegNext((levelUInt === 1.U) & valid, false.B)
130        l1 := RegNext((levelUInt === 0.U) & valid, false.B)
131      }
132    }
133    // duplicate level and sel_pte for each page caches, for better fanout
134    val req_info_dup = Vec(3, new L2TlbInnerBundle())
135    val level_dup = Vec(3, UInt(log2Up(Level).W))
136    val sel_pte_dup = Vec(3, UInt(XLEN.W))
137  }))
138  val sfence_dup = Vec(4, Input(new SfenceBundle()))
139  val csr_dup = Vec(3, Input(new TlbCsrBundle()))
140}
141
142class PtwCache()(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents {
143  val io = IO(new PtwCacheIO)
144  val ecc = Code.fromString(l2tlbParams.ecc)
145  val l2EntryType = new PTWEntriesWithEcc(ecc, num = PtwL2SectorSize, tagLen = PtwL2TagLen, level = 1, hasPerm = false)
146  val l3EntryType = new PTWEntriesWithEcc(ecc, num = PtwL3SectorSize, tagLen = PtwL3TagLen, level = 2, hasPerm = true)
147
148  // TODO: four caches make the codes dirty, think about how to deal with it
149
150  val sfence_dup = io.sfence_dup
151  val refill = io.refill.bits
152  val refill_prefetch_dup = io.refill.bits.req_info_dup.map(a => from_pre(a.source))
153  val flush_dup = sfence_dup.zip(io.csr_dup).map(f => f._1.valid || f._2.satp.changed || f._2.vsatp.changed || f._2.hgatp.changed)
154  val flush = flush_dup(0)
155
156  // when refill, refuce to accept new req
157  val rwHarzad = if (sramSinglePort) io.refill.valid else false.B
158
159  // handle hand signal and req_info
160  // TODO: replace with FlushableQueue
161  val stageReq = Wire(Decoupled(new PtwCacheReq()))         // enq stage & read page cache valid
162  val stageDelay = Wire(Vec(2, Decoupled(new PtwCacheReq()))) // page cache resp
163  val stageCheck = Wire(Vec(2, Decoupled(new PtwCacheReq()))) // check hit & check ecc
164  val stageResp = Wire(Decoupled(new PtwCacheReq()))         // deq stage
165
166  val stageDelay_valid_1cycle = OneCycleValid(stageReq.fire, flush)      // catch ram data
167  val stageCheck_valid_1cycle = OneCycleValid(stageDelay(1).fire, flush) // replace & perf counter
168  val stageResp_valid_1cycle_dup = Wire(Vec(2, Bool()))
169  stageResp_valid_1cycle_dup.map(_ := OneCycleValid(stageCheck(1).fire, flush))  // ecc flush
170
171  stageReq <> io.req
172  PipelineConnect(stageReq, stageDelay(0), stageDelay(1).ready, flush, rwHarzad)
173  InsideStageConnect(stageDelay(0), stageDelay(1), stageDelay_valid_1cycle)
174  PipelineConnect(stageDelay(1), stageCheck(0), stageCheck(1).ready, flush)
175  InsideStageConnect(stageCheck(0), stageCheck(1), stageCheck_valid_1cycle)
176  PipelineConnect(stageCheck(1), stageResp, io.resp.ready, flush)
177  stageResp.ready := !stageResp.valid || io.resp.ready
178
179  // l1: level 0 non-leaf pte
180  val l1 = Reg(Vec(l2tlbParams.l1Size, new PtwEntry(tagLen = PtwL1TagLen)))
181  val l1v = RegInit(0.U(l2tlbParams.l1Size.W))
182  val l1g = Reg(UInt(l2tlbParams.l1Size.W))
183  val l1asids = l1.map(_.asid)
184  val l1vmids = l1.map(_.vmid)
185  val l1h = Reg(Vec(l2tlbParams.l1Size, UInt(2.W))) // 0 bit: s2xlate, 1 bit: stage 1 or stage 2
186
187  // l2: level 1 non-leaf pte
188  val l2 = Module(new SRAMTemplate(
189    l2EntryType,
190    set = l2tlbParams.l2nSets,
191    way = l2tlbParams.l2nWays,
192    singlePort = sramSinglePort
193  ))
194  val l2v = RegInit(0.U((l2tlbParams.l2nSets * l2tlbParams.l2nWays).W))
195  val l2g = Reg(UInt((l2tlbParams.l2nSets * l2tlbParams.l2nWays).W))
196  val l2h = Reg(Vec(l2tlbParams.l2nSets, Vec(l2tlbParams.l2nWays, UInt(2.W))))
197  def getl2vSet(vpn: UInt) = {
198    require(log2Up(l2tlbParams.l2nWays) == log2Down(l2tlbParams.l2nWays))
199    val set = genPtwL2SetIdx(vpn)
200    require(set.getWidth == log2Up(l2tlbParams.l2nSets))
201    val l2vVec = l2v.asTypeOf(Vec(l2tlbParams.l2nSets, UInt(l2tlbParams.l2nWays.W)))
202    l2vVec(set)
203  }
204  def getl2hSet(vpn: UInt) = {
205    require(log2Up(l2tlbParams.l2nWays) == log2Down(l2tlbParams.l2nWays))
206    val set = genPtwL2SetIdx(vpn)
207    require(set.getWidth == log2Up(l2tlbParams.l2nSets))
208    l2h(set)
209  }
210
211
212
213  // l3: level 2 leaf pte of 4KB pages
214  val l3 = Module(new SRAMTemplate(
215    l3EntryType,
216    set = l2tlbParams.l3nSets,
217    way = l2tlbParams.l3nWays,
218    singlePort = sramSinglePort
219  ))
220  val l3v = RegInit(0.U((l2tlbParams.l3nSets * l2tlbParams.l3nWays).W))
221  val l3g = Reg(UInt((l2tlbParams.l3nSets * l2tlbParams.l3nWays).W))
222  val l3h = Reg(Vec(l2tlbParams.l3nSets, Vec(l2tlbParams.l3nWays, UInt(2.W))))
223  def getl3vSet(vpn: UInt) = {
224    require(log2Up(l2tlbParams.l3nWays) == log2Down(l2tlbParams.l3nWays))
225    val set = genPtwL3SetIdx(vpn)
226    require(set.getWidth == log2Up(l2tlbParams.l3nSets))
227    val l3vVec = l3v.asTypeOf(Vec(l2tlbParams.l3nSets, UInt(l2tlbParams.l3nWays.W)))
228    l3vVec(set)
229  }
230  def getl3hSet(vpn: UInt) = {
231    require(log2Up(l2tlbParams.l3nWays) == log2Down(l2tlbParams.l3nWays))
232    val set = genPtwL3SetIdx(vpn)
233    require(set.getWidth == log2Up(l2tlbParams.l3nSets))
234    l3h(set)
235  }
236
237  // sp: level 0/1 leaf pte of 1GB/2MB super pages
238  val sp = Reg(Vec(l2tlbParams.spSize, new PtwEntry(tagLen = SPTagLen, hasPerm = true, hasLevel = true)))
239  val spv = RegInit(0.U(l2tlbParams.spSize.W))
240  val spg = Reg(UInt(l2tlbParams.spSize.W))
241  val spasids = sp.map(_.asid)
242  val spvmids = sp.map(_.vmid)
243  val sph = Reg(Vec(l2tlbParams.spSize, UInt(2.W)))
244
245  // Access Perf
246  val l1AccessPerf = Wire(Vec(l2tlbParams.l1Size, Bool()))
247  val l2AccessPerf = Wire(Vec(l2tlbParams.l2nWays, Bool()))
248  val l3AccessPerf = Wire(Vec(l2tlbParams.l3nWays, Bool()))
249  val spAccessPerf = Wire(Vec(l2tlbParams.spSize, Bool()))
250  l1AccessPerf.map(_ := false.B)
251  l2AccessPerf.map(_ := false.B)
252  l3AccessPerf.map(_ := false.B)
253  spAccessPerf.map(_ := false.B)
254
255
256
257  def vpn_match(vpn1: UInt, vpn2: UInt, level: Int) = {
258    (vpn1(vpnLen-1, vpnnLen*(2-level)+3) === vpn2(vpnLen-1, vpnnLen*(2-level)+3))
259  }
260  // NOTE: not actually bypassed, just check if hit, re-access the page cache
261  def refill_bypass(vpn: UInt, level: Int, h_search: UInt) = {
262    val change_h = MuxLookup(h_search, noS2xlate)(Seq(
263      allStage -> onlyStage1,
264      onlyStage1 -> onlyStage1,
265      onlyStage2 -> onlyStage2
266    ))
267    val refill_vpn = io.refill.bits.req_info_dup(0).vpn
268    io.refill.valid && (level.U === io.refill.bits.level_dup(0)) && vpn_match(refill_vpn, vpn, level) && change_h === io.refill.bits.req_info_dup(0).s2xlate
269  }
270
271  val vpn_search = stageReq.bits.req_info.vpn
272  val h_search = MuxLookup(stageReq.bits.req_info.s2xlate, noS2xlate)(Seq(
273    allStage -> onlyStage1,
274    onlyStage1 -> onlyStage1,
275    onlyStage2 -> onlyStage2
276  ))
277  // l1
278  val ptwl1replace = ReplacementPolicy.fromString(l2tlbParams.l1Replacer, l2tlbParams.l1Size)
279  val (l1Hit, l1HitPPN, l1Pre) = {
280    val hitVecT = l1.zipWithIndex.map {
281      case (e, i) => (e.hit(vpn_search, io.csr_dup(0).satp.asid, io.csr_dup(0).vsatp.asid, io.csr_dup(0).hgatp.asid, s2xlate = h_search =/= noS2xlate)
282        && l1v(i) && h_search === l1h(i))
283    }
284    val hitVec = hitVecT.map(RegEnable(_, stageReq.fire))
285
286    // stageDelay, but check for l1
287    val hitPPN = DataHoldBypass(ParallelPriorityMux(hitVec zip l1.map(_.ppn)), stageDelay_valid_1cycle)
288    val hitPre = DataHoldBypass(ParallelPriorityMux(hitVec zip l1.map(_.prefetch)), stageDelay_valid_1cycle)
289    val hit = DataHoldBypass(ParallelOR(hitVec), stageDelay_valid_1cycle)
290
291    when (hit && stageDelay_valid_1cycle) { ptwl1replace.access(OHToUInt(hitVec)) }
292
293    l1AccessPerf.zip(hitVec).map{ case (l, h) => l := h && stageDelay_valid_1cycle}
294    for (i <- 0 until l2tlbParams.l1Size) {
295      XSDebug(stageReq.fire, p"[l1] l1(${i.U}) ${l1(i)} hit:${l1(i).hit(vpn_search, io.csr_dup(0).satp.asid, io.csr_dup(0).vsatp.asid, io.csr_dup(0).hgatp.asid, s2xlate = h_search =/= noS2xlate)}\n")
296    }
297    XSDebug(stageReq.fire, p"[l1] l1v:${Binary(l1v)} hitVecT:${Binary(VecInit(hitVecT).asUInt)}\n")
298    XSDebug(stageDelay(0).valid, p"[l1] l1Hit:${hit} l1HitPPN:0x${Hexadecimal(hitPPN)} hitVec:${VecInit(hitVec).asUInt}\n")
299
300    VecInit(hitVecT).suggestName(s"l1_hitVecT")
301    VecInit(hitVec).suggestName(s"l1_hitVec")
302
303    // synchronize with other entries with RegEnable
304    (RegEnable(hit, stageDelay(1).fire),
305     RegEnable(hitPPN, stageDelay(1).fire),
306     RegEnable(hitPre, stageDelay(1).fire))
307  }
308
309  // l2
310  val ptwl2replace = ReplacementPolicy.fromString(l2tlbParams.l2Replacer,l2tlbParams.l2nWays,l2tlbParams.l2nSets)
311  val (l2Hit, l2HitPPN, l2Pre, l2eccError) = {
312    val ridx = genPtwL2SetIdx(vpn_search)
313    l2.io.r.req.valid := stageReq.fire
314    l2.io.r.req.bits.apply(setIdx = ridx)
315    val vVec_req = getl2vSet(vpn_search)
316    val hVec_req = getl2hSet(vpn_search)
317
318    // delay one cycle after sram read
319    val delay_vpn = stageDelay(0).bits.req_info.vpn
320    val delay_h = MuxLookup(stageDelay(0).bits.req_info.s2xlate, noS2xlate)(Seq(
321      allStage -> onlyStage1,
322      onlyStage1 -> onlyStage1,
323      onlyStage2 -> onlyStage2
324    ))
325    val data_resp = DataHoldBypass(l2.io.r.resp.data, stageDelay_valid_1cycle)
326    val vVec_delay = RegEnable(vVec_req, stageReq.fire)
327    val hVec_delay = RegEnable(hVec_req, stageReq.fire)
328    val hitVec_delay = VecInit(data_resp.zip(vVec_delay.asBools).zip(hVec_delay).map { case ((wayData, v), h) =>
329      wayData.entries.hit(delay_vpn, io.csr_dup(1).satp.asid, io.csr_dup(1).vsatp.asid, io.csr_dup(1).hgatp.asid, s2xlate = delay_h =/= noS2xlate) && v && (delay_h === h)})
330
331    // check hit and ecc
332    val check_vpn = stageCheck(0).bits.req_info.vpn
333    val ramDatas = RegEnable(data_resp, stageDelay(1).fire)
334    val vVec = RegEnable(vVec_delay, stageDelay(1).fire).asBools
335
336    val hitVec = RegEnable(hitVec_delay, stageDelay(1).fire)
337    val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas)
338    val hitWayData = hitWayEntry.entries
339    val hit = ParallelOR(hitVec)
340    val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l2nWays).map(_.U(log2Up(l2tlbParams.l2nWays).W)))
341    val eccError = hitWayEntry.decode()
342
343    ridx.suggestName(s"l2_ridx")
344    ramDatas.suggestName(s"l2_ramDatas")
345    hitVec.suggestName(s"l2_hitVec")
346    hitWayData.suggestName(s"l2_hitWayData")
347    hitWay.suggestName(s"l2_hitWay")
348
349    when (hit && stageCheck_valid_1cycle) { ptwl2replace.access(genPtwL2SetIdx(check_vpn), hitWay) }
350
351    l2AccessPerf.zip(hitVec).map{ case (l, h) => l := h && stageCheck_valid_1cycle }
352    XSDebug(stageDelay_valid_1cycle, p"[l2] ridx:0x${Hexadecimal(ridx)}\n")
353    for (i <- 0 until l2tlbParams.l2nWays) {
354      XSDebug(stageCheck_valid_1cycle, p"[l2] ramDatas(${i.U}) ${ramDatas(i)}  l2v:${vVec(i)}  hit:${hit}\n")
355    }
356    XSDebug(stageCheck_valid_1cycle, p"[l2] l2Hit:${hit} l2HitPPN:0x${Hexadecimal(hitWayData.ppns(genPtwL2SectorIdx(check_vpn)))} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} vidx:${vVec}\n")
357
358    (hit, hitWayData.ppns(genPtwL2SectorIdx(check_vpn)), hitWayData.prefetch, eccError)
359  }
360
361  // l3
362  val ptwl3replace = ReplacementPolicy.fromString(l2tlbParams.l3Replacer,l2tlbParams.l3nWays,l2tlbParams.l3nSets)
363  val (l3Hit, l3HitData, l3Pre, l3eccError) = {
364    val ridx = genPtwL3SetIdx(vpn_search)
365    l3.io.r.req.valid := stageReq.fire
366    l3.io.r.req.bits.apply(setIdx = ridx)
367    val vVec_req = getl3vSet(vpn_search)
368    val hVec_req = getl3hSet(vpn_search)
369
370    // delay one cycle after sram read
371    val delay_vpn = stageDelay(0).bits.req_info.vpn
372    val delay_h = MuxLookup(stageDelay(0).bits.req_info.s2xlate, noS2xlate)(Seq(
373      allStage -> onlyStage1,
374      onlyStage1 -> onlyStage1,
375      onlyStage2 -> onlyStage2
376    ))
377    val data_resp = DataHoldBypass(l3.io.r.resp.data, stageDelay_valid_1cycle)
378    val vVec_delay = RegEnable(vVec_req, stageReq.fire)
379    val hVec_delay = RegEnable(hVec_req, stageReq.fire)
380    val hitVec_delay = VecInit(data_resp.zip(vVec_delay.asBools).zip(hVec_delay).map { case ((wayData, v), h) =>
381      wayData.entries.hit(delay_vpn, io.csr_dup(2).satp.asid, io.csr_dup(2).vsatp.asid, io.csr_dup(2).hgatp.asid, s2xlate = delay_h =/= noS2xlate) && v && (delay_h === h)})
382
383    // check hit and ecc
384    val check_vpn = stageCheck(0).bits.req_info.vpn
385    val ramDatas = RegEnable(data_resp, stageDelay(1).fire)
386    val vVec = RegEnable(vVec_delay, stageDelay(1).fire).asBools
387
388    val hitVec = RegEnable(hitVec_delay, stageDelay(1).fire)
389    val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas)
390    val hitWayData = hitWayEntry.entries
391    val hitWayEcc = hitWayEntry.ecc
392    val hit = ParallelOR(hitVec)
393    val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l3nWays).map(_.U(log2Up(l2tlbParams.l3nWays).W)))
394    val eccError = hitWayEntry.decode()
395
396    when (hit && stageCheck_valid_1cycle) { ptwl3replace.access(genPtwL3SetIdx(check_vpn), hitWay) }
397
398    l3AccessPerf.zip(hitVec).map{ case (l, h) => l := h && stageCheck_valid_1cycle }
399    XSDebug(stageReq.fire, p"[l3] ridx:0x${Hexadecimal(ridx)}\n")
400    for (i <- 0 until l2tlbParams.l3nWays) {
401      XSDebug(stageCheck_valid_1cycle, p"[l3] ramDatas(${i.U}) ${ramDatas(i)}  l3v:${vVec(i)}  hit:${hitVec(i)}\n")
402    }
403    XSDebug(stageCheck_valid_1cycle, p"[l3] l3Hit:${hit} l3HitData:${hitWayData} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} v:${vVec}\n")
404
405    ridx.suggestName(s"l3_ridx")
406    ramDatas.suggestName(s"l3_ramDatas")
407    hitVec.suggestName(s"l3_hitVec")
408    hitWay.suggestName(s"l3_hitWay")
409
410    (hit, hitWayData, hitWayData.prefetch, eccError)
411  }
412  val l3HitPPN = l3HitData.ppns
413  val l3HitPerm = l3HitData.perms.getOrElse(0.U.asTypeOf(Vec(PtwL3SectorSize, new PtePermBundle)))
414  val l3HitValid = l3HitData.vs
415
416  // super page
417  val spreplace = ReplacementPolicy.fromString(l2tlbParams.spReplacer, l2tlbParams.spSize)
418  val (spHit, spHitData, spPre, spValid) = {
419    val hitVecT = sp.zipWithIndex.map { case (e, i) => e.hit(vpn_search, io.csr_dup(0).satp.asid, io.csr_dup(0).vsatp.asid, io.csr_dup(0).hgatp.asid, s2xlate = h_search =/= noS2xlate) && spv(i) && (sph(i) === h_search) }
420    val hitVec = hitVecT.map(RegEnable(_, stageReq.fire))
421    val hitData = ParallelPriorityMux(hitVec zip sp)
422    val hit = ParallelOR(hitVec)
423
424    when (hit && stageDelay_valid_1cycle) { spreplace.access(OHToUInt(hitVec)) }
425
426    spAccessPerf.zip(hitVec).map{ case (s, h) => s := h && stageDelay_valid_1cycle }
427    for (i <- 0 until l2tlbParams.spSize) {
428      XSDebug(stageReq.fire, p"[sp] sp(${i.U}) ${sp(i)} hit:${sp(i).hit(vpn_search, io.csr_dup(0).satp.asid, io.csr_dup(0).vsatp.asid, io.csr_dup(0).hgatp.asid, s2xlate = h_search =/= noS2xlate)} spv:${spv(i)}\n")
429    }
430    XSDebug(stageDelay_valid_1cycle, p"[sp] spHit:${hit} spHitData:${hitData} hitVec:${Binary(VecInit(hitVec).asUInt)}\n")
431
432    VecInit(hitVecT).suggestName(s"sp_hitVecT")
433    VecInit(hitVec).suggestName(s"sp_hitVec")
434
435    (RegEnable(hit, stageDelay(1).fire),
436     RegEnable(hitData, stageDelay(1).fire),
437     RegEnable(hitData.prefetch, stageDelay(1).fire),
438     RegEnable(hitData.v, stageDelay(1).fire))
439  }
440  val spHitPerm = spHitData.perm.getOrElse(0.U.asTypeOf(new PtePermBundle))
441  val spHitLevel = spHitData.level.getOrElse(0.U)
442
443  val check_res = Wire(new PageCacheRespBundle)
444  check_res.l1.apply(l1Hit, l1Pre, l1HitPPN)
445  check_res.l2.apply(l2Hit, l2Pre, l2HitPPN, ecc = l2eccError)
446  check_res.l3.apply(l3Hit, l3Pre, l3HitPPN, l3HitPerm, l3eccError, valid = l3HitValid)
447  check_res.sp.apply(spHit, spPre, spHitData.ppn, spHitPerm, false.B, spHitLevel, spValid)
448
449  val resp_res = Reg(new PageCacheRespBundle)
450  when (stageCheck(1).fire) { resp_res := check_res }
451
452  // stageResp bypass
453  val bypassed = Wire(Vec(3, Bool()))
454  bypassed.indices.foreach(i =>
455    bypassed(i) := stageResp.bits.bypassed(i) ||
456      ValidHoldBypass(refill_bypass(stageResp.bits.req_info.vpn, i, stageResp.bits.req_info.s2xlate),
457        OneCycleValid(stageCheck(1).fire, false.B) || io.refill.valid)
458  )
459
460  // stageResp bypass to hptw
461  val hptw_bypassed = Wire(Vec(3, Bool()))
462  hptw_bypassed.indices.foreach(i =>
463    hptw_bypassed(i) := stageResp.bits.bypassed(i) ||
464      ValidHoldBypass(refill_bypass(stageResp.bits.req_info.vpn, i, stageResp.bits.req_info.s2xlate),
465        io.resp.fire)
466  )
467
468  val isAllStage = stageResp.bits.req_info.s2xlate === allStage
469  val isOnlyStage2 = stageResp.bits.req_info.s2xlate === onlyStage2
470  val stage1Hit = (resp_res.l3.hit || resp_res.sp.hit) && isAllStage
471  io.resp.bits.req_info   := stageResp.bits.req_info
472  io.resp.bits.isFirst  := stageResp.bits.isFirst
473  io.resp.bits.hit      := (resp_res.l3.hit || resp_res.sp.hit) && !isAllStage
474  io.resp.bits.bypassed := (bypassed(2) || (bypassed(1) && !resp_res.l2.hit) || (bypassed(0) && !resp_res.l1.hit)) && !isAllStage
475  io.resp.bits.prefetch := resp_res.l3.pre && resp_res.l3.hit || resp_res.sp.pre && resp_res.sp.hit
476  io.resp.bits.toFsm.l1Hit := resp_res.l1.hit && !stage1Hit && !isOnlyStage2 && !stageResp.bits.isHptwReq
477  io.resp.bits.toFsm.l2Hit := resp_res.l2.hit && !stage1Hit && !isOnlyStage2 && !stageResp.bits.isHptwReq
478  io.resp.bits.toFsm.ppn   := Mux(resp_res.l2.hit, resp_res.l2.ppn, resp_res.l1.ppn)
479  io.resp.bits.toFsm.stage1Hit := stage1Hit
480
481  io.resp.bits.isHptwReq := stageResp.bits.isHptwReq
482  io.resp.bits.toHptw.bypassed := (hptw_bypassed(2) || (hptw_bypassed(1) && !resp_res.l2.hit) || (hptw_bypassed(0) && !resp_res.l1.hit)) && stageResp.bits.isHptwReq
483  io.resp.bits.toHptw.id := stageResp.bits.hptwId
484  io.resp.bits.toHptw.l1Hit := resp_res.l1.hit && stageResp.bits.isHptwReq
485  io.resp.bits.toHptw.l2Hit := resp_res.l2.hit && stageResp.bits.isHptwReq
486  io.resp.bits.toHptw.ppn := Mux(resp_res.l2.hit, resp_res.l2.ppn, resp_res.l1.ppn)
487  val idx = stageResp.bits.req_info.vpn(2, 0)
488  io.resp.bits.toHptw.resp.entry.tag := stageResp.bits.req_info.vpn
489  io.resp.bits.toHptw.resp.entry.asid := DontCare
490  io.resp.bits.toHptw.resp.entry.vmid.map(_ := io.csr_dup(0).hgatp.asid)
491  io.resp.bits.toHptw.resp.entry.level.map(_ := Mux(resp_res.l3.hit, 2.U, resp_res.sp.level))
492  io.resp.bits.toHptw.resp.entry.prefetch := from_pre(stageResp.bits.req_info.source)
493  io.resp.bits.toHptw.resp.entry.ppn := Mux(resp_res.l3.hit, resp_res.l3.ppn(idx), resp_res.sp.ppn)
494  io.resp.bits.toHptw.resp.entry.perm.map(_ := Mux(resp_res.l3.hit, resp_res.l3.perm(idx), resp_res.sp.perm))
495  io.resp.bits.toHptw.resp.entry.v := Mux(resp_res.l3.hit, resp_res.l3.v(idx), resp_res.sp.v)
496  io.resp.bits.toHptw.resp.gpf := !io.resp.bits.toHptw.resp.entry.v
497  io.resp.bits.toHptw.resp.gaf := false.B
498
499  io.resp.bits.toTlb.entry.map(_.tag := stageResp.bits.req_info.vpn(vpnLen - 1, 3))
500  io.resp.bits.toTlb.entry.map(_.asid := Mux(stageResp.bits.req_info.hasS2xlate(), io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid)) // DontCare
501  io.resp.bits.toTlb.entry.map(_.vmid.map(_ := io.csr_dup(0).hgatp.asid))
502  io.resp.bits.toTlb.entry.map(_.level.map(_ := Mux(resp_res.l3.hit, 2.U, resp_res.sp.level)))
503  io.resp.bits.toTlb.entry.map(_.prefetch := from_pre(stageResp.bits.req_info.source))
504  for (i <- 0 until tlbcontiguous) {
505    io.resp.bits.toTlb.entry(i).ppn := Mux(resp_res.l3.hit, resp_res.l3.ppn(i)(ppnLen - 1, sectortlbwidth), resp_res.sp.ppn(ppnLen - 1, sectortlbwidth))
506    io.resp.bits.toTlb.entry(i).ppn_low := Mux(resp_res.l3.hit, resp_res.l3.ppn(i)(sectortlbwidth - 1, 0), resp_res.sp.ppn(sectortlbwidth - 1, 0))
507    io.resp.bits.toTlb.entry(i).perm.map(_ := Mux(resp_res.l3.hit, resp_res.l3.perm(i), resp_res.sp.perm))
508    io.resp.bits.toTlb.entry(i).v := Mux(resp_res.l3.hit, resp_res.l3.v(i), resp_res.sp.v)
509    io.resp.bits.toTlb.entry(i).pf := !io.resp.bits.toTlb.entry(i).v
510    io.resp.bits.toTlb.entry(i).af := false.B
511  }
512  io.resp.bits.toTlb.pteidx := UIntToOH(stageResp.bits.req_info.vpn(2, 0)).asBools
513  io.resp.bits.toTlb.not_super := Mux(resp_res.l3.hit, true.B, false.B)
514  io.resp.valid := stageResp.valid
515  XSError(stageResp.valid && resp_res.l3.hit && resp_res.sp.hit, "normal page and super page both hit")
516  XSError(stageResp.valid && io.resp.bits.hit && bypassed(2), "page cache, bypassed but hit")
517
518  // refill Perf
519  val l1RefillPerf = Wire(Vec(l2tlbParams.l1Size, Bool()))
520  val l2RefillPerf = Wire(Vec(l2tlbParams.l2nWays, Bool()))
521  val l3RefillPerf = Wire(Vec(l2tlbParams.l3nWays, Bool()))
522  val spRefillPerf = Wire(Vec(l2tlbParams.spSize, Bool()))
523  l1RefillPerf.map(_ := false.B)
524  l2RefillPerf.map(_ := false.B)
525  l3RefillPerf.map(_ := false.B)
526  spRefillPerf.map(_ := false.B)
527
528  // refill
529  l2.io.w.req <> DontCare
530  l3.io.w.req <> DontCare
531  l2.io.w.req.valid := false.B
532  l3.io.w.req.valid := false.B
533
534  val memRdata = refill.ptes
535  val memPtes = (0 until (l2tlbParams.blockBytes/(XLEN/8))).map(i => memRdata((i+1)*XLEN-1, i*XLEN).asTypeOf(new PteBundle))
536  val memSelData = io.refill.bits.sel_pte_dup
537  val memPte = memSelData.map(a => a.asTypeOf(new PteBundle))
538
539  // TODO: handle sfenceLatch outsize
540  when (!flush_dup(0) && refill.levelOH.l1 && !memPte(0).isLeaf() && !memPte(0).isPf(refill.level_dup(0)) && !memPte(0).isAf()) {
541    // val refillIdx = LFSR64()(log2Up(l2tlbParams.l1Size)-1,0) // TODO: may be LRU
542    val refillIdx = replaceWrapper(l1v, ptwl1replace.way)
543    refillIdx.suggestName(s"PtwL1RefillIdx")
544    val rfOH = UIntToOH(refillIdx)
545    l1(refillIdx).refill(
546      refill.req_info_dup(0).vpn,
547      Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid),
548      io.csr_dup(0).hgatp.asid,
549      memSelData(0),
550      0.U,
551      refill_prefetch_dup(0)
552    )
553    ptwl1replace.access(refillIdx)
554    l1v := l1v | rfOH
555    l1g := (l1g & ~rfOH) | Mux(memPte(0).perm.g, rfOH, 0.U)
556    l1h(refillIdx) := refill.req_info_dup(0).s2xlate
557
558    for (i <- 0 until l2tlbParams.l1Size) {
559      l1RefillPerf(i) := i.U === refillIdx
560    }
561
562    XSDebug(p"[l1 refill] refillIdx:${refillIdx} refillEntry:${l1(refillIdx).genPtwEntry(refill.req_info_dup(0).vpn, Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid), memSelData(0), 0.U, prefetch = refill_prefetch_dup(0))}\n")
563    XSDebug(p"[l1 refill] l1v:${Binary(l1v)}->${Binary(l1v | rfOH)} l1g:${Binary(l1g)}->${Binary((l1g & ~rfOH) | Mux(memPte(0).perm.g, rfOH, 0.U))}\n")
564
565    refillIdx.suggestName(s"l1_refillIdx")
566    rfOH.suggestName(s"l1_rfOH")
567  }
568
569  when (!flush_dup(1) && refill.levelOH.l2 && !memPte(1).isLeaf() && !memPte(1).isPf(refill.level_dup(1)) && !memPte(1).isAf()) {
570    val refillIdx = genPtwL2SetIdx(refill.req_info_dup(1).vpn)
571    val victimWay = replaceWrapper(getl2vSet(refill.req_info_dup(1).vpn), ptwl2replace.way(refillIdx))
572    val victimWayOH = UIntToOH(victimWay)
573    val rfvOH = UIntToOH(Cat(refillIdx, victimWay))
574    val wdata = Wire(l2EntryType)
575    wdata.gen(
576      vpn = refill.req_info_dup(1).vpn,
577      asid = Mux(refill.req_info_dup(1).s2xlate =/= noS2xlate, io.csr_dup(1).vsatp.asid, io.csr_dup(1).satp.asid),
578      vmid = io.csr_dup(1).hgatp.asid,
579      data = memRdata,
580      levelUInt = 1.U,
581      refill_prefetch_dup(1)
582    )
583    l2.io.w.apply(
584      valid = true.B,
585      setIdx = refillIdx,
586      data = wdata,
587      waymask = victimWayOH
588    )
589    ptwl2replace.access(refillIdx, victimWay)
590    l2v := l2v | rfvOH
591    l2g := l2g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U)
592    l2h(refillIdx)(victimWay) := refill.req_info_dup(1).s2xlate
593
594    for (i <- 0 until l2tlbParams.l2nWays) {
595      l2RefillPerf(i) := i.U === victimWay
596    }
597
598    XSDebug(p"[l2 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n")
599    XSDebug(p"[l2 refill] refilldata:0x${wdata}\n")
600    XSDebug(p"[l2 refill] l2v:${Binary(l2v)} -> ${Binary(l2v | rfvOH)}\n")
601    XSDebug(p"[l2 refill] l2g:${Binary(l2g)} -> ${Binary(l2g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n")
602
603    refillIdx.suggestName(s"l2_refillIdx")
604    victimWay.suggestName(s"l2_victimWay")
605    victimWayOH.suggestName(s"l2_victimWayOH")
606    rfvOH.suggestName(s"l2_rfvOH")
607  }
608
609  when (!flush_dup(2) && refill.levelOH.l3 && !memPte(2).isAf()) {
610    val refillIdx = genPtwL3SetIdx(refill.req_info_dup(2).vpn)
611    val victimWay = replaceWrapper(getl3vSet(refill.req_info_dup(2).vpn), ptwl3replace.way(refillIdx))
612    val victimWayOH = UIntToOH(victimWay)
613    val rfvOH = UIntToOH(Cat(refillIdx, victimWay))
614    val wdata = Wire(l3EntryType)
615    wdata.gen(
616      vpn =  refill.req_info_dup(2).vpn,
617      asid = Mux(refill.req_info_dup(2).s2xlate =/= noS2xlate, io.csr_dup(2).vsatp.asid, io.csr_dup(2).satp.asid),
618      vmid = io.csr_dup(2).hgatp.asid,
619      data = memRdata,
620      levelUInt = 2.U,
621      refill_prefetch_dup(2)
622    )
623    l3.io.w.apply(
624      valid = true.B,
625      setIdx = refillIdx,
626      data = wdata,
627      waymask = victimWayOH
628    )
629    ptwl3replace.access(refillIdx, victimWay)
630    l3v := l3v | rfvOH
631    l3g := l3g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U)
632    l3h(refillIdx)(victimWay) := refill.req_info_dup(2).s2xlate
633
634    for (i <- 0 until l2tlbParams.l3nWays) {
635      l3RefillPerf(i) := i.U === victimWay
636    }
637
638    XSDebug(p"[l3 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n")
639    XSDebug(p"[l3 refill] refilldata:0x${wdata}\n")
640    XSDebug(p"[l3 refill] l3v:${Binary(l3v)} -> ${Binary(l3v | rfvOH)}\n")
641    XSDebug(p"[l3 refill] l3g:${Binary(l3g)} -> ${Binary(l3g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n")
642
643    refillIdx.suggestName(s"l3_refillIdx")
644    victimWay.suggestName(s"l3_victimWay")
645    victimWayOH.suggestName(s"l3_victimWayOH")
646    rfvOH.suggestName(s"l3_rfvOH")
647  }
648
649
650  // misc entries: super & invalid
651  when (!flush_dup(0) && refill.levelOH.sp && (memPte(0).isLeaf() || memPte(0).isPf(refill.level_dup(0))) && !memPte(0).isAf()) {
652    val refillIdx = spreplace.way// LFSR64()(log2Up(l2tlbParams.spSize)-1,0) // TODO: may be LRU
653    val rfOH = UIntToOH(refillIdx)
654    sp(refillIdx).refill(
655      refill.req_info_dup(0).vpn,
656      Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid),
657      io.csr_dup(0).hgatp.asid,
658      memSelData(0),
659      refill.level_dup(2),
660      refill_prefetch_dup(0),
661      !memPte(0).isPf(refill.level_dup(0)),
662    )
663    spreplace.access(refillIdx)
664    spv := spv | rfOH
665    spg := spg & ~rfOH | Mux(memPte(0).perm.g, rfOH, 0.U)
666    sph(refillIdx) := refill.req_info_dup(0).s2xlate
667
668    for (i <- 0 until l2tlbParams.spSize) {
669      spRefillPerf(i) := i.U === refillIdx
670    }
671
672    XSDebug(p"[sp refill] refillIdx:${refillIdx} refillEntry:${sp(refillIdx).genPtwEntry(refill.req_info_dup(0).vpn, Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid), memSelData(0), refill.level_dup(0), refill_prefetch_dup(0))}\n")
673    XSDebug(p"[sp refill] spv:${Binary(spv)}->${Binary(spv | rfOH)} spg:${Binary(spg)}->${Binary(spg & ~rfOH | Mux(memPte(0).perm.g, rfOH, 0.U))}\n")
674
675    refillIdx.suggestName(s"sp_refillIdx")
676    rfOH.suggestName(s"sp_rfOH")
677  }
678
679  val l2eccFlush = resp_res.l2.ecc && stageResp_valid_1cycle_dup(0) // RegNext(l2eccError, init = false.B)
680  val l3eccFlush = resp_res.l3.ecc && stageResp_valid_1cycle_dup(1) // RegNext(l3eccError, init = false.B)
681  val eccVpn = stageResp.bits.req_info.vpn
682
683  XSError(l2eccFlush, "l2tlb.cache.l2 ecc error. Should not happen at sim stage")
684  XSError(l3eccFlush, "l2tlb.cache.l3 ecc error. Should not happen at sim stage")
685  when (l2eccFlush) {
686    val flushSetIdxOH = UIntToOH(genPtwL2SetIdx(eccVpn))
687    val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l2nWays, a.asUInt) }).asUInt
688    l2v := l2v & ~flushMask
689    l2g := l2g & ~flushMask
690  }
691
692  when (l3eccFlush) {
693    val flushSetIdxOH = UIntToOH(genPtwL3SetIdx(eccVpn))
694    val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l3nWays, a.asUInt) }).asUInt
695    l3v := l3v & ~flushMask
696    l3g := l3g & ~flushMask
697  }
698
699  // sfence for l3
700  val sfence_valid_l3 = sfence_dup(3).valid && !sfence_dup(3).bits.hg && !sfence_dup(3).bits.hv
701  when (sfence_valid_l3) {
702    val l3hhit = VecInit(l3h.flatMap(_.map(_ === onlyStage1 && io.csr_dup(0).priv.virt || !io.csr_dup(0).priv.virt))).asUInt
703    val sfence_vpn = sfence_dup(3).bits.addr(sfence_dup(3).bits.addr.getWidth-1, offLen)
704    when (sfence_dup(3).bits.rs1/*va*/) {
705      when (sfence_dup(3).bits.rs2) {
706        // all va && all asid
707        l3v := l3v & ~l3hhit
708      } .otherwise {
709        // all va && specific asid except global
710        l3v := l3v & l3g & ~l3hhit
711      }
712    } .otherwise {
713      // val flushMask = UIntToOH(genTlbL2Idx(sfence.bits.addr(sfence.bits.addr.getWidth-1, offLen)))
714      val flushSetIdxOH = UIntToOH(genPtwL3SetIdx(sfence_vpn))
715      // val flushMask = VecInit(flushSetIdxOH.asBools.map(Fill(l2tlbParams.l3nWays, _.asUInt))).asUInt
716      val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l3nWays, a.asUInt) }).asUInt
717      flushSetIdxOH.suggestName(s"sfence_nrs1_flushSetIdxOH")
718      flushMask.suggestName(s"sfence_nrs1_flushMask")
719
720      when (sfence_dup(3).bits.rs2) {
721        // specific leaf of addr && all asid
722        l3v := l3v & ~flushMask & ~l3hhit
723      } .otherwise {
724        // specific leaf of addr && specific asid
725        l3v := l3v & (~flushMask | l3g | ~l3hhit)
726      }
727    }
728  }
729
730  // hfencev, simple implementation for l3
731  val hfencev_valid_l3 = sfence_dup(3).valid && sfence_dup(3).bits.hv
732  when(hfencev_valid_l3) {
733    val flushMask = VecInit(l3h.flatMap(_.map(_  === onlyStage1))).asUInt
734    l3v := l3v & ~flushMask // all VS-stage l3 pte
735  }
736
737  // hfenceg, simple implementation for l3
738  val hfenceg_valid_l3 = sfence_dup(3).valid && sfence_dup(3).bits.hg
739  when(hfenceg_valid_l3) {
740    val flushMask = VecInit(l3h.flatMap(_.map(_ === onlyStage2))).asUInt
741    l3v := l3v & ~flushMask // all G-stage l3 pte
742  }
743
744
745  val l1asidhit = VecInit(l1asids.map(_ === sfence_dup(0).bits.id)).asUInt
746  val spasidhit = VecInit(spasids.map(_ === sfence_dup(0).bits.id)).asUInt
747  val sfence_valid = sfence_dup(0).valid && !sfence_dup(0).bits.hg && !sfence_dup(0).bits.hv
748  when (sfence_valid) {
749    val l1vmidhit = VecInit(l1vmids.map(_.getOrElse(0.U) === io.csr_dup(0).hgatp.asid)).asUInt
750    val spvmidhit = VecInit(spvmids.map(_.getOrElse(0.U) === io.csr_dup(0).hgatp.asid)).asUInt
751    val l1hhit = VecInit(l1h.map{a => io.csr_dup(0).priv.virt && a === onlyStage1 || !io.csr_dup(0).priv.virt && a === noS2xlate}).asUInt
752    val sphhit = VecInit(sph.map{a => io.csr_dup(0).priv.virt && a === onlyStage1 || !io.csr_dup(0).priv.virt && a === noS2xlate}).asUInt
753    val l2hhit = VecInit(l2h.flatMap(_.map{a => io.csr_dup(0).priv.virt && a === onlyStage1 || !io.csr_dup(0).priv.virt && a === noS2xlate})).asUInt
754    val sfence_vpn = sfence_dup(0).bits.addr(sfence_dup(0).bits.addr.getWidth-1, offLen)
755
756    when (sfence_dup(0).bits.rs1/*va*/) {
757      when (sfence_dup(0).bits.rs2) {
758        // all va && all asid
759        l2v := l2v & ~l2hhit
760        l1v := l1v & ~(l1hhit & VecInit(l1vmidhit.asBools.map{a => io.csr_dup(0).priv.virt && a || !io.csr_dup(0).priv.virt}).asUInt)
761        spv := spv & ~(sphhit & VecInit(spvmidhit.asBools.map{a => io.csr_dup(0).priv.virt && a || !io.csr_dup(0).priv.virt}).asUInt)
762      } .otherwise {
763        // all va && specific asid except global
764        l2v := l2v & (l2g | ~l2hhit)
765        l1v := l1v & ~(~l1g & l1hhit & l1asidhit & VecInit(l1vmidhit.asBools.map{a => io.csr_dup(0).priv.virt && a || !io.csr_dup(0).priv.virt}).asUInt)
766        spv := spv & ~(~spg & sphhit & spasidhit & VecInit(spvmidhit.asBools.map{a => io.csr_dup(0).priv.virt && a || !io.csr_dup(0).priv.virt}).asUInt)
767      }
768    } .otherwise {
769      when (sfence_dup(0).bits.rs2) {
770        // specific leaf of addr && all asid
771        spv := spv & ~(sphhit & VecInit(sp.map(_.hit(sfence_vpn, sfence_dup(0).bits.id, sfence_dup(0).bits.id, io.csr_dup(0).hgatp.asid, ignoreAsid = true, s2xlate = io.csr_dup(0).priv.virt))).asUInt)
772      } .otherwise {
773        // specific leaf of addr && specific asid
774        spv := spv & ~(~spg & sphhit & VecInit(sp.map(_.hit(sfence_vpn, sfence_dup(0).bits.id, sfence_dup(0).bits.id, io.csr_dup(0).hgatp.asid, s2xlate = io.csr_dup(0).priv.virt))).asUInt)
775      }
776    }
777  }
778
779  val hfencev_valid = sfence_dup(0).valid && sfence_dup(0).bits.hv
780  when (hfencev_valid) {
781    val l1vmidhit = VecInit(l1vmids.map(_.getOrElse(0.U) === io.csr_dup(0).hgatp.asid)).asUInt
782    val spvmidhit = VecInit(spvmids.map(_.getOrElse(0.U) === io.csr_dup(0).hgatp.asid)).asUInt
783    val l1hhit = VecInit(l1h.map(_ === onlyStage1)).asUInt
784    val sphhit = VecInit(sph.map(_ === onlyStage1)).asUInt
785    val l2hhit = VecInit(l2h.flatMap(_.map(_ === onlyStage1))).asUInt
786    val hfencev_vpn = sfence_dup(0).bits.addr(sfence_dup(0).bits.addr.getWidth-1, offLen)
787    when(sfence_dup(0).bits.rs1) {
788      when(sfence_dup(0).bits.rs2) {
789        l2v := l2v & ~l2hhit
790        l1v := l1v & ~(l1hhit & l1vmidhit)
791        spv := spv & ~(sphhit & spvmidhit)
792      }.otherwise {
793        l2v := l2v & (l2g | ~l2hhit)
794        l1v := l1v & ~(~l1g & l1hhit & l1asidhit & l1vmidhit)
795        spv := spv & ~(~spg & sphhit & spasidhit & spvmidhit)
796      }
797    }.otherwise {
798      when(sfence_dup(0).bits.rs2) {
799        spv := spv & ~(sphhit & VecInit(sp.map(_.hit(hfencev_vpn, sfence_dup(0).bits.id, sfence_dup(0).bits.id, io.csr_dup(0).hgatp.asid, ignoreAsid = true, s2xlate = true.B))).asUInt)
800      }.otherwise {
801        spv := spv & ~(~spg & sphhit & VecInit(sp.map(_.hit(hfencev_vpn, sfence_dup(0).bits.id, sfence_dup(0).bits.id, io.csr_dup(0).hgatp.asid, s2xlate = true.B))).asUInt)
802      }
803    }
804  }
805
806
807  val hfenceg_valid = sfence_dup(0).valid && sfence_dup(0).bits.hg
808  when(hfenceg_valid) {
809    val l1vmidhit = VecInit(l1vmids.map(_.getOrElse(0.U) === sfence_dup(0).bits.id)).asUInt
810    val spvmidhit = VecInit(spvmids.map(_.getOrElse(0.U) === sfence_dup(0).bits.id)).asUInt
811    val l1hhit = VecInit(l1h.map(_ === onlyStage2)).asUInt
812    val sphhit = VecInit(sph.map(_ === onlyStage2)).asUInt
813    val l2hhit = VecInit(l2h.flatMap(_.map(_ === onlyStage2))).asUInt
814    val hfenceg_gvpn = (sfence_dup(0).bits.addr << 2)(sfence_dup(0).bits.addr.getWidth - 1, offLen)
815    when(sfence_dup(0).bits.rs1) {
816      when(sfence_dup(0).bits.rs2) {
817        l2v := l2v & ~l2hhit
818        l1v := l1v & ~l1hhit
819        spv := spv & ~sphhit
820      }.otherwise {
821        l2v := l2v & ~l2hhit
822        l1v := l1v & ~(l1hhit & l1vmidhit)
823        spv := spv & ~(sphhit & spvmidhit)
824      }
825    }.otherwise {
826      when(sfence_dup(0).bits.rs2) {
827        spv := spv & ~(sphhit & VecInit(sp.map(_.hit(hfenceg_gvpn, 0.U, 0.U, sfence_dup(0).bits.id, ignoreAsid = true, s2xlate = true.B))).asUInt)
828      }.otherwise {
829        spv := spv & ~(~spg & sphhit & VecInit(sp.map(_.hit(hfenceg_gvpn, 0.U, 0.U, sfence_dup(0).bits.id, ignoreAsid = true, s2xlate = false.B))).asUInt)
830      }
831    }
832  }
833
834  def InsideStageConnect(in: DecoupledIO[PtwCacheReq], out: DecoupledIO[PtwCacheReq], inFire: Bool): Unit = {
835    in.ready := !in.valid || out.ready
836    out.valid := in.valid
837    out.bits := in.bits
838    out.bits.bypassed.zip(in.bits.bypassed).zipWithIndex.map{ case (b, i) =>
839      val bypassed_reg = Reg(Bool())
840      val bypassed_wire = refill_bypass(in.bits.req_info.vpn, i, in.bits.req_info.s2xlate) && io.refill.valid
841      when (inFire) { bypassed_reg := bypassed_wire }
842      .elsewhen (io.refill.valid) { bypassed_reg := bypassed_reg || bypassed_wire }
843
844      b._1 := b._2 || (bypassed_wire || (bypassed_reg && !inFire))
845    }
846  }
847
848  // Perf Count
849  val resp_l3 = resp_res.l3.hit
850  val resp_sp = resp_res.sp.hit
851  val resp_l1_pre = resp_res.l1.pre
852  val resp_l2_pre = resp_res.l2.pre
853  val resp_l3_pre = resp_res.l3.pre
854  val resp_sp_pre = resp_res.sp.pre
855  val base_valid_access_0 = !from_pre(io.resp.bits.req_info.source) && io.resp.fire
856  XSPerfAccumulate("access", base_valid_access_0)
857  XSPerfAccumulate("l1_hit", base_valid_access_0 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
858  XSPerfAccumulate("l2_hit", base_valid_access_0 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
859  XSPerfAccumulate("l3_hit", base_valid_access_0 && resp_l3)
860  XSPerfAccumulate("sp_hit", base_valid_access_0 && resp_sp)
861  XSPerfAccumulate("pte_hit",base_valid_access_0 && io.resp.bits.hit)
862
863  XSPerfAccumulate("l1_hit_pre", base_valid_access_0 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
864  XSPerfAccumulate("l2_hit_pre", base_valid_access_0 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
865  XSPerfAccumulate("l3_hit_pre", base_valid_access_0 && resp_l3_pre && resp_l3)
866  XSPerfAccumulate("sp_hit_pre", base_valid_access_0 && resp_sp_pre && resp_sp)
867  XSPerfAccumulate("pte_hit_pre",base_valid_access_0 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit)
868
869  val base_valid_access_1 = from_pre(io.resp.bits.req_info.source) && io.resp.fire
870  XSPerfAccumulate("pre_access", base_valid_access_1)
871  XSPerfAccumulate("pre_l1_hit", base_valid_access_1 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
872  XSPerfAccumulate("pre_l2_hit", base_valid_access_1 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
873  XSPerfAccumulate("pre_l3_hit", base_valid_access_1 && resp_l3)
874  XSPerfAccumulate("pre_sp_hit", base_valid_access_1 && resp_sp)
875  XSPerfAccumulate("pre_pte_hit",base_valid_access_1 && io.resp.bits.hit)
876
877  XSPerfAccumulate("pre_l1_hit_pre", base_valid_access_1 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
878  XSPerfAccumulate("pre_l2_hit_pre", base_valid_access_1 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
879  XSPerfAccumulate("pre_l3_hit_pre", base_valid_access_1 && resp_l3_pre && resp_l3)
880  XSPerfAccumulate("pre_sp_hit_pre", base_valid_access_1 && resp_sp_pre && resp_sp)
881  XSPerfAccumulate("pre_pte_hit_pre",base_valid_access_1 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit)
882
883  val base_valid_access_2 = stageResp.bits.isFirst && !from_pre(io.resp.bits.req_info.source) && io.resp.fire
884  XSPerfAccumulate("access_first", base_valid_access_2)
885  XSPerfAccumulate("l1_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
886  XSPerfAccumulate("l2_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
887  XSPerfAccumulate("l3_hit_first", base_valid_access_2 && resp_l3)
888  XSPerfAccumulate("sp_hit_first", base_valid_access_2 && resp_sp)
889  XSPerfAccumulate("pte_hit_first",base_valid_access_2 && io.resp.bits.hit)
890
891  XSPerfAccumulate("l1_hit_pre_first", base_valid_access_2 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
892  XSPerfAccumulate("l2_hit_pre_first", base_valid_access_2 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
893  XSPerfAccumulate("l3_hit_pre_first", base_valid_access_2 && resp_l3_pre && resp_l3)
894  XSPerfAccumulate("sp_hit_pre_first", base_valid_access_2 && resp_sp_pre && resp_sp)
895  XSPerfAccumulate("pte_hit_pre_first",base_valid_access_2 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit)
896
897  val base_valid_access_3 = stageResp.bits.isFirst && from_pre(io.resp.bits.req_info.source) && io.resp.fire
898  XSPerfAccumulate("pre_access_first", base_valid_access_3)
899  XSPerfAccumulate("pre_l1_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
900  XSPerfAccumulate("pre_l2_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
901  XSPerfAccumulate("pre_l3_hit_first", base_valid_access_3 && resp_l3)
902  XSPerfAccumulate("pre_sp_hit_first", base_valid_access_3 && resp_sp)
903  XSPerfAccumulate("pre_pte_hit_first", base_valid_access_3 && io.resp.bits.hit)
904
905  XSPerfAccumulate("pre_l1_hit_pre_first", base_valid_access_3 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
906  XSPerfAccumulate("pre_l2_hit_pre_first", base_valid_access_3 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
907  XSPerfAccumulate("pre_l3_hit_pre_first", base_valid_access_3 && resp_l3_pre && resp_l3)
908  XSPerfAccumulate("pre_sp_hit_pre_first", base_valid_access_3 && resp_sp_pre && resp_sp)
909  XSPerfAccumulate("pre_pte_hit_pre_first",base_valid_access_3 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit)
910
911  XSPerfAccumulate("rwHarzad", io.req.valid && !io.req.ready)
912  XSPerfAccumulate("out_blocked", io.resp.valid && !io.resp.ready)
913  l1AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L1AccessIndex${i}", l) }
914  l2AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L2AccessIndex${i}", l) }
915  l3AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L3AccessIndex${i}", l) }
916  spAccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPAccessIndex${i}", l) }
917  l1RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L1RefillIndex${i}", l) }
918  l2RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L2RefillIndex${i}", l) }
919  l3RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L3RefillIndex${i}", l) }
920  spRefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPRefillIndex${i}", l) }
921
922  XSPerfAccumulate("l1Refill", Cat(l1RefillPerf).orR)
923  XSPerfAccumulate("l2Refill", Cat(l2RefillPerf).orR)
924  XSPerfAccumulate("l3Refill", Cat(l3RefillPerf).orR)
925  XSPerfAccumulate("spRefill", Cat(spRefillPerf).orR)
926  XSPerfAccumulate("l1Refill_pre", Cat(l1RefillPerf).orR && refill_prefetch_dup(0))
927  XSPerfAccumulate("l2Refill_pre", Cat(l2RefillPerf).orR && refill_prefetch_dup(0))
928  XSPerfAccumulate("l3Refill_pre", Cat(l3RefillPerf).orR && refill_prefetch_dup(0))
929  XSPerfAccumulate("spRefill_pre", Cat(spRefillPerf).orR && refill_prefetch_dup(0))
930
931  // debug
932  XSDebug(sfence_dup(0).valid, p"[sfence] original v and g vector:\n")
933  XSDebug(sfence_dup(0).valid, p"[sfence] l1v:${Binary(l1v)}\n")
934  XSDebug(sfence_dup(0).valid, p"[sfence] l2v:${Binary(l2v)}\n")
935  XSDebug(sfence_dup(0).valid, p"[sfence] l3v:${Binary(l3v)}\n")
936  XSDebug(sfence_dup(0).valid, p"[sfence] l3g:${Binary(l3g)}\n")
937  XSDebug(sfence_dup(0).valid, p"[sfence] spv:${Binary(spv)}\n")
938  XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] new v and g vector:\n")
939  XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l1v:${Binary(l1v)}\n")
940  XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l2v:${Binary(l2v)}\n")
941  XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l3v:${Binary(l3v)}\n")
942  XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l3g:${Binary(l3g)}\n")
943  XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] spv:${Binary(spv)}\n")
944
945  val perfEvents = Seq(
946    ("access           ", base_valid_access_0             ),
947    ("l1_hit           ", l1Hit                           ),
948    ("l2_hit           ", l2Hit                           ),
949    ("l3_hit           ", l3Hit                           ),
950    ("sp_hit           ", spHit                           ),
951    ("pte_hit          ", l3Hit || spHit                  ),
952    ("rwHarzad         ",  io.req.valid && !io.req.ready  ),
953    ("out_blocked      ",  io.resp.valid && !io.resp.ready),
954  )
955  generatePerfEvent()
956}
957