1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.cache.mmu 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29 30/* ptw cache caches the page table of all the three layers 31 * ptw cache resp at next cycle 32 * the cache should not be blocked 33 * when miss queue if full, just block req outside 34 */ 35 36class PageCachePerPespBundle(implicit p: Parameters) extends PtwBundle { 37 val hit = Bool() 38 val pre = Bool() 39 val ppn = UInt(gvpnLen.W) 40 val pbmt = UInt(ptePbmtLen.W) 41 val perm = new PtePermBundle() 42 val ecc = Bool() 43 val level = UInt(2.W) 44 val v = Bool() 45 46 def apply(hit: Bool, pre: Bool, ppn: UInt, pbmt: UInt = 0.U, 47 perm: PtePermBundle = 0.U.asTypeOf(new PtePermBundle()), 48 ecc: Bool = false.B, level: UInt = 0.U, valid: Bool = true.B): Unit = { 49 this.hit := hit && !ecc 50 this.pre := pre 51 this.ppn := ppn 52 this.pbmt := pbmt 53 this.perm := perm 54 this.ecc := ecc && hit 55 this.level := level 56 this.v := valid 57 } 58} 59 60class PageCacheMergePespBundle(implicit p: Parameters) extends PtwBundle { 61 assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!") 62 val hit = Bool() 63 val pre = Bool() 64 val ppn = Vec(tlbcontiguous, UInt(gvpnLen.W)) 65 val pbmt = Vec(tlbcontiguous, UInt(ptePbmtLen.W)) 66 val perm = Vec(tlbcontiguous, new PtePermBundle()) 67 val ecc = Bool() 68 val level = UInt(2.W) 69 val v = Vec(tlbcontiguous, Bool()) 70 val af = Vec(tlbcontiguous, Bool()) 71 72 def apply(hit: Bool, pre: Bool, ppn: Vec[UInt], pbmt: Vec[UInt] = Vec(tlbcontiguous, 0.U), 73 perm: Vec[PtePermBundle] = Vec(tlbcontiguous, 0.U.asTypeOf(new PtePermBundle())), 74 ecc: Bool = false.B, level: UInt = 0.U, valid: Vec[Bool] = Vec(tlbcontiguous, true.B), 75 accessFault: Vec[Bool] = Vec(tlbcontiguous, true.B)): Unit = { 76 this.hit := hit && !ecc 77 this.pre := pre 78 this.ppn := ppn 79 this.pbmt := pbmt 80 this.perm := perm 81 this.ecc := ecc && hit 82 this.level := level 83 this.v := valid 84 this.af := accessFault 85 } 86} 87 88class PageCacheRespBundle(implicit p: Parameters) extends PtwBundle { 89 val l3 = if (EnableSv48) Some(new PageCachePerPespBundle) else None 90 val l2 = new PageCachePerPespBundle 91 val l1 = new PageCachePerPespBundle 92 val l0 = new PageCacheMergePespBundle 93 val sp = new PageCachePerPespBundle 94} 95 96class PtwCacheReq(implicit p: Parameters) extends PtwBundle { 97 val req_info = new L2TlbInnerBundle() 98 val isFirst = Bool() 99 val bypassed = if (EnableSv48) Vec(4, Bool()) else Vec(3, Bool()) 100 val isHptwReq = Bool() 101 val hptwId = UInt(log2Up(l2tlbParams.llptwsize).W) 102} 103 104class PtwCacheIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 105 val req = Flipped(DecoupledIO(new PtwCacheReq())) 106 val resp = DecoupledIO(new Bundle { 107 val req_info = new L2TlbInnerBundle() 108 val isFirst = Bool() 109 val hit = Bool() 110 val prefetch = Bool() // is the entry fetched by prefetch 111 val bypassed = Bool() 112 val toFsm = new Bundle { 113 val l3Hit = if (EnableSv48) Some(Bool()) else None 114 val l2Hit = Bool() 115 val l1Hit = Bool() 116 val ppn = UInt(gvpnLen.W) 117 val stage1Hit = Bool() // find stage 1 pte in cache, but need to search stage 2 pte in cache at PTW 118 } 119 val stage1 = new PtwMergeResp() 120 val isHptwReq = Bool() 121 val toHptw = new Bundle { 122 val l3Hit = if (EnableSv48) Some(Bool()) else None 123 val l2Hit = Bool() 124 val l1Hit = Bool() 125 val ppn = UInt(ppnLen.W) 126 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 127 val resp = new HptwResp() // used if hit 128 val bypassed = Bool() 129 } 130 }) 131 val refill = Flipped(ValidIO(new Bundle { 132 val ptes = UInt(blockBits.W) 133 val levelOH = new Bundle { 134 // NOTE: levelOH has (Level+1) bits, each stands for page cache entries 135 val sp = Bool() 136 val l0 = Bool() 137 val l1 = Bool() 138 val l2 = Bool() 139 val l3 = if (EnableSv48) Some(Bool()) else None 140 def apply(levelUInt: UInt, valid: Bool) = { 141 sp := GatedValidRegNext((levelUInt === 1.U || levelUInt === 2.U || levelUInt === 3.U) && valid, false.B) 142 l0 := GatedValidRegNext((levelUInt === 0.U) & valid, false.B) 143 l1 := GatedValidRegNext((levelUInt === 1.U) & valid, false.B) 144 l2 := GatedValidRegNext((levelUInt === 2.U) & valid, false.B) 145 l3.map(_ := GatedValidRegNext((levelUInt === 3.U) & valid, false.B)) 146 } 147 } 148 // duplicate level and sel_pte for each page caches, for better fanout 149 val req_info_dup = Vec(3, new L2TlbInnerBundle()) 150 val level_dup = Vec(3, UInt(log2Up(Level + 1).W)) 151 val sel_pte_dup = Vec(3, UInt(XLEN.W)) 152 })) 153 val sfence_dup = Vec(4, Input(new SfenceBundle())) 154 val csr_dup = Vec(3, Input(new TlbCsrBundle())) 155} 156 157class PtwCache()(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents { 158 val io = IO(new PtwCacheIO) 159 val ecc = Code.fromString(l2tlbParams.ecc) 160 val l1EntryType = new PTWEntriesWithEcc(ecc, num = PtwL1SectorSize, tagLen = PtwL1TagLen, level = 1, hasPerm = false) 161 val l0EntryType = new PTWEntriesWithEcc(ecc, num = PtwL0SectorSize, tagLen = PtwL0TagLen, level = 0, hasPerm = true) 162 163 // TODO: four caches make the codes dirty, think about how to deal with it 164 165 val sfence_dup = io.sfence_dup 166 val refill = io.refill.bits 167 val refill_prefetch_dup = io.refill.bits.req_info_dup.map(a => from_pre(a.source)) 168 val refill_h = io.refill.bits.req_info_dup.map(a => Mux(a.s2xlate === allStage, onlyStage1, a.s2xlate)) 169 val flush_dup = sfence_dup.zip(io.csr_dup).map(f => f._1.valid || f._2.satp.changed || f._2.vsatp.changed || f._2.hgatp.changed) 170 val flush = flush_dup(0) 171 172 // when refill, refuce to accept new req 173 val rwHarzad = if (sramSinglePort) io.refill.valid else false.B 174 175 // handle hand signal and req_info 176 // TODO: replace with FlushableQueue 177 val stageReq = Wire(Decoupled(new PtwCacheReq())) // enq stage & read page cache valid 178 val stageDelay = Wire(Vec(2, Decoupled(new PtwCacheReq()))) // page cache resp 179 val stageCheck = Wire(Vec(2, Decoupled(new PtwCacheReq()))) // check hit & check ecc 180 val stageResp = Wire(Decoupled(new PtwCacheReq())) // deq stage 181 182 val stageDelay_valid_1cycle = OneCycleValid(stageReq.fire, flush) // catch ram data 183 val stageCheck_valid_1cycle = OneCycleValid(stageDelay(1).fire, flush) // replace & perf counter 184 val stageResp_valid_1cycle_dup = Wire(Vec(2, Bool())) 185 stageResp_valid_1cycle_dup.map(_ := OneCycleValid(stageCheck(1).fire, flush)) // ecc flush 186 187 stageReq <> io.req 188 PipelineConnect(stageReq, stageDelay(0), stageDelay(1).ready, flush, rwHarzad) 189 InsideStageConnect(stageDelay(0), stageDelay(1), stageDelay_valid_1cycle) 190 PipelineConnect(stageDelay(1), stageCheck(0), stageCheck(1).ready, flush) 191 InsideStageConnect(stageCheck(0), stageCheck(1), stageCheck_valid_1cycle) 192 PipelineConnect(stageCheck(1), stageResp, io.resp.ready, flush) 193 stageResp.ready := !stageResp.valid || io.resp.ready 194 195 // l3: level 3 non-leaf pte 196 val l3 = if (EnableSv48) Some(Reg(Vec(l2tlbParams.l3Size, new PtwEntry(tagLen = PtwL3TagLen)))) else None 197 val l3v = if (EnableSv48) Some(RegInit(0.U(l2tlbParams.l3Size.W))) else None 198 val l3g = if (EnableSv48) Some(Reg(UInt(l2tlbParams.l3Size.W))) else None 199 val l3asids = if (EnableSv48) Some(l3.get.map(_.asid)) else None 200 val l3vmids = if (EnableSv48) Some(l3.get.map(_.vmid)) else None 201 val l3h = if (EnableSv48) Some(Reg(Vec(l2tlbParams.l3Size, UInt(2.W)))) else None 202 203 // l2: level 2 non-leaf pte 204 val l2 = Reg(Vec(l2tlbParams.l2Size, new PtwEntry(tagLen = PtwL2TagLen))) 205 val l2v = RegInit(0.U(l2tlbParams.l2Size.W)) 206 val l2g = Reg(UInt(l2tlbParams.l2Size.W)) 207 val l2asids = l2.map(_.asid) 208 val l2vmids = l2.map(_.vmid) 209 val l2h = Reg(Vec(l2tlbParams.l2Size, UInt(2.W))) 210 211 // l1: level 1 non-leaf pte 212 val l1 = Module(new SRAMTemplate( 213 l1EntryType, 214 set = l2tlbParams.l1nSets, 215 way = l2tlbParams.l1nWays, 216 singlePort = sramSinglePort 217 )) 218 val l1v = RegInit(0.U((l2tlbParams.l1nSets * l2tlbParams.l1nWays).W)) 219 val l1g = Reg(UInt((l2tlbParams.l1nSets * l2tlbParams.l1nWays).W)) 220 val l1h = Reg(Vec(l2tlbParams.l1nSets, Vec(l2tlbParams.l1nWays, UInt(2.W)))) 221 def getl1vSet(vpn: UInt) = { 222 require(log2Up(l2tlbParams.l1nWays) == log2Down(l2tlbParams.l1nWays)) 223 val set = genPtwL1SetIdx(vpn) 224 require(set.getWidth == log2Up(l2tlbParams.l1nSets)) 225 val l1vVec = l1v.asTypeOf(Vec(l2tlbParams.l1nSets, UInt(l2tlbParams.l1nWays.W))) 226 l1vVec(set) 227 } 228 def getl1hSet(vpn: UInt) = { 229 require(log2Up(l2tlbParams.l1nWays) == log2Down(l2tlbParams.l1nWays)) 230 val set = genPtwL1SetIdx(vpn) 231 require(set.getWidth == log2Up(l2tlbParams.l1nSets)) 232 l1h(set) 233 } 234 235 // l0: level 0 leaf pte of 4KB pages 236 val l0 = Module(new SRAMTemplate( 237 l0EntryType, 238 set = l2tlbParams.l0nSets, 239 way = l2tlbParams.l0nWays, 240 singlePort = sramSinglePort 241 )) 242 val l0v = RegInit(0.U((l2tlbParams.l0nSets * l2tlbParams.l0nWays).W)) 243 val l0g = Reg(UInt((l2tlbParams.l0nSets * l2tlbParams.l0nWays).W)) 244 val l0h = Reg(Vec(l2tlbParams.l0nSets, Vec(l2tlbParams.l0nWays, UInt(2.W)))) 245 def getl0vSet(vpn: UInt) = { 246 require(log2Up(l2tlbParams.l0nWays) == log2Down(l2tlbParams.l0nWays)) 247 val set = genPtwL0SetIdx(vpn) 248 require(set.getWidth == log2Up(l2tlbParams.l0nSets)) 249 val l0vVec = l0v.asTypeOf(Vec(l2tlbParams.l0nSets, UInt(l2tlbParams.l0nWays.W))) 250 l0vVec(set) 251 } 252 def getl0hSet(vpn: UInt) = { 253 require(log2Up(l2tlbParams.l0nWays) == log2Down(l2tlbParams.l0nWays)) 254 val set = genPtwL0SetIdx(vpn) 255 require(set.getWidth == log2Up(l2tlbParams.l0nSets)) 256 l0h(set) 257 } 258 259 // sp: level 1/2/3 leaf pte of 512GB/1GB/2MB super pages 260 val sp = Reg(Vec(l2tlbParams.spSize, new PtwEntry(tagLen = SPTagLen, hasPerm = true, hasLevel = true))) 261 val spv = RegInit(0.U(l2tlbParams.spSize.W)) 262 val spg = Reg(UInt(l2tlbParams.spSize.W)) 263 val spasids = sp.map(_.asid) 264 val spvmids = sp.map(_.vmid) 265 val sph = Reg(Vec(l2tlbParams.spSize, UInt(2.W))) 266 267 // Access Perf 268 val l3AccessPerf = if(EnableSv48) Some(Wire(Vec(l2tlbParams.l3Size, Bool()))) else None 269 val l2AccessPerf = Wire(Vec(l2tlbParams.l2Size, Bool())) 270 val l1AccessPerf = Wire(Vec(l2tlbParams.l1nWays, Bool())) 271 val l0AccessPerf = Wire(Vec(l2tlbParams.l0nWays, Bool())) 272 val spAccessPerf = Wire(Vec(l2tlbParams.spSize, Bool())) 273 if (EnableSv48) l3AccessPerf.map(_.map(_ := false.B)) 274 l2AccessPerf.map(_ := false.B) 275 l1AccessPerf.map(_ := false.B) 276 l0AccessPerf.map(_ := false.B) 277 spAccessPerf.map(_ := false.B) 278 279 280 281 def vpn_match(vpn1: UInt, vpn2: UInt, level: Int) = { 282 (vpn1(vpnLen-1, vpnnLen*level+3) === vpn2(vpnLen-1, vpnnLen*level+3)) 283 } 284 // NOTE: not actually bypassed, just check if hit, re-access the page cache 285 def refill_bypass(vpn: UInt, level: Int, h_search: UInt) = { 286 val change_h = MuxLookup(h_search, noS2xlate)(Seq( 287 allStage -> onlyStage1, 288 onlyStage1 -> onlyStage1, 289 onlyStage2 -> onlyStage2 290 )) 291 val change_refill_h = MuxLookup(io.refill.bits.req_info_dup(0).s2xlate, noS2xlate)(Seq( 292 allStage -> onlyStage1, 293 onlyStage1 -> onlyStage1, 294 onlyStage2 -> onlyStage2 295 )) 296 val refill_vpn = io.refill.bits.req_info_dup(0).vpn 297 io.refill.valid && (level.U === io.refill.bits.level_dup(0)) && vpn_match(refill_vpn, vpn, level) && change_h === change_refill_h 298 } 299 300 val vpn_search = stageReq.bits.req_info.vpn 301 val h_search = MuxLookup(stageReq.bits.req_info.s2xlate, noS2xlate)(Seq( 302 allStage -> onlyStage1, 303 onlyStage1 -> onlyStage1, 304 onlyStage2 -> onlyStage2 305 )) 306 307 // l3 308 val l3Hit = if(EnableSv48) Some(Wire(Bool())) else None 309 val l3HitPPN = if(EnableSv48) Some(Wire(UInt(ppnLen.W))) else None 310 val l3HitPbmt = if(EnableSv48) Some(Wire(UInt(ptePbmtLen.W))) else None 311 val l3Pre = if(EnableSv48) Some(Wire(Bool())) else None 312 val ptwl3replace = if(EnableSv48) Some(ReplacementPolicy.fromString(l2tlbParams.l3Replacer, l2tlbParams.l3Size)) else None 313 if (EnableSv48) { 314 val hitVecT = l3.get.zipWithIndex.map { 315 case (e, i) => (e.hit(vpn_search, io.csr_dup(2).satp.asid, io.csr_dup(2).vsatp.asid, io.csr_dup(2).hgatp.vmid, s2xlate = h_search =/= noS2xlate) 316 && l3v.get(i) && h_search === l3h.get(i)) 317 } 318 val hitVec = hitVecT.map(RegEnable(_, stageReq.fire)) 319 320 // stageDelay, but check for l3 321 val hitPPN = DataHoldBypass(ParallelPriorityMux(hitVec zip l3.get.map(_.ppn)), stageDelay_valid_1cycle) 322 val hitPbmt = DataHoldBypass(ParallelPriorityMux(hitVec zip l3.get.map(_.pbmt)), stageDelay_valid_1cycle) 323 val hitPre = DataHoldBypass(ParallelPriorityMux(hitVec zip l3.get.map(_.prefetch)), stageDelay_valid_1cycle) 324 val hit = DataHoldBypass(ParallelOR(hitVec), stageDelay_valid_1cycle) 325 326 when (hit && stageDelay_valid_1cycle) { ptwl3replace.get.access(OHToUInt(hitVec)) } 327 328 l3AccessPerf.get.zip(hitVec).map{ case (l, h) => l := h && stageDelay_valid_1cycle} 329 for (i <- 0 until l2tlbParams.l3Size) { 330 XSDebug(stageReq.fire, p"[l3] l3(${i.U}) ${l3.get(i)} hit:${l3.get(i).hit(vpn_search, io.csr_dup(2).satp.asid, io.csr_dup(2).vsatp.asid, io.csr_dup(2).hgatp.vmid, s2xlate = h_search =/= noS2xlate)}\n") 331 } 332 XSDebug(stageReq.fire, p"[l3] l3v:${Binary(l3v.get)} hitVecT:${Binary(VecInit(hitVecT).asUInt)}\n") 333 XSDebug(stageDelay(0).valid, p"[l3] l3Hit:${hit} l3HitPPN:0x${Hexadecimal(hitPPN)} hitVec:${VecInit(hitVec).asUInt}\n") 334 335 VecInit(hitVecT).suggestName(s"l3_hitVecT") 336 VecInit(hitVec).suggestName(s"l3_hitVec") 337 338 // synchronize with other entries with RegEnable 339 l3Hit.map(_ := RegEnable(hit, stageDelay(1).fire)) 340 l3HitPPN.map(_ := RegEnable(hitPPN, stageDelay(1).fire)) 341 l3HitPbmt.map(_ := RegEnable(hitPbmt, stageDelay(1).fire)) 342 l3Pre.map(_ := RegEnable(hitPre, stageDelay(1).fire)) 343 } 344 345 // l2 346 val ptwl2replace = ReplacementPolicy.fromString(l2tlbParams.l2Replacer, l2tlbParams.l2Size) 347 val (l2Hit, l2HitPPN, l2HitPbmt, l2Pre) = { 348 val hitVecT = l2.zipWithIndex.map { 349 case (e, i) => (e.hit(vpn_search, io.csr_dup(2).satp.asid, io.csr_dup(2).vsatp.asid, io.csr_dup(2).hgatp.vmid, s2xlate = h_search =/= noS2xlate) 350 && l2v(i) && h_search === l2h(i)) 351 } 352 val hitVec = hitVecT.map(RegEnable(_, stageReq.fire)) 353 354 // stageDelay, but check for l2 355 val hitPPN = DataHoldBypass(ParallelPriorityMux(hitVec zip l2.map(_.ppn)), stageDelay_valid_1cycle) 356 val hitPbmt = DataHoldBypass(ParallelPriorityMux(hitVec zip l2.map(_.pbmt)), stageDelay_valid_1cycle) 357 val hitPre = DataHoldBypass(ParallelPriorityMux(hitVec zip l2.map(_.prefetch)), stageDelay_valid_1cycle) 358 val hit = DataHoldBypass(ParallelOR(hitVec), stageDelay_valid_1cycle) 359 360 when (hit && stageDelay_valid_1cycle) { ptwl2replace.access(OHToUInt(hitVec)) } 361 362 l2AccessPerf.zip(hitVec).map{ case (l, h) => l := h && stageDelay_valid_1cycle} 363 for (i <- 0 until l2tlbParams.l2Size) { 364 XSDebug(stageReq.fire, p"[l2] l2(${i.U}) ${l2(i)} hit:${l2(i).hit(vpn_search, io.csr_dup(2).satp.asid, io.csr_dup(2).vsatp.asid, io.csr_dup(2).hgatp.vmid, s2xlate = h_search =/= noS2xlate)}\n") 365 } 366 XSDebug(stageReq.fire, p"[l2] l2v:${Binary(l2v)} hitVecT:${Binary(VecInit(hitVecT).asUInt)}\n") 367 XSDebug(stageDelay(0).valid, p"[l2] l2Hit:${hit} l2HitPPN:0x${Hexadecimal(hitPPN)} hitVec:${VecInit(hitVec).asUInt}\n") 368 369 VecInit(hitVecT).suggestName(s"l2_hitVecT") 370 VecInit(hitVec).suggestName(s"l2_hitVec") 371 372 // synchronize with other entries with RegEnable 373 (RegEnable(hit, stageDelay(1).fire), 374 RegEnable(hitPPN, stageDelay(1).fire), 375 RegEnable(hitPbmt, stageDelay(1).fire), 376 RegEnable(hitPre, stageDelay(1).fire)) 377 } 378 379 // l1 380 val ptwl1replace = ReplacementPolicy.fromString(l2tlbParams.l1Replacer,l2tlbParams.l1nWays,l2tlbParams.l1nSets) 381 val (l1Hit, l1HitPPN, l1HitPbmt, l1Pre, l1eccError) = { 382 val ridx = genPtwL1SetIdx(vpn_search) 383 l1.io.r.req.valid := stageReq.fire 384 l1.io.r.req.bits.apply(setIdx = ridx) 385 val vVec_req = getl1vSet(vpn_search) 386 val hVec_req = getl1hSet(vpn_search) 387 388 // delay one cycle after sram read 389 val delay_vpn = stageDelay(0).bits.req_info.vpn 390 val delay_h = MuxLookup(stageDelay(0).bits.req_info.s2xlate, noS2xlate)(Seq( 391 allStage -> onlyStage1, 392 onlyStage1 -> onlyStage1, 393 onlyStage2 -> onlyStage2 394 )) 395 val data_resp = DataHoldBypass(l1.io.r.resp.data, stageDelay_valid_1cycle) 396 val vVec_delay = RegEnable(vVec_req, stageReq.fire) 397 val hVec_delay = RegEnable(hVec_req, stageReq.fire) 398 val hitVec_delay = VecInit(data_resp.zip(vVec_delay.asBools).zip(hVec_delay).map { case ((wayData, v), h) => 399 wayData.entries.hit(delay_vpn, io.csr_dup(1).satp.asid, io.csr_dup(1).vsatp.asid, io.csr_dup(1).hgatp.vmid, s2xlate = delay_h =/= noS2xlate) && v && (delay_h === h)}) 400 401 // check hit and ecc 402 val check_vpn = stageCheck(0).bits.req_info.vpn 403 val ramDatas = RegEnable(data_resp, stageDelay(1).fire) 404 val vVec = RegEnable(vVec_delay, stageDelay(1).fire).asBools 405 406 val hitVec = RegEnable(hitVec_delay, stageDelay(1).fire) 407 val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas) 408 val hitWayData = hitWayEntry.entries 409 val hit = ParallelOR(hitVec) 410 val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l1nWays).map(_.U(log2Up(l2tlbParams.l1nWays).W))) 411 val eccError = WireInit(false.B) 412 if (l2tlbParams.enablePTWECC) { 413 eccError := hitWayEntry.decode() 414 } else { 415 eccError := false.B 416 } 417 418 ridx.suggestName(s"l1_ridx") 419 ramDatas.suggestName(s"l1_ramDatas") 420 hitVec.suggestName(s"l1_hitVec") 421 hitWayData.suggestName(s"l1_hitWayData") 422 hitWay.suggestName(s"l1_hitWay") 423 424 when (hit && stageCheck_valid_1cycle) { ptwl1replace.access(genPtwL1SetIdx(check_vpn), hitWay) } 425 426 l1AccessPerf.zip(hitVec).map{ case (l, h) => l := h && stageCheck_valid_1cycle } 427 XSDebug(stageDelay_valid_1cycle, p"[l1] ridx:0x${Hexadecimal(ridx)}\n") 428 for (i <- 0 until l2tlbParams.l1nWays) { 429 XSDebug(stageCheck_valid_1cycle, p"[l1] ramDatas(${i.U}) ${ramDatas(i)} l1v:${vVec(i)} hit:${hit}\n") 430 } 431 XSDebug(stageCheck_valid_1cycle, p"[l1] l1Hit:${hit} l1HitPPN:0x${Hexadecimal(hitWayData.ppns(genPtwL1SectorIdx(check_vpn)))} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} vidx:${vVec}\n") 432 433 (hit, hitWayData.ppns(genPtwL1SectorIdx(check_vpn)), hitWayData.pbmts(genPtwL1SectorIdx(check_vpn)), hitWayData.prefetch, eccError) 434 } 435 436 // l0 437 val ptwl0replace = ReplacementPolicy.fromString(l2tlbParams.l0Replacer,l2tlbParams.l0nWays,l2tlbParams.l0nSets) 438 val (l0Hit, l0HitData, l0Pre, l0eccError) = { 439 val ridx = genPtwL0SetIdx(vpn_search) 440 l0.io.r.req.valid := stageReq.fire 441 l0.io.r.req.bits.apply(setIdx = ridx) 442 val vVec_req = getl0vSet(vpn_search) 443 val hVec_req = getl0hSet(vpn_search) 444 445 // delay one cycle after sram read 446 val delay_vpn = stageDelay(0).bits.req_info.vpn 447 val delay_h = MuxLookup(stageDelay(0).bits.req_info.s2xlate, noS2xlate)(Seq( 448 allStage -> onlyStage1, 449 onlyStage1 -> onlyStage1, 450 onlyStage2 -> onlyStage2 451 )) 452 val data_resp = DataHoldBypass(l0.io.r.resp.data, stageDelay_valid_1cycle) 453 val vVec_delay = RegEnable(vVec_req, stageReq.fire) 454 val hVec_delay = RegEnable(hVec_req, stageReq.fire) 455 val hitVec_delay = VecInit(data_resp.zip(vVec_delay.asBools).zip(hVec_delay).map { case ((wayData, v), h) => 456 wayData.entries.hit(delay_vpn, io.csr_dup(0).satp.asid, io.csr_dup(0).vsatp.asid, io.csr_dup(0).hgatp.vmid, s2xlate = delay_h =/= noS2xlate) && v && (delay_h === h)}) 457 458 // check hit and ecc 459 val check_vpn = stageCheck(0).bits.req_info.vpn 460 val ramDatas = RegEnable(data_resp, stageDelay(1).fire) 461 val vVec = RegEnable(vVec_delay, stageDelay(1).fire).asBools 462 463 val hitVec = RegEnable(hitVec_delay, stageDelay(1).fire) 464 val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas) 465 val hitWayData = hitWayEntry.entries 466 val hitWayEcc = hitWayEntry.ecc 467 val hit = ParallelOR(hitVec) 468 val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l0nWays).map(_.U(log2Up(l2tlbParams.l0nWays).W))) 469 val eccError = WireInit(false.B) 470 if (l2tlbParams.enablePTWECC) { 471 eccError := hitWayEntry.decode() 472 } else { 473 eccError := false.B 474 } 475 476 when (hit && stageCheck_valid_1cycle) { ptwl0replace.access(genPtwL0SetIdx(check_vpn), hitWay) } 477 478 l0AccessPerf.zip(hitVec).map{ case (l, h) => l := h && stageCheck_valid_1cycle } 479 XSDebug(stageReq.fire, p"[l0] ridx:0x${Hexadecimal(ridx)}\n") 480 for (i <- 0 until l2tlbParams.l0nWays) { 481 XSDebug(stageCheck_valid_1cycle, p"[l0] ramDatas(${i.U}) ${ramDatas(i)} l0v:${vVec(i)} hit:${hitVec(i)}\n") 482 } 483 XSDebug(stageCheck_valid_1cycle, p"[l0] l0Hit:${hit} l0HitData:${hitWayData} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} v:${vVec}\n") 484 485 ridx.suggestName(s"l0_ridx") 486 ramDatas.suggestName(s"l0_ramDatas") 487 hitVec.suggestName(s"l0_hitVec") 488 hitWay.suggestName(s"l0_hitWay") 489 490 (hit, hitWayData, hitWayData.prefetch, eccError) 491 } 492 val l0HitPPN = l0HitData.ppns 493 val l0HitPbmt = l0HitData.pbmts 494 val l0HitPerm = l0HitData.perms.getOrElse(0.U.asTypeOf(Vec(PtwL0SectorSize, new PtePermBundle))) 495 val l0HitValid = l0HitData.vs 496 val l0HitAf = l0HitData.af 497 498 // super page 499 val spreplace = ReplacementPolicy.fromString(l2tlbParams.spReplacer, l2tlbParams.spSize) 500 val (spHit, spHitData, spPre, spValid) = { 501 val hitVecT = sp.zipWithIndex.map { case (e, i) => e.hit(vpn_search, io.csr_dup(0).satp.asid, io.csr_dup(0).vsatp.asid, io.csr_dup(0).hgatp.vmid, s2xlate = h_search =/= noS2xlate) && spv(i) && (sph(i) === h_search) } 502 val hitVec = hitVecT.map(RegEnable(_, stageReq.fire)) 503 val hitData = ParallelPriorityMux(hitVec zip sp) 504 val hit = ParallelOR(hitVec) 505 506 when (hit && stageDelay_valid_1cycle) { spreplace.access(OHToUInt(hitVec)) } 507 508 spAccessPerf.zip(hitVec).map{ case (s, h) => s := h && stageDelay_valid_1cycle } 509 for (i <- 0 until l2tlbParams.spSize) { 510 XSDebug(stageReq.fire, p"[sp] sp(${i.U}) ${sp(i)} hit:${sp(i).hit(vpn_search, io.csr_dup(0).satp.asid, io.csr_dup(0).vsatp.asid, io.csr_dup(0).hgatp.vmid, s2xlate = h_search =/= noS2xlate)} spv:${spv(i)}\n") 511 } 512 XSDebug(stageDelay_valid_1cycle, p"[sp] spHit:${hit} spHitData:${hitData} hitVec:${Binary(VecInit(hitVec).asUInt)}\n") 513 514 VecInit(hitVecT).suggestName(s"sp_hitVecT") 515 VecInit(hitVec).suggestName(s"sp_hitVec") 516 517 (RegEnable(hit, stageDelay(1).fire), 518 RegEnable(hitData, stageDelay(1).fire), 519 RegEnable(hitData.prefetch, stageDelay(1).fire), 520 RegEnable(hitData.v, stageDelay(1).fire)) 521 } 522 val spHitPerm = spHitData.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)) 523 val spHitLevel = spHitData.level.getOrElse(0.U) 524 525 val check_res = Wire(new PageCacheRespBundle) 526 check_res.l3.map(_.apply(l3Hit.get, l3Pre.get, l3HitPPN.get)) 527 check_res.l2.apply(l2Hit, l2Pre, l2HitPPN, l2HitPbmt) 528 check_res.l1.apply(l1Hit, l1Pre, l1HitPPN, l1HitPbmt, ecc = l1eccError) 529 check_res.l0.apply(l0Hit, l0Pre, l0HitPPN, l0HitPbmt, l0HitPerm, l0eccError, valid = l0HitValid, accessFault = l0HitAf) 530 check_res.sp.apply(spHit, spPre, spHitData.ppn, spHitData.pbmt, spHitPerm, false.B, spHitLevel, spValid) 531 532 val resp_res = Reg(new PageCacheRespBundle) 533 when (stageCheck(1).fire) { resp_res := check_res } 534 535 // stageResp bypass 536 val bypassed = if (EnableSv48) Wire(Vec(4, Bool())) else Wire(Vec(3, Bool())) 537 bypassed.indices.foreach(i => 538 bypassed(i) := stageResp.bits.bypassed(i) || 539 ValidHoldBypass(refill_bypass(stageResp.bits.req_info.vpn, i, stageResp.bits.req_info.s2xlate), 540 OneCycleValid(stageCheck(1).fire, false.B) || io.refill.valid) 541 ) 542 543 // stageResp bypass to hptw 544 val hptw_bypassed = if (EnableSv48) Wire(Vec(4, Bool())) else Wire(Vec(3, Bool())) 545 hptw_bypassed.indices.foreach(i => 546 hptw_bypassed(i) := stageResp.bits.bypassed(i) || 547 ValidHoldBypass(refill_bypass(stageResp.bits.req_info.vpn, i, stageResp.bits.req_info.s2xlate), 548 io.resp.fire) 549 ) 550 551 val isAllStage = stageResp.bits.req_info.s2xlate === allStage 552 val isOnlyStage2 = stageResp.bits.req_info.s2xlate === onlyStage2 553 val stage1Hit = (resp_res.l0.hit || resp_res.sp.hit) && isAllStage 554 val idx = stageResp.bits.req_info.vpn(2, 0) 555 val stage1Pf = !Mux(resp_res.l0.hit, resp_res.l0.v(idx), resp_res.sp.v) 556 io.resp.bits.req_info := stageResp.bits.req_info 557 io.resp.bits.isFirst := stageResp.bits.isFirst 558 io.resp.bits.hit := (resp_res.l0.hit || resp_res.sp.hit) && (!isAllStage || isAllStage && stage1Pf) 559 if (EnableSv48) { 560 io.resp.bits.bypassed := (bypassed(0) || (bypassed(1) && !resp_res.l1.hit) || (bypassed(2) && !resp_res.l2.hit) || (bypassed(3) && !resp_res.l3.get.hit)) && !isAllStage 561 } else { 562 io.resp.bits.bypassed := (bypassed(0) || (bypassed(1) && !resp_res.l1.hit) || (bypassed(2) && !resp_res.l2.hit)) && !isAllStage 563 } 564 io.resp.bits.prefetch := resp_res.l0.pre && resp_res.l0.hit || resp_res.sp.pre && resp_res.sp.hit 565 io.resp.bits.toFsm.l3Hit.map(_ := resp_res.l3.get.hit && !stage1Hit && !isOnlyStage2 && !stageResp.bits.isHptwReq) 566 io.resp.bits.toFsm.l2Hit := resp_res.l2.hit && !stage1Hit && !isOnlyStage2 && !stageResp.bits.isHptwReq 567 io.resp.bits.toFsm.l1Hit := resp_res.l1.hit && !stage1Hit && !isOnlyStage2 && !stageResp.bits.isHptwReq 568 io.resp.bits.toFsm.ppn := Mux(resp_res.l1.hit, resp_res.l1.ppn, Mux(resp_res.l2.hit, resp_res.l2.ppn, resp_res.l3.getOrElse(0.U.asTypeOf(new PageCachePerPespBundle)).ppn)) 569 io.resp.bits.toFsm.stage1Hit := stage1Hit 570 571 io.resp.bits.isHptwReq := stageResp.bits.isHptwReq 572 if (EnableSv48) { 573 io.resp.bits.toHptw.bypassed := (hptw_bypassed(0) || (hptw_bypassed(1) && !resp_res.l1.hit) || (hptw_bypassed(2) && !resp_res.l2.hit) || (hptw_bypassed(3) && !resp_res.l3.get.hit)) && stageResp.bits.isHptwReq 574 } else { 575 io.resp.bits.toHptw.bypassed := (hptw_bypassed(0) || (hptw_bypassed(1) && !resp_res.l1.hit) || (hptw_bypassed(2) && !resp_res.l2.hit)) && stageResp.bits.isHptwReq 576 } 577 io.resp.bits.toHptw.id := stageResp.bits.hptwId 578 io.resp.bits.toHptw.l3Hit.map(_ := resp_res.l3.get.hit && stageResp.bits.isHptwReq) 579 io.resp.bits.toHptw.l2Hit := resp_res.l2.hit && stageResp.bits.isHptwReq 580 io.resp.bits.toHptw.l1Hit := resp_res.l1.hit && stageResp.bits.isHptwReq 581 io.resp.bits.toHptw.ppn := Mux(resp_res.l1.hit, resp_res.l1.ppn, Mux(resp_res.l2.hit, resp_res.l2.ppn, resp_res.l3.getOrElse(0.U.asTypeOf(new PageCachePerPespBundle)).ppn))(ppnLen - 1, 0) 582 io.resp.bits.toHptw.resp.entry.tag := stageResp.bits.req_info.vpn 583 io.resp.bits.toHptw.resp.entry.asid := DontCare 584 io.resp.bits.toHptw.resp.entry.vmid.map(_ := io.csr_dup(0).hgatp.vmid) 585 io.resp.bits.toHptw.resp.entry.level.map(_ := Mux(resp_res.l0.hit, 0.U, resp_res.sp.level)) 586 io.resp.bits.toHptw.resp.entry.prefetch := from_pre(stageResp.bits.req_info.source) 587 io.resp.bits.toHptw.resp.entry.ppn := Mux(resp_res.l0.hit, resp_res.l0.ppn(idx), resp_res.sp.ppn)(ppnLen - 1, 0) 588 io.resp.bits.toHptw.resp.entry.pbmt := Mux(resp_res.l0.hit, resp_res.l0.pbmt(idx), resp_res.sp.pbmt) 589 io.resp.bits.toHptw.resp.entry.perm.map(_ := Mux(resp_res.l0.hit, resp_res.l0.perm(idx), resp_res.sp.perm)) 590 io.resp.bits.toHptw.resp.entry.v := Mux(resp_res.l0.hit, resp_res.l0.v(idx), resp_res.sp.v) 591 io.resp.bits.toHptw.resp.gpf := !io.resp.bits.toHptw.resp.entry.v 592 io.resp.bits.toHptw.resp.gaf := Mux(resp_res.l0.hit, resp_res.l0.af(idx), false.B) 593 594 io.resp.bits.stage1.entry.map(_.tag := stageResp.bits.req_info.vpn(vpnLen - 1, 3)) 595 io.resp.bits.stage1.entry.map(_.asid := Mux(stageResp.bits.req_info.hasS2xlate(), io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid)) // DontCare 596 io.resp.bits.stage1.entry.map(_.vmid.map(_ := io.csr_dup(0).hgatp.vmid)) 597 if (EnableSv48) { 598 io.resp.bits.stage1.entry.map(_.level.map(_ := Mux(resp_res.l0.hit, 0.U, 599 Mux(resp_res.sp.hit, resp_res.sp.level, 600 Mux(resp_res.l1.hit, 1.U, 601 Mux(resp_res.l2.hit, 2.U, 3.U)))))) 602 } else { 603 io.resp.bits.stage1.entry.map(_.level.map(_ := Mux(resp_res.l0.hit, 0.U, 604 Mux(resp_res.sp.hit, resp_res.sp.level, 605 Mux(resp_res.l1.hit, 1.U, 2.U))))) 606 } 607 io.resp.bits.stage1.entry.map(_.prefetch := from_pre(stageResp.bits.req_info.source)) 608 for (i <- 0 until tlbcontiguous) { 609 if (EnableSv48) { 610 io.resp.bits.stage1.entry(i).ppn := Mux(resp_res.l0.hit, resp_res.l0.ppn(i)(gvpnLen - 1, sectortlbwidth), 611 Mux(resp_res.sp.hit, resp_res.sp.ppn(gvpnLen - 1, sectortlbwidth), 612 Mux(resp_res.l1.hit, resp_res.l1.ppn(gvpnLen - 1, sectortlbwidth), 613 Mux(resp_res.l2.hit, resp_res.l2.ppn(gvpnLen - 1, sectortlbwidth), 614 resp_res.l3.get.ppn(gvpnLen - 1, sectortlbwidth))))) 615 io.resp.bits.stage1.entry(i).ppn_low := Mux(resp_res.l0.hit, resp_res.l0.ppn(i)(sectortlbwidth - 1, 0), 616 Mux(resp_res.sp.hit, resp_res.sp.ppn(sectortlbwidth - 1, 0), 617 Mux(resp_res.l1.hit, resp_res.l1.ppn(sectortlbwidth - 1, 0), 618 Mux(resp_res.l2.hit, resp_res.l2.ppn(sectortlbwidth - 1, 0), 619 resp_res.l3.get.ppn(sectortlbwidth - 1, 0))))) 620 io.resp.bits.stage1.entry(i).v := Mux(resp_res.l0.hit, resp_res.l0.v(i), 621 Mux(resp_res.sp.hit, resp_res.sp.v, 622 Mux(resp_res.l1.hit, resp_res.l1.v, 623 Mux(resp_res.l2.hit, resp_res.l2.v, 624 resp_res.l3.get.v)))) 625 } else { 626 io.resp.bits.stage1.entry(i).ppn := Mux(resp_res.l0.hit, resp_res.l0.ppn(i)(gvpnLen - 1, sectortlbwidth), 627 Mux(resp_res.sp.hit, resp_res.sp.ppn(gvpnLen - 1, sectortlbwidth), 628 Mux(resp_res.l1.hit, resp_res.l1.ppn(gvpnLen - 1, sectortlbwidth), 629 resp_res.l2.ppn(gvpnLen - 1, sectortlbwidth)))) 630 io.resp.bits.stage1.entry(i).ppn_low := Mux(resp_res.l0.hit, resp_res.l0.ppn(i)(sectortlbwidth - 1, 0), 631 Mux(resp_res.sp.hit, resp_res.sp.ppn(sectortlbwidth - 1, 0), 632 Mux(resp_res.l1.hit, resp_res.l1.ppn(sectortlbwidth - 1, 0), 633 resp_res.l2.ppn(sectortlbwidth - 1, 0)))) 634 io.resp.bits.stage1.entry(i).v := Mux(resp_res.l0.hit, resp_res.l0.v(i), 635 Mux(resp_res.sp.hit, resp_res.sp.v, 636 Mux(resp_res.l1.hit, resp_res.l1.v, 637 resp_res.l2.v))) 638 } 639 io.resp.bits.stage1.entry(i).pbmt := Mux(resp_res.l0.hit, resp_res.l0.pbmt(i), 640 Mux(resp_res.sp.hit, resp_res.sp.pbmt, 641 Mux(resp_res.l1.hit, resp_res.l1.pbmt, 642 resp_res.l2.pbmt))) 643 io.resp.bits.stage1.entry(i).perm.map(_ := Mux(resp_res.l0.hit, resp_res.l0.perm(i), Mux(resp_res.sp.hit, resp_res.sp.perm, 0.U.asTypeOf(new PtePermBundle)))) 644 io.resp.bits.stage1.entry(i).pf := !io.resp.bits.stage1.entry(i).v 645 io.resp.bits.stage1.entry(i).af := Mux(resp_res.l0.hit, resp_res.l0.af(i), false.B) 646 } 647 io.resp.bits.stage1.pteidx := UIntToOH(idx).asBools 648 io.resp.bits.stage1.not_super := Mux(resp_res.l0.hit, true.B, false.B) 649 io.resp.valid := stageResp.valid 650 XSError(stageResp.valid && resp_res.l0.hit && resp_res.sp.hit, "normal page and super page both hit") 651 XSError(stageResp.valid && io.resp.bits.hit && bypassed(0), "page cache, bypassed but hit") 652 653 // refill Perf 654 val l3RefillPerf = if (EnableSv48) Some(Wire(Vec(l2tlbParams.l3Size, Bool()))) else None 655 val l2RefillPerf = Wire(Vec(l2tlbParams.l2Size, Bool())) 656 val l1RefillPerf = Wire(Vec(l2tlbParams.l1nWays, Bool())) 657 val l0RefillPerf = Wire(Vec(l2tlbParams.l0nWays, Bool())) 658 val spRefillPerf = Wire(Vec(l2tlbParams.spSize, Bool())) 659 l3RefillPerf.map(_.map(_ := false.B)) 660 l2RefillPerf.map(_ := false.B) 661 l1RefillPerf.map(_ := false.B) 662 l0RefillPerf.map(_ := false.B) 663 spRefillPerf.map(_ := false.B) 664 665 // refill 666 l1.io.w.req <> DontCare 667 l0.io.w.req <> DontCare 668 l1.io.w.req.valid := false.B 669 l0.io.w.req.valid := false.B 670 671 val memRdata = refill.ptes 672 val memPtes = (0 until (l2tlbParams.blockBytes/(XLEN/8))).map(i => memRdata((i+1)*XLEN-1, i*XLEN).asTypeOf(new PteBundle)) 673 val memSelData = io.refill.bits.sel_pte_dup 674 val memPte = memSelData.map(a => a.asTypeOf(new PteBundle)) 675 676 // TODO: handle sfenceLatch outsize 677 if (EnableSv48) { 678 when (!flush_dup(2) && refill.levelOH.l3.get && !memPte(2).isLeaf() && !memPte(2).isPf(refill.level_dup(2)) 679 && Mux(refill.req_info_dup(2).s2xlate === allStage, !memPte(2).isStage1Gpf(io.csr_dup(2).vsatp.mode), Mux(refill.req_info_dup(2).s2xlate === onlyStage1, !(memPte(2).isAf() || memPte(2).isStage1Gpf(io.csr_dup(2).vsatp.mode)), Mux(refill.req_info_dup(2).s2xlate === onlyStage2, !memPte(2).isGpf(refill.level_dup(2)), !memPte(2).isAf())))) { 680 val refillIdx = replaceWrapper(l3v.get, ptwl3replace.get.way) 681 refillIdx.suggestName(s"Ptwl3RefillIdx") 682 val rfOH = UIntToOH(refillIdx) 683 l3.get(refillIdx).refill( 684 refill.req_info_dup(2).vpn, 685 Mux(refill.req_info_dup(2).s2xlate =/= noS2xlate, io.csr_dup(2).vsatp.asid, io.csr_dup(2).satp.asid), 686 io.csr_dup(2).hgatp.vmid, 687 memSelData(2), 688 3.U, 689 refill_prefetch_dup(2) 690 ) 691 ptwl2replace.access(refillIdx) 692 l3v.get := l3v.get | rfOH 693 l3g.get := (l3g.get & ~rfOH) | Mux(memPte(2).perm.g, rfOH, 0.U) 694 l3h.get(refillIdx) := refill_h(2) 695 696 for (i <- 0 until l2tlbParams.l3Size) { 697 l3RefillPerf.get(i) := i.U === refillIdx 698 } 699 700 XSDebug(p"[l3 refill] refillIdx:${refillIdx} refillEntry:${l3.get(refillIdx).genPtwEntry(refill.req_info_dup(2).vpn, Mux(refill.req_info_dup(2).s2xlate =/= noS2xlate, io.csr_dup(2).vsatp.asid, io.csr_dup(2).satp.asid), memSelData(2), 0.U, prefetch = refill_prefetch_dup(2))}\n") 701 XSDebug(p"[l3 refill] l3v:${Binary(l3v.get)}->${Binary(l3v.get | rfOH)} l3g:${Binary(l3g.get)}->${Binary((l3g.get & ~rfOH) | Mux(memPte(2).perm.g, rfOH, 0.U))}\n") 702 703 refillIdx.suggestName(s"l3_refillIdx") 704 rfOH.suggestName(s"l3_rfOH") 705 } 706 } 707 708 when (!flush_dup(2) && refill.levelOH.l2 && !memPte(2).isLeaf() && !memPte(2).isPf(refill.level_dup(2)) 709 && Mux(refill.req_info_dup(2).s2xlate === allStage, !memPte(2).isStage1Gpf(io.csr_dup(2).vsatp.mode), Mux(refill.req_info_dup(2).s2xlate === onlyStage1, !(memPte(2).isAf() || memPte(2).isStage1Gpf(io.csr_dup(2).vsatp.mode)), Mux(refill.req_info_dup(2).s2xlate === onlyStage2, !memPte(2).isGpf(refill.level_dup(2)), !memPte(2).isAf())))) { 710 val refillIdx = replaceWrapper(l2v, ptwl2replace.way) 711 refillIdx.suggestName(s"Ptwl2RefillIdx") 712 val rfOH = UIntToOH(refillIdx) 713 l2(refillIdx).refill( 714 refill.req_info_dup(2).vpn, 715 Mux(refill.req_info_dup(2).s2xlate =/= noS2xlate, io.csr_dup(2).vsatp.asid, io.csr_dup(2).satp.asid), 716 io.csr_dup(2).hgatp.vmid, 717 memSelData(2), 718 2.U, 719 refill_prefetch_dup(2) 720 ) 721 ptwl2replace.access(refillIdx) 722 l2v := l2v | rfOH 723 l2g := (l2g & ~rfOH) | Mux(memPte(2).perm.g, rfOH, 0.U) 724 l2h(refillIdx) := refill_h(2) 725 726 for (i <- 0 until l2tlbParams.l2Size) { 727 l2RefillPerf(i) := i.U === refillIdx 728 } 729 730 XSDebug(p"[l2 refill] refillIdx:${refillIdx} refillEntry:${l2(refillIdx).genPtwEntry(refill.req_info_dup(2).vpn, Mux(refill.req_info_dup(2).s2xlate =/= noS2xlate, io.csr_dup(2).vsatp.asid, io.csr_dup(2).satp.asid), memSelData(2), 0.U, prefetch = refill_prefetch_dup(2))}\n") 731 XSDebug(p"[l2 refill] l2v:${Binary(l2v)}->${Binary(l2v | rfOH)} l2g:${Binary(l2g)}->${Binary((l2g & ~rfOH) | Mux(memPte(2).perm.g, rfOH, 0.U))}\n") 732 733 refillIdx.suggestName(s"l2_refillIdx") 734 rfOH.suggestName(s"l2_rfOH") 735 } 736 737 when (!flush_dup(1) && refill.levelOH.l1 && !memPte(1).isLeaf() && !memPte(1).isPf(refill.level_dup(1)) 738 && Mux(refill.req_info_dup(1).s2xlate === allStage, !memPte(1).isStage1Gpf(io.csr_dup(1).vsatp.mode), Mux(refill.req_info_dup(1).s2xlate === onlyStage1, !(memPte(1).isAf() || memPte(1).isStage1Gpf(io.csr_dup(1).vsatp.mode)), Mux(refill.req_info_dup(1).s2xlate === onlyStage2, !memPte(1).isGpf(refill.level_dup(1)), !memPte(1).isAf())))) { 739 val refillIdx = genPtwL1SetIdx(refill.req_info_dup(1).vpn) 740 val victimWay = replaceWrapper(getl1vSet(refill.req_info_dup(1).vpn), ptwl1replace.way(refillIdx)) 741 val victimWayOH = UIntToOH(victimWay) 742 val rfvOH = UIntToOH(Cat(refillIdx, victimWay)) 743 val wdata = Wire(l1EntryType) 744 wdata.gen( 745 vpn = refill.req_info_dup(1).vpn, 746 asid = Mux(refill.req_info_dup(1).s2xlate =/= noS2xlate, io.csr_dup(1).vsatp.asid, io.csr_dup(1).satp.asid), 747 vmid = io.csr_dup(1).hgatp.vmid, 748 data = memRdata, 749 levelUInt = 1.U, 750 refill_prefetch_dup(1), 751 refill.req_info_dup(1).s2xlate 752 ) 753 l1.io.w.apply( 754 valid = true.B, 755 setIdx = refillIdx, 756 data = wdata, 757 waymask = victimWayOH 758 ) 759 ptwl1replace.access(refillIdx, victimWay) 760 l1v := l1v | rfvOH 761 l1g := l1g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U) 762 l1h(refillIdx)(victimWay) := refill_h(1) 763 764 for (i <- 0 until l2tlbParams.l1nWays) { 765 l1RefillPerf(i) := i.U === victimWay 766 } 767 768 XSDebug(p"[l1 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n") 769 XSDebug(p"[l1 refill] refilldata:0x${wdata}\n") 770 XSDebug(p"[l1 refill] l1v:${Binary(l1v)} -> ${Binary(l1v | rfvOH)}\n") 771 XSDebug(p"[l1 refill] l1g:${Binary(l1g)} -> ${Binary(l1g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n") 772 773 refillIdx.suggestName(s"l1_refillIdx") 774 victimWay.suggestName(s"l1_victimWay") 775 victimWayOH.suggestName(s"l1_victimWayOH") 776 rfvOH.suggestName(s"l1_rfvOH") 777 } 778 779 when (!flush_dup(0) && refill.levelOH.l0 780 && Mux(refill.req_info_dup(0).s2xlate === allStage, !memPte(0).isStage1Gpf(io.csr_dup(0).vsatp.mode), Mux(refill.req_info_dup(0).s2xlate === onlyStage1, !(memPte(0).isAf() || memPte(0).isStage1Gpf(io.csr_dup(0).vsatp.mode)), Mux(refill.req_info_dup(0).s2xlate === onlyStage2, !memPte(0).isGpf(refill.level_dup(0)), !memPte(0).isAf())))) { 781 val refillIdx = genPtwL0SetIdx(refill.req_info_dup(0).vpn) 782 val victimWay = replaceWrapper(getl0vSet(refill.req_info_dup(0).vpn), ptwl0replace.way(refillIdx)) 783 val victimWayOH = UIntToOH(victimWay) 784 val rfvOH = UIntToOH(Cat(refillIdx, victimWay)) 785 val wdata = Wire(l0EntryType) 786 wdata.gen( 787 vpn = refill.req_info_dup(0).vpn, 788 asid = Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid), 789 vmid = io.csr_dup(0).hgatp.vmid, 790 data = memRdata, 791 levelUInt = 0.U, 792 refill_prefetch_dup(0), 793 refill.req_info_dup(0).s2xlate 794 ) 795 l0.io.w.apply( 796 valid = true.B, 797 setIdx = refillIdx, 798 data = wdata, 799 waymask = victimWayOH 800 ) 801 ptwl0replace.access(refillIdx, victimWay) 802 l0v := l0v | rfvOH 803 l0g := l0g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U) 804 l0h(refillIdx)(victimWay) := refill_h(0) 805 806 for (i <- 0 until l2tlbParams.l0nWays) { 807 l0RefillPerf(i) := i.U === victimWay 808 } 809 810 XSDebug(p"[l0 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n") 811 XSDebug(p"[l0 refill] refilldata:0x${wdata}\n") 812 XSDebug(p"[l0 refill] l0v:${Binary(l0v)} -> ${Binary(l0v | rfvOH)}\n") 813 XSDebug(p"[l0 refill] l0g:${Binary(l0g)} -> ${Binary(l0g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n") 814 815 refillIdx.suggestName(s"l0_refillIdx") 816 victimWay.suggestName(s"l0_victimWay") 817 victimWayOH.suggestName(s"l0_victimWayOH") 818 rfvOH.suggestName(s"l0_rfvOH") 819 } 820 821 822 // misc entries: super & invalid 823 when (!flush_dup(0) && refill.levelOH.sp && (memPte(0).isLeaf() || memPte(0).isPf(refill.level_dup(0))) 824 && Mux(refill.req_info_dup(0).s2xlate === allStage, !memPte(0).isStage1Gpf(io.csr_dup(0).vsatp.mode), Mux(refill.req_info_dup(0).s2xlate === onlyStage1, !(memPte(0).isAf() || memPte(0).isStage1Gpf(io.csr_dup(0).vsatp.mode)), Mux(refill.req_info_dup(0).s2xlate === onlyStage2, !memPte(0).isGpf(refill.level_dup(0)), !memPte(0).isAf())))) { 825 val refillIdx = spreplace.way// LFSR64()(log2Up(l2tlbParams.spSize)-1,0) // TODO: may be LRU 826 val rfOH = UIntToOH(refillIdx) 827 sp(refillIdx).refill( 828 refill.req_info_dup(0).vpn, 829 Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid), 830 io.csr_dup(0).hgatp.vmid, 831 memSelData(0), 832 refill.level_dup(0), 833 refill_prefetch_dup(0), 834 !memPte(0).isPf(refill.level_dup(0)), 835 ) 836 spreplace.access(refillIdx) 837 spv := spv | rfOH 838 spg := spg & ~rfOH | Mux(memPte(0).perm.g, rfOH, 0.U) 839 sph(refillIdx) := refill_h(0) 840 841 for (i <- 0 until l2tlbParams.spSize) { 842 spRefillPerf(i) := i.U === refillIdx 843 } 844 845 XSDebug(p"[sp refill] refillIdx:${refillIdx} refillEntry:${sp(refillIdx).genPtwEntry(refill.req_info_dup(0).vpn, Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid), memSelData(0), refill.level_dup(0), refill_prefetch_dup(0))}\n") 846 XSDebug(p"[sp refill] spv:${Binary(spv)}->${Binary(spv | rfOH)} spg:${Binary(spg)}->${Binary(spg & ~rfOH | Mux(memPte(0).perm.g, rfOH, 0.U))}\n") 847 848 refillIdx.suggestName(s"sp_refillIdx") 849 rfOH.suggestName(s"sp_rfOH") 850 } 851 852 val l1eccFlush = resp_res.l1.ecc && stageResp_valid_1cycle_dup(0) // RegNext(l1eccError, init = false.B) 853 val l0eccFlush = resp_res.l0.ecc && stageResp_valid_1cycle_dup(1) // RegNext(l0eccError, init = false.B) 854 val eccVpn = stageResp.bits.req_info.vpn 855 856 XSError(l1eccFlush, "l2tlb.cache.l1 ecc error. Should not happen at sim stage") 857 XSError(l0eccFlush, "l2tlb.cache.l0 ecc error. Should not happen at sim stage") 858 when (l1eccFlush) { 859 val flushSetIdxOH = UIntToOH(genPtwL1SetIdx(eccVpn)) 860 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l1nWays, a.asUInt) }).asUInt 861 l1v := l1v & ~flushMask 862 l1g := l1g & ~flushMask 863 } 864 865 when (l0eccFlush) { 866 val flushSetIdxOH = UIntToOH(genPtwL0SetIdx(eccVpn)) 867 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l0nWays, a.asUInt) }).asUInt 868 l0v := l0v & ~flushMask 869 l0g := l0g & ~flushMask 870 } 871 872 // sfence for l0 873 val sfence_valid_l0 = sfence_dup(0).valid && !sfence_dup(0).bits.hg && !sfence_dup(0).bits.hv 874 when (sfence_valid_l0) { 875 val l0hhit = VecInit(l0h.flatMap(_.map{a => io.csr_dup(0).priv.virt && a === onlyStage1 || !io.csr_dup(0).priv.virt && a === noS2xlate})).asUInt 876 val sfence_vpn = sfence_dup(0).bits.addr(sfence_dup(0).bits.addr.getWidth-1, offLen) 877 when (sfence_dup(0).bits.rs1/*va*/) { 878 when (sfence_dup(0).bits.rs2) { 879 // all va && all asid 880 l0v := l0v & ~l0hhit 881 } .otherwise { 882 // all va && specific asid except global 883 l0v := l0v & (l0g | ~l0hhit) 884 } 885 } .otherwise { 886 // val flushMask = UIntToOH(genTlbl1Idx(sfence.bits.addr(sfence.bits.addr.getWidth-1, offLen))) 887 val flushSetIdxOH = UIntToOH(genPtwL0SetIdx(sfence_vpn)) 888 // val flushMask = VecInit(flushSetIdxOH.asBools.map(Fill(l2tlbParams.l0nWays, _.asUInt))).asUInt 889 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l0nWays, a.asUInt) }).asUInt 890 flushSetIdxOH.suggestName(s"sfence_nrs1_flushSetIdxOH") 891 flushMask.suggestName(s"sfence_nrs1_flushMask") 892 893 when (sfence_dup(0).bits.rs2) { 894 // specific leaf of addr && all asid 895 l0v := l0v & ~flushMask & ~l0hhit 896 } .otherwise { 897 // specific leaf of addr && specific asid 898 l0v := l0v & (~flushMask | l0g | ~l0hhit) 899 } 900 } 901 } 902 903 // hfencev, simple implementation for l0 904 val hfencev_valid_l0 = sfence_dup(0).valid && sfence_dup(0).bits.hv 905 when(hfencev_valid_l0) { 906 val flushMask = VecInit(l0h.flatMap(_.map(_ === onlyStage1))).asUInt 907 l0v := l0v & ~flushMask // all VS-stage l0 pte 908 } 909 910 // hfenceg, simple implementation for l0 911 val hfenceg_valid_l0 = sfence_dup(0).valid && sfence_dup(0).bits.hg 912 when(hfenceg_valid_l0) { 913 val flushMask = VecInit(l0h.flatMap(_.map(_ === onlyStage2))).asUInt 914 l0v := l0v & ~flushMask // all G-stage l0 pte 915 } 916 917 val l2asidhit = VecInit(l2asids.map(_ === sfence_dup(2).bits.id)).asUInt 918 val spasidhit = VecInit(spasids.map(_ === sfence_dup(0).bits.id)).asUInt 919 val sfence_valid = sfence_dup(0).valid && !sfence_dup(0).bits.hg && !sfence_dup(0).bits.hv 920 when (sfence_valid) { 921 val l2vmidhit = VecInit(l2vmids.map(_.getOrElse(0.U) === io.csr_dup(2).hgatp.vmid)).asUInt 922 val spvmidhit = VecInit(spvmids.map(_.getOrElse(0.U) === io.csr_dup(0).hgatp.vmid)).asUInt 923 val l2hhit = VecInit(l2h.map{a => io.csr_dup(2).priv.virt && a === onlyStage1 || !io.csr_dup(2).priv.virt && a === noS2xlate}).asUInt 924 val sphhit = VecInit(sph.map{a => io.csr_dup(0).priv.virt && a === onlyStage1 || !io.csr_dup(0).priv.virt && a === noS2xlate}).asUInt 925 val l1hhit = VecInit(l1h.flatMap(_.map{a => io.csr_dup(1).priv.virt && a === onlyStage1 || !io.csr_dup(1).priv.virt && a === noS2xlate})).asUInt 926 val sfence_vpn = sfence_dup(0).bits.addr(sfence_dup(0).bits.addr.getWidth-1, offLen) 927 928 when (sfence_dup(0).bits.rs1/*va*/) { 929 when (sfence_dup(0).bits.rs2) { 930 // all va && all asid 931 l1v := l1v & ~l1hhit 932 l2v := l2v & ~(l2hhit & VecInit(l2vmidhit.asBools.map{a => io.csr_dup(2).priv.virt && a || !io.csr_dup(2).priv.virt}).asUInt) 933 spv := spv & ~(sphhit & VecInit(spvmidhit.asBools.map{a => io.csr_dup(0).priv.virt && a || !io.csr_dup(0).priv.virt}).asUInt) 934 } .otherwise { 935 // all va && specific asid except global 936 l1v := l1v & (l1g | ~l1hhit) 937 l2v := l2v & ~(~l2g & l2hhit & l2asidhit & VecInit(l2vmidhit.asBools.map{a => io.csr_dup(2).priv.virt && a || !io.csr_dup(2).priv.virt}).asUInt) 938 spv := spv & ~(~spg & sphhit & spasidhit & VecInit(spvmidhit.asBools.map{a => io.csr_dup(0).priv.virt && a || !io.csr_dup(0).priv.virt}).asUInt) 939 } 940 } .otherwise { 941 when (sfence_dup(0).bits.rs2) { 942 // specific leaf of addr && all asid 943 spv := spv & ~(sphhit & VecInit(sp.map(_.hit(sfence_vpn, sfence_dup(0).bits.id, sfence_dup(0).bits.id, io.csr_dup(0).hgatp.vmid, ignoreAsid = true, s2xlate = io.csr_dup(0).priv.virt))).asUInt) 944 } .otherwise { 945 // specific leaf of addr && specific asid 946 spv := spv & ~(~spg & sphhit & VecInit(sp.map(_.hit(sfence_vpn, sfence_dup(0).bits.id, sfence_dup(0).bits.id, io.csr_dup(0).hgatp.vmid, s2xlate = io.csr_dup(0).priv.virt))).asUInt) 947 } 948 } 949 } 950 951 val hfencev_valid = sfence_dup(0).valid && sfence_dup(0).bits.hv 952 when (hfencev_valid) { 953 val l2vmidhit = VecInit(l2vmids.map(_.getOrElse(0.U) === io.csr_dup(2).hgatp.vmid)).asUInt 954 val spvmidhit = VecInit(spvmids.map(_.getOrElse(0.U) === io.csr_dup(0).hgatp.vmid)).asUInt 955 val l2hhit = VecInit(l2h.map(_ === onlyStage1)).asUInt 956 val sphhit = VecInit(sph.map(_ === onlyStage1)).asUInt 957 val l1hhit = VecInit(l1h.flatMap(_.map(_ === onlyStage1))).asUInt 958 val hfencev_vpn = sfence_dup(0).bits.addr(sfence_dup(0).bits.addr.getWidth-1, offLen) 959 when(sfence_dup(0).bits.rs1) { 960 when(sfence_dup(0).bits.rs2) { 961 l1v := l1v & ~l1hhit 962 l2v := l2v & ~(l2hhit & l2vmidhit) 963 spv := spv & ~(sphhit & spvmidhit) 964 }.otherwise { 965 l1v := l1v & (l1g | ~l1hhit) 966 l2v := l2v & ~(~l2g & l2hhit & l2asidhit & l2vmidhit) 967 spv := spv & ~(~spg & sphhit & spasidhit & spvmidhit) 968 } 969 }.otherwise { 970 when(sfence_dup(0).bits.rs2) { 971 spv := spv & ~(sphhit & VecInit(sp.map(_.hit(hfencev_vpn, sfence_dup(0).bits.id, sfence_dup(0).bits.id, io.csr_dup(0).hgatp.vmid, ignoreAsid = true, s2xlate = true.B))).asUInt) 972 }.otherwise { 973 spv := spv & ~(~spg & sphhit & VecInit(sp.map(_.hit(hfencev_vpn, sfence_dup(0).bits.id, sfence_dup(0).bits.id, io.csr_dup(0).hgatp.vmid, s2xlate = true.B))).asUInt) 974 } 975 } 976 } 977 978 979 val hfenceg_valid = sfence_dup(0).valid && sfence_dup(0).bits.hg 980 when(hfenceg_valid) { 981 val l2vmidhit = VecInit(l2vmids.map(_.getOrElse(0.U) === sfence_dup(2).bits.id)).asUInt 982 val spvmidhit = VecInit(spvmids.map(_.getOrElse(0.U) === sfence_dup(0).bits.id)).asUInt 983 val l2hhit = VecInit(l2h.map(_ === onlyStage2)).asUInt 984 val sphhit = VecInit(sph.map(_ === onlyStage2)).asUInt 985 val l1hhit = VecInit(l1h.flatMap(_.map(_ === onlyStage2))).asUInt 986 val hfenceg_gvpn = (sfence_dup(0).bits.addr << 2)(sfence_dup(0).bits.addr.getWidth - 1, offLen) 987 when(sfence_dup(0).bits.rs1) { 988 when(sfence_dup(0).bits.rs2) { 989 l1v := l1v & ~l1hhit 990 l2v := l2v & ~l2hhit 991 spv := spv & ~sphhit 992 }.otherwise { 993 l1v := l1v & ~l1hhit 994 l2v := l2v & ~(l2hhit & l2vmidhit) 995 spv := spv & ~(sphhit & spvmidhit) 996 } 997 }.otherwise { 998 when(sfence_dup(0).bits.rs2) { 999 spv := spv & ~(sphhit & VecInit(sp.map(_.hit(hfenceg_gvpn, 0.U, 0.U, sfence_dup(0).bits.id, ignoreAsid = true, s2xlate = false.B))).asUInt) 1000 }.otherwise { 1001 spv := spv & ~(~spg & sphhit & VecInit(sp.map(_.hit(hfenceg_gvpn, 0.U, 0.U, sfence_dup(0).bits.id, ignoreAsid = true, s2xlate = true.B))).asUInt) 1002 } 1003 } 1004 } 1005 1006 if (EnableSv48) { 1007 val l3asidhit = VecInit(l3asids.get.map(_ === sfence_dup(2).bits.id)).asUInt 1008 val l3vmidhit = VecInit(l3vmids.get.map(_.getOrElse(0.U) === io.csr_dup(2).hgatp.vmid)).asUInt 1009 val l3hhit = VecInit(l3h.get.map{a => io.csr_dup(2).priv.virt && a === onlyStage1 || !io.csr_dup(2).priv.virt && a === noS2xlate}).asUInt 1010 1011 when (sfence_valid) { 1012 val l3vmidhit = VecInit(l3vmids.get.map(_.getOrElse(0.U) === io.csr_dup(2).hgatp.vmid)).asUInt 1013 val l3hhit = VecInit(l3h.get.map{a => io.csr_dup(2).priv.virt && a === onlyStage1 || !io.csr_dup(2).priv.virt && a === noS2xlate}).asUInt 1014 val sfence_vpn = sfence_dup(2).bits.addr(sfence_dup(2).bits.addr.getWidth-1, offLen) 1015 1016 when (sfence_dup(2).bits.rs1/*va*/) { 1017 when (sfence_dup(2).bits.rs2) { 1018 // all va && all asid 1019 l3v.map(_ := l3v.get & ~(l3hhit & VecInit(l3vmidhit.asBools.map{a => io.csr_dup(2).priv.virt && a || !io.csr_dup(2).priv.virt}).asUInt)) 1020 } .otherwise { 1021 // all va && specific asid except global 1022 l3v.map(_ := l3v.get & ~(~l3g.get & l3hhit & l3asidhit & VecInit(l3vmidhit.asBools.map{a => io.csr_dup(2).priv.virt && a || !io.csr_dup(2).priv.virt}).asUInt)) 1023 } 1024 } 1025 } 1026 1027 when (hfencev_valid) { 1028 val l3vmidhit = VecInit(l3vmids.get.map(_.getOrElse(0.U) === io.csr_dup(2).hgatp.vmid)).asUInt 1029 val l3hhit = VecInit(l3h.get.map(_ === onlyStage1)).asUInt 1030 val hfencev_vpn = sfence_dup(2).bits.addr(sfence_dup(2).bits.addr.getWidth-1, offLen) 1031 when(sfence_dup(2).bits.rs1) { 1032 when(sfence_dup(2).bits.rs2) { 1033 l3v.map(_ := l3v.get & ~(l3hhit & l3vmidhit)) 1034 }.otherwise { 1035 l3v.map(_ := l3v.get & ~(~l3g.get & l3hhit & l3asidhit & l3vmidhit)) 1036 } 1037 } 1038 } 1039 1040 when (hfenceg_valid) { 1041 val l3vmidhit = VecInit(l3vmids.get.map(_.getOrElse(0.U) === sfence_dup(2).bits.id)).asUInt 1042 val l3hhit = VecInit(l3h.get.map(_ === onlyStage2)).asUInt 1043 val hfenceg_gvpn = (sfence_dup(2).bits.addr << 2)(sfence_dup(2).bits.addr.getWidth - 1, offLen) 1044 when(sfence_dup(2).bits.rs1) { 1045 when(sfence_dup(2).bits.rs2) { 1046 l3v.map(_ := l3v.get & ~l3hhit) 1047 }.otherwise { 1048 l3v.map(_ := l3v.get & ~(l3hhit & l3vmidhit)) 1049 } 1050 } 1051 } 1052 } 1053 1054 def InsideStageConnect(in: DecoupledIO[PtwCacheReq], out: DecoupledIO[PtwCacheReq], inFire: Bool): Unit = { 1055 in.ready := !in.valid || out.ready 1056 out.valid := in.valid 1057 out.bits := in.bits 1058 out.bits.bypassed.zip(in.bits.bypassed).zipWithIndex.map{ case (b, i) => 1059 val bypassed_reg = Reg(Bool()) 1060 val bypassed_wire = refill_bypass(in.bits.req_info.vpn, i, in.bits.req_info.s2xlate) && io.refill.valid 1061 when (inFire) { bypassed_reg := bypassed_wire } 1062 .elsewhen (io.refill.valid) { bypassed_reg := bypassed_reg || bypassed_wire } 1063 1064 b._1 := b._2 || (bypassed_wire || (bypassed_reg && !inFire)) 1065 } 1066 } 1067 1068 // Perf Count 1069 val resp_l0 = resp_res.l0.hit 1070 val resp_sp = resp_res.sp.hit 1071 val resp_l3_pre = if (EnableSv48) Some(resp_res.l3.get.pre) else None 1072 val resp_l2_pre = resp_res.l2.pre 1073 val resp_l1_pre = resp_res.l1.pre 1074 val resp_l0_pre = resp_res.l0.pre 1075 val resp_sp_pre = resp_res.sp.pre 1076 val base_valid_access_0 = !from_pre(io.resp.bits.req_info.source) && io.resp.fire 1077 XSPerfAccumulate("access", base_valid_access_0) 1078 if (EnableSv48) { 1079 XSPerfAccumulate("l3_hit", base_valid_access_0 && io.resp.bits.toFsm.l3Hit.get && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1080 } 1081 XSPerfAccumulate("l2_hit", base_valid_access_0 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1082 XSPerfAccumulate("l1_hit", base_valid_access_0 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1083 XSPerfAccumulate("l0_hit", base_valid_access_0 && resp_l0) 1084 XSPerfAccumulate("sp_hit", base_valid_access_0 && resp_sp) 1085 XSPerfAccumulate("pte_hit",base_valid_access_0 && io.resp.bits.hit) 1086 1087 if (EnableSv48) { 1088 XSPerfAccumulate("l3_hit_pre", base_valid_access_0 && resp_l3_pre.get && io.resp.bits.toFsm.l3Hit.get && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1089 } 1090 XSPerfAccumulate("l2_hit_pre", base_valid_access_0 && resp_l2_pre && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1091 XSPerfAccumulate("l1_hit_pre", base_valid_access_0 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1092 XSPerfAccumulate("l0_hit_pre", base_valid_access_0 && resp_l0_pre && resp_l0) 1093 XSPerfAccumulate("sp_hit_pre", base_valid_access_0 && resp_sp_pre && resp_sp) 1094 XSPerfAccumulate("pte_hit_pre",base_valid_access_0 && (resp_l0_pre && resp_l0 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 1095 1096 val base_valid_access_1 = from_pre(io.resp.bits.req_info.source) && io.resp.fire 1097 XSPerfAccumulate("pre_access", base_valid_access_1) 1098 if (EnableSv48) { 1099 XSPerfAccumulate("pre_l3_hit", base_valid_access_1 && io.resp.bits.toFsm.l3Hit.get && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1100 } 1101 XSPerfAccumulate("pre_l2_hit", base_valid_access_1 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1102 XSPerfAccumulate("pre_l1_hit", base_valid_access_1 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1103 XSPerfAccumulate("pre_l0_hit", base_valid_access_1 && resp_l0) 1104 XSPerfAccumulate("pre_sp_hit", base_valid_access_1 && resp_sp) 1105 XSPerfAccumulate("pre_pte_hit",base_valid_access_1 && io.resp.bits.hit) 1106 1107 if (EnableSv48) { 1108 XSPerfAccumulate("pre_l3_hit_pre", base_valid_access_1 && resp_l3_pre.get && io.resp.bits.toFsm.l3Hit.get && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1109 } 1110 XSPerfAccumulate("pre_l2_hit_pre", base_valid_access_1 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1111 XSPerfAccumulate("pre_l1_hit_pre", base_valid_access_1 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1112 XSPerfAccumulate("pre_l0_hit_pre", base_valid_access_1 && resp_l0_pre && resp_l0) 1113 XSPerfAccumulate("pre_sp_hit_pre", base_valid_access_1 && resp_sp_pre && resp_sp) 1114 XSPerfAccumulate("pre_pte_hit_pre",base_valid_access_1 && (resp_l0_pre && resp_l0 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 1115 1116 val base_valid_access_2 = stageResp.bits.isFirst && !from_pre(io.resp.bits.req_info.source) && io.resp.fire 1117 XSPerfAccumulate("access_first", base_valid_access_2) 1118 if (EnableSv48) { 1119 XSPerfAccumulate("l3_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l3Hit.get && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1120 } 1121 XSPerfAccumulate("l2_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1122 XSPerfAccumulate("l1_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1123 XSPerfAccumulate("l0_hit_first", base_valid_access_2 && resp_l0) 1124 XSPerfAccumulate("sp_hit_first", base_valid_access_2 && resp_sp) 1125 XSPerfAccumulate("pte_hit_first",base_valid_access_2 && io.resp.bits.hit) 1126 1127 if (EnableSv48) { 1128 XSPerfAccumulate("l3_hit_pre_first", base_valid_access_2 && resp_l3_pre.get && io.resp.bits.toFsm.l3Hit.get && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1129 } 1130 XSPerfAccumulate("l2_hit_pre_first", base_valid_access_2 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1131 XSPerfAccumulate("l1_hit_pre_first", base_valid_access_2 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1132 XSPerfAccumulate("l0_hit_pre_first", base_valid_access_2 && resp_l0_pre && resp_l0) 1133 XSPerfAccumulate("sp_hit_pre_first", base_valid_access_2 && resp_sp_pre && resp_sp) 1134 XSPerfAccumulate("pte_hit_pre_first",base_valid_access_2 && (resp_l0_pre && resp_l0 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 1135 1136 val base_valid_access_3 = stageResp.bits.isFirst && from_pre(io.resp.bits.req_info.source) && io.resp.fire 1137 XSPerfAccumulate("pre_access_first", base_valid_access_3) 1138 if (EnableSv48) { 1139 XSPerfAccumulate("pre_l3_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l3Hit.get && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1140 } 1141 XSPerfAccumulate("pre_l2_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1142 XSPerfAccumulate("pre_l1_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1143 XSPerfAccumulate("pre_l0_hit_first", base_valid_access_3 && resp_l0) 1144 XSPerfAccumulate("pre_sp_hit_first", base_valid_access_3 && resp_sp) 1145 XSPerfAccumulate("pre_pte_hit_first", base_valid_access_3 && io.resp.bits.hit) 1146 1147 if (EnableSv48) { 1148 XSPerfAccumulate("pre_l3_hit_pre_first", base_valid_access_3 && resp_l3_pre.get && io.resp.bits.toFsm.l3Hit.get && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1149 } 1150 XSPerfAccumulate("pre_l2_hit_pre_first", base_valid_access_3 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1151 XSPerfAccumulate("pre_l1_hit_pre_first", base_valid_access_3 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.hit) 1152 XSPerfAccumulate("pre_l0_hit_pre_first", base_valid_access_3 && resp_l0_pre && resp_l0) 1153 XSPerfAccumulate("pre_sp_hit_pre_first", base_valid_access_3 && resp_sp_pre && resp_sp) 1154 XSPerfAccumulate("pre_pte_hit_pre_first",base_valid_access_3 && (resp_l0_pre && resp_l0 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 1155 1156 XSPerfAccumulate("rwHarzad", io.req.valid && !io.req.ready) 1157 XSPerfAccumulate("out_blocked", io.resp.valid && !io.resp.ready) 1158 if (EnableSv48) { 1159 l3AccessPerf.get.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"l3AccessIndex${i}", l) } 1160 } 1161 l2AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"l2AccessIndex${i}", l) } 1162 l1AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"l1AccessIndex${i}", l) } 1163 l0AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"l0AccessIndex${i}", l) } 1164 spAccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPAccessIndex${i}", l) } 1165 if (EnableSv48) { 1166 l3RefillPerf.get.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"l3RefillIndex${i}", l) } 1167 } 1168 l2RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"l2RefillIndex${i}", l) } 1169 l1RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"l1RefillIndex${i}", l) } 1170 l0RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"l0RefillIndex${i}", l) } 1171 spRefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPRefillIndex${i}", l) } 1172 1173 if (EnableSv48) { 1174 XSPerfAccumulate("l3Refill", Cat(l3RefillPerf.get).orR) 1175 } 1176 XSPerfAccumulate("l2Refill", Cat(l2RefillPerf).orR) 1177 XSPerfAccumulate("l1Refill", Cat(l1RefillPerf).orR) 1178 XSPerfAccumulate("l0Refill", Cat(l0RefillPerf).orR) 1179 XSPerfAccumulate("spRefill", Cat(spRefillPerf).orR) 1180 if (EnableSv48) { 1181 XSPerfAccumulate("l3Refill_pre", Cat(l3RefillPerf.get).orR && refill_prefetch_dup(0)) 1182 } 1183 XSPerfAccumulate("l2Refill_pre", Cat(l2RefillPerf).orR && refill_prefetch_dup(0)) 1184 XSPerfAccumulate("l1Refill_pre", Cat(l1RefillPerf).orR && refill_prefetch_dup(0)) 1185 XSPerfAccumulate("l0Refill_pre", Cat(l0RefillPerf).orR && refill_prefetch_dup(0)) 1186 XSPerfAccumulate("spRefill_pre", Cat(spRefillPerf).orR && refill_prefetch_dup(0)) 1187 1188 // debug 1189 XSDebug(sfence_dup(0).valid, p"[sfence] original v and g vector:\n") 1190 if (EnableSv48) { 1191 XSDebug(sfence_dup(0).valid, p"[sfence] l3v:${Binary(l3v.get)}\n") 1192 } 1193 XSDebug(sfence_dup(0).valid, p"[sfence] l2v:${Binary(l2v)}\n") 1194 XSDebug(sfence_dup(0).valid, p"[sfence] l1v:${Binary(l1v)}\n") 1195 XSDebug(sfence_dup(0).valid, p"[sfence] l0v:${Binary(l0v)}\n") 1196 XSDebug(sfence_dup(0).valid, p"[sfence] l0g:${Binary(l0g)}\n") 1197 XSDebug(sfence_dup(0).valid, p"[sfence] spv:${Binary(spv)}\n") 1198 XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] new v and g vector:\n") 1199 if (EnableSv48) { 1200 XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l3v:${Binary(l3v.get)}\n") 1201 } 1202 XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l2v:${Binary(l2v)}\n") 1203 XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l1v:${Binary(l1v)}\n") 1204 XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l0v:${Binary(l0v)}\n") 1205 XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l0g:${Binary(l0g)}\n") 1206 XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] spv:${Binary(spv)}\n") 1207 1208 val perfEvents = Seq( 1209 ("access ", base_valid_access_0 ), 1210 ("l2_hit ", l2Hit ), 1211 ("l1_hit ", l1Hit ), 1212 ("l0_hit ", l0Hit ), 1213 ("sp_hit ", spHit ), 1214 ("pte_hit ", l0Hit || spHit ), 1215 ("rwHarzad ", io.req.valid && !io.req.ready ), 1216 ("out_blocked ", io.resp.valid && !io.resp.ready), 1217 ) 1218 generatePerfEvent() 1219} 1220