xref: /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala (revision 039cdc35f5f3b68b6295ec5ace90f22a77322e02) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.cache.mmu
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import xiangshan._
23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants}
24import utils._
25import utility._
26import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
27import freechips.rocketchip.tilelink._
28
29/* ptw cache caches the page table of all the three layers
30 * ptw cache resp at next cycle
31 * the cache should not be blocked
32 * when miss queue if full, just block req outside
33 */
34
35class PageCachePerPespBundle(implicit p: Parameters) extends PtwBundle {
36  val hit = Bool()
37  val pre = Bool()
38  val ppn = UInt(gvpnLen.W)
39  val perm = new PtePermBundle()
40  val ecc = Bool()
41  val level = UInt(2.W)
42  val v = Bool()
43
44  def apply(hit: Bool, pre: Bool, ppn: UInt, perm: PtePermBundle = 0.U.asTypeOf(new PtePermBundle()),
45            ecc: Bool = false.B, level: UInt = 0.U, valid: Bool = true.B) {
46    this.hit := hit && !ecc
47    this.pre := pre
48    this.ppn := ppn
49    this.perm := perm
50    this.ecc := ecc && hit
51    this.level := level
52    this.v := valid
53  }
54}
55
56class PageCacheMergePespBundle(implicit p: Parameters) extends PtwBundle {
57  assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!")
58  val hit = Bool()
59  val pre = Bool()
60  val ppn = Vec(tlbcontiguous, UInt(gvpnLen.W))
61  val perm = Vec(tlbcontiguous, new PtePermBundle())
62  val ecc = Bool()
63  val level = UInt(2.W)
64  val v = Vec(tlbcontiguous, Bool())
65
66  def apply(hit: Bool, pre: Bool, ppn: Vec[UInt], perm: Vec[PtePermBundle] = Vec(tlbcontiguous, 0.U.asTypeOf(new PtePermBundle())),
67            ecc: Bool = false.B, level: UInt = 0.U, valid: Vec[Bool] = Vec(tlbcontiguous, true.B)) {
68    this.hit := hit && !ecc
69    this.pre := pre
70    this.ppn := ppn
71    this.perm := perm
72    this.ecc := ecc && hit
73    this.level := level
74    this.v := valid
75  }
76}
77
78class PageCacheRespBundle(implicit p: Parameters) extends PtwBundle {
79  val l1 = new PageCachePerPespBundle
80  val l2 = new PageCachePerPespBundle
81  val l3 = new PageCacheMergePespBundle
82  val sp = new PageCachePerPespBundle
83}
84
85class PtwCacheReq(implicit p: Parameters) extends PtwBundle {
86  val req_info = new L2TlbInnerBundle()
87  val isFirst = Bool()
88  val bypassed = Vec(3, Bool())
89  val isHptwReq = Bool()
90  val hptwId = UInt(log2Up(l2tlbParams.llptwsize).W)
91}
92
93class PtwCacheIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst {
94  val req = Flipped(DecoupledIO(new PtwCacheReq()))
95  val resp = DecoupledIO(new Bundle {
96    val req_info = new L2TlbInnerBundle()
97    val isFirst = Bool()
98    val hit = Bool()
99    val prefetch = Bool() // is the entry fetched by prefetch
100    val bypassed = Bool()
101    val toFsm = new Bundle {
102      val l1Hit = Bool()
103      val l2Hit = Bool()
104      val ppn = UInt(gvpnLen.W)
105      val stage1Hit = Bool() // find stage 1 pte in cache, but need to search stage 2 pte in cache at PTW
106    }
107    val toTlb = new PtwMergeResp()
108    val isHptwReq = Bool()
109    val toHptw = new Bundle {
110      val l1Hit = Bool()
111      val l2Hit = Bool()
112      val ppn = UInt(ppnLen.W)
113      val id = UInt(log2Up(l2tlbParams.llptwsize).W)
114      val resp = new HptwResp() // used if hit
115      val bypassed = Bool()
116    }
117  })
118  val refill = Flipped(ValidIO(new Bundle {
119    val ptes = UInt(blockBits.W)
120    val levelOH = new Bundle {
121      // NOTE: levelOH has (Level+1) bits, each stands for page cache entries
122      val sp = Bool()
123      val l3 = Bool()
124      val l2 = Bool()
125      val l1 = Bool()
126      def apply(levelUInt: UInt, valid: Bool) = {
127        sp := GatedValidRegNext((levelUInt === 0.U || levelUInt === 1.U) && valid, false.B)
128        l3 := GatedValidRegNext((levelUInt === 2.U) & valid, false.B)
129        l2 := GatedValidRegNext((levelUInt === 1.U) & valid, false.B)
130        l1 := GatedValidRegNext((levelUInt === 0.U) & valid, false.B)
131      }
132    }
133    // duplicate level and sel_pte for each page caches, for better fanout
134    val req_info_dup = Vec(3, new L2TlbInnerBundle())
135    val level_dup = Vec(3, UInt(log2Up(Level).W))
136    val sel_pte_dup = Vec(3, UInt(XLEN.W))
137  }))
138  val sfence_dup = Vec(4, Input(new SfenceBundle()))
139  val csr_dup = Vec(3, Input(new TlbCsrBundle()))
140}
141
142class PtwCache()(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents {
143  val io = IO(new PtwCacheIO)
144  val ecc = Code.fromString(l2tlbParams.ecc)
145  val l2EntryType = new PTWEntriesWithEcc(ecc, num = PtwL2SectorSize, tagLen = PtwL2TagLen, level = 1, hasPerm = false)
146  val l3EntryType = new PTWEntriesWithEcc(ecc, num = PtwL3SectorSize, tagLen = PtwL3TagLen, level = 2, hasPerm = true)
147
148  // TODO: four caches make the codes dirty, think about how to deal with it
149
150  val sfence_dup = io.sfence_dup
151  val refill = io.refill.bits
152  val refill_prefetch_dup = io.refill.bits.req_info_dup.map(a => from_pre(a.source))
153  val flush_dup = sfence_dup.zip(io.csr_dup).map(f => f._1.valid || f._2.satp.changed || f._2.vsatp.changed || f._2.hgatp.changed)
154  val flush = flush_dup(0)
155
156  // when refill, refuce to accept new req
157  val rwHarzad = if (sramSinglePort) io.refill.valid else false.B
158
159  // handle hand signal and req_info
160  // TODO: replace with FlushableQueue
161  val stageReq = Wire(Decoupled(new PtwCacheReq()))         // enq stage & read page cache valid
162  val stageDelay = Wire(Vec(2, Decoupled(new PtwCacheReq()))) // page cache resp
163  val stageCheck = Wire(Vec(2, Decoupled(new PtwCacheReq()))) // check hit & check ecc
164  val stageResp = Wire(Decoupled(new PtwCacheReq()))         // deq stage
165
166  val stageDelay_valid_1cycle = OneCycleValid(stageReq.fire, flush)      // catch ram data
167  val stageCheck_valid_1cycle = OneCycleValid(stageDelay(1).fire, flush) // replace & perf counter
168  val stageResp_valid_1cycle_dup = Wire(Vec(2, Bool()))
169  stageResp_valid_1cycle_dup.map(_ := OneCycleValid(stageCheck(1).fire, flush))  // ecc flush
170
171  stageReq <> io.req
172  PipelineConnect(stageReq, stageDelay(0), stageDelay(1).ready, flush, rwHarzad)
173  InsideStageConnect(stageDelay(0), stageDelay(1), stageDelay_valid_1cycle)
174  PipelineConnect(stageDelay(1), stageCheck(0), stageCheck(1).ready, flush)
175  InsideStageConnect(stageCheck(0), stageCheck(1), stageCheck_valid_1cycle)
176  PipelineConnect(stageCheck(1), stageResp, io.resp.ready, flush)
177  stageResp.ready := !stageResp.valid || io.resp.ready
178
179  // l1: level 0 non-leaf pte
180  val l1 = Reg(Vec(l2tlbParams.l1Size, new PtwEntry(tagLen = PtwL1TagLen)))
181  val l1v = RegInit(0.U(l2tlbParams.l1Size.W))
182  val l1g = Reg(UInt(l2tlbParams.l1Size.W))
183  val l1asids = l1.map(_.asid)
184  val l1vmids = l1.map(_.vmid)
185  val l1h = Reg(Vec(l2tlbParams.l1Size, UInt(2.W)))
186
187  // l2: level 1 non-leaf pte
188  val l2 = Module(new SRAMTemplate(
189    l2EntryType,
190    set = l2tlbParams.l2nSets,
191    way = l2tlbParams.l2nWays,
192    singlePort = sramSinglePort
193  ))
194  val l2v = RegInit(0.U((l2tlbParams.l2nSets * l2tlbParams.l2nWays).W))
195  val l2g = Reg(UInt((l2tlbParams.l2nSets * l2tlbParams.l2nWays).W))
196  val l2h = Reg(Vec(l2tlbParams.l2nSets, Vec(l2tlbParams.l2nWays, UInt(2.W))))
197  def getl2vSet(vpn: UInt) = {
198    require(log2Up(l2tlbParams.l2nWays) == log2Down(l2tlbParams.l2nWays))
199    val set = genPtwL2SetIdx(vpn)
200    require(set.getWidth == log2Up(l2tlbParams.l2nSets))
201    val l2vVec = l2v.asTypeOf(Vec(l2tlbParams.l2nSets, UInt(l2tlbParams.l2nWays.W)))
202    l2vVec(set)
203  }
204  def getl2hSet(vpn: UInt) = {
205    require(log2Up(l2tlbParams.l2nWays) == log2Down(l2tlbParams.l2nWays))
206    val set = genPtwL2SetIdx(vpn)
207    require(set.getWidth == log2Up(l2tlbParams.l2nSets))
208    l2h(set)
209  }
210
211
212
213  // l3: level 2 leaf pte of 4KB pages
214  val l3 = Module(new SRAMTemplate(
215    l3EntryType,
216    set = l2tlbParams.l3nSets,
217    way = l2tlbParams.l3nWays,
218    singlePort = sramSinglePort
219  ))
220  val l3v = RegInit(0.U((l2tlbParams.l3nSets * l2tlbParams.l3nWays).W))
221  val l3g = Reg(UInt((l2tlbParams.l3nSets * l2tlbParams.l3nWays).W))
222  val l3h = Reg(Vec(l2tlbParams.l3nSets, Vec(l2tlbParams.l3nWays, UInt(2.W))))
223  def getl3vSet(vpn: UInt) = {
224    require(log2Up(l2tlbParams.l3nWays) == log2Down(l2tlbParams.l3nWays))
225    val set = genPtwL3SetIdx(vpn)
226    require(set.getWidth == log2Up(l2tlbParams.l3nSets))
227    val l3vVec = l3v.asTypeOf(Vec(l2tlbParams.l3nSets, UInt(l2tlbParams.l3nWays.W)))
228    l3vVec(set)
229  }
230  def getl3hSet(vpn: UInt) = {
231    require(log2Up(l2tlbParams.l3nWays) == log2Down(l2tlbParams.l3nWays))
232    val set = genPtwL3SetIdx(vpn)
233    require(set.getWidth == log2Up(l2tlbParams.l3nSets))
234    l3h(set)
235  }
236
237  // sp: level 0/1 leaf pte of 1GB/2MB super pages
238  val sp = Reg(Vec(l2tlbParams.spSize, new PtwEntry(tagLen = SPTagLen, hasPerm = true, hasLevel = true)))
239  val spv = RegInit(0.U(l2tlbParams.spSize.W))
240  val spg = Reg(UInt(l2tlbParams.spSize.W))
241  val spasids = sp.map(_.asid)
242  val spvmids = sp.map(_.vmid)
243  val sph = Reg(Vec(l2tlbParams.spSize, UInt(2.W)))
244
245  // Access Perf
246  val l1AccessPerf = Wire(Vec(l2tlbParams.l1Size, Bool()))
247  val l2AccessPerf = Wire(Vec(l2tlbParams.l2nWays, Bool()))
248  val l3AccessPerf = Wire(Vec(l2tlbParams.l3nWays, Bool()))
249  val spAccessPerf = Wire(Vec(l2tlbParams.spSize, Bool()))
250  l1AccessPerf.map(_ := false.B)
251  l2AccessPerf.map(_ := false.B)
252  l3AccessPerf.map(_ := false.B)
253  spAccessPerf.map(_ := false.B)
254
255
256
257  def vpn_match(vpn1: UInt, vpn2: UInt, level: Int) = {
258    (vpn1(vpnLen-1, vpnnLen*(2-level)+3) === vpn2(vpnLen-1, vpnnLen*(2-level)+3))
259  }
260  // NOTE: not actually bypassed, just check if hit, re-access the page cache
261  def refill_bypass(vpn: UInt, level: Int, h_search: UInt) = {
262    val change_h = MuxLookup(h_search, noS2xlate)(Seq(
263      allStage -> onlyStage1,
264      onlyStage1 -> onlyStage1,
265      onlyStage2 -> onlyStage2
266    ))
267    val refill_vpn = io.refill.bits.req_info_dup(0).vpn
268    io.refill.valid && (level.U === io.refill.bits.level_dup(0)) && vpn_match(refill_vpn, vpn, level) && change_h === io.refill.bits.req_info_dup(0).s2xlate
269  }
270
271  val vpn_search = stageReq.bits.req_info.vpn
272  val h_search = MuxLookup(stageReq.bits.req_info.s2xlate, noS2xlate)(Seq(
273    allStage -> onlyStage1,
274    onlyStage1 -> onlyStage1,
275    onlyStage2 -> onlyStage2
276  ))
277  // l1
278  val ptwl1replace = ReplacementPolicy.fromString(l2tlbParams.l1Replacer, l2tlbParams.l1Size)
279  val (l1Hit, l1HitPPN, l1Pre) = {
280    val hitVecT = l1.zipWithIndex.map {
281      case (e, i) => (e.hit(vpn_search, io.csr_dup(0).satp.asid, io.csr_dup(0).vsatp.asid, io.csr_dup(0).hgatp.asid, s2xlate = h_search =/= noS2xlate)
282        && l1v(i) && h_search === l1h(i))
283    }
284    val hitVec = hitVecT.map(RegEnable(_, stageReq.fire))
285
286    // stageDelay, but check for l1
287    val hitPPN = DataHoldBypass(ParallelPriorityMux(hitVec zip l1.map(_.ppn)), stageDelay_valid_1cycle)
288    val hitPre = DataHoldBypass(ParallelPriorityMux(hitVec zip l1.map(_.prefetch)), stageDelay_valid_1cycle)
289    val hit = DataHoldBypass(ParallelOR(hitVec), stageDelay_valid_1cycle)
290
291    when (hit && stageDelay_valid_1cycle) { ptwl1replace.access(OHToUInt(hitVec)) }
292
293    l1AccessPerf.zip(hitVec).map{ case (l, h) => l := h && stageDelay_valid_1cycle}
294    for (i <- 0 until l2tlbParams.l1Size) {
295      XSDebug(stageReq.fire, p"[l1] l1(${i.U}) ${l1(i)} hit:${l1(i).hit(vpn_search, io.csr_dup(0).satp.asid, io.csr_dup(0).vsatp.asid, io.csr_dup(0).hgatp.asid, s2xlate = h_search =/= noS2xlate)}\n")
296    }
297    XSDebug(stageReq.fire, p"[l1] l1v:${Binary(l1v)} hitVecT:${Binary(VecInit(hitVecT).asUInt)}\n")
298    XSDebug(stageDelay(0).valid, p"[l1] l1Hit:${hit} l1HitPPN:0x${Hexadecimal(hitPPN)} hitVec:${VecInit(hitVec).asUInt}\n")
299
300    VecInit(hitVecT).suggestName(s"l1_hitVecT")
301    VecInit(hitVec).suggestName(s"l1_hitVec")
302
303    // synchronize with other entries with RegEnable
304    (RegEnable(hit, stageDelay(1).fire),
305     RegEnable(hitPPN, stageDelay(1).fire),
306     RegEnable(hitPre, stageDelay(1).fire))
307  }
308
309  // l2
310  val ptwl2replace = ReplacementPolicy.fromString(l2tlbParams.l2Replacer,l2tlbParams.l2nWays,l2tlbParams.l2nSets)
311  val (l2Hit, l2HitPPN, l2Pre, l2eccError) = {
312    val ridx = genPtwL2SetIdx(vpn_search)
313    l2.io.r.req.valid := stageReq.fire
314    l2.io.r.req.bits.apply(setIdx = ridx)
315    val vVec_req = getl2vSet(vpn_search)
316    val hVec_req = getl2hSet(vpn_search)
317
318    // delay one cycle after sram read
319    val delay_vpn = stageDelay(0).bits.req_info.vpn
320    val delay_h = MuxLookup(stageDelay(0).bits.req_info.s2xlate, noS2xlate)(Seq(
321      allStage -> onlyStage1,
322      onlyStage1 -> onlyStage1,
323      onlyStage2 -> onlyStage2
324    ))
325    val data_resp = DataHoldBypass(l2.io.r.resp.data, stageDelay_valid_1cycle)
326    val vVec_delay = RegEnable(vVec_req, stageReq.fire)
327    val hVec_delay = RegEnable(hVec_req, stageReq.fire)
328    val hitVec_delay = VecInit(data_resp.zip(vVec_delay.asBools).zip(hVec_delay).map { case ((wayData, v), h) =>
329      wayData.entries.hit(delay_vpn, io.csr_dup(1).satp.asid, io.csr_dup(1).vsatp.asid, io.csr_dup(1).hgatp.asid, s2xlate = delay_h =/= noS2xlate) && v && (delay_h === h)})
330
331    // check hit and ecc
332    val check_vpn = stageCheck(0).bits.req_info.vpn
333    val ramDatas = RegEnable(data_resp, stageDelay(1).fire)
334    val vVec = RegEnable(vVec_delay, stageDelay(1).fire).asBools
335
336    val hitVec = RegEnable(hitVec_delay, stageDelay(1).fire)
337    val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas)
338    val hitWayData = hitWayEntry.entries
339    val hit = ParallelOR(hitVec)
340    val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l2nWays).map(_.U(log2Up(l2tlbParams.l2nWays).W)))
341    val eccError = WireInit(false.B)
342    if (l2tlbParams.enablePTWECC) {
343      eccError := hitWayEntry.decode()
344    } else {
345      eccError := false.B
346    }
347
348    ridx.suggestName(s"l2_ridx")
349    ramDatas.suggestName(s"l2_ramDatas")
350    hitVec.suggestName(s"l2_hitVec")
351    hitWayData.suggestName(s"l2_hitWayData")
352    hitWay.suggestName(s"l2_hitWay")
353
354    when (hit && stageCheck_valid_1cycle) { ptwl2replace.access(genPtwL2SetIdx(check_vpn), hitWay) }
355
356    l2AccessPerf.zip(hitVec).map{ case (l, h) => l := h && stageCheck_valid_1cycle }
357    XSDebug(stageDelay_valid_1cycle, p"[l2] ridx:0x${Hexadecimal(ridx)}\n")
358    for (i <- 0 until l2tlbParams.l2nWays) {
359      XSDebug(stageCheck_valid_1cycle, p"[l2] ramDatas(${i.U}) ${ramDatas(i)}  l2v:${vVec(i)}  hit:${hit}\n")
360    }
361    XSDebug(stageCheck_valid_1cycle, p"[l2] l2Hit:${hit} l2HitPPN:0x${Hexadecimal(hitWayData.ppns(genPtwL2SectorIdx(check_vpn)))} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} vidx:${vVec}\n")
362
363    (hit, hitWayData.ppns(genPtwL2SectorIdx(check_vpn)), hitWayData.prefetch, eccError)
364  }
365
366  // l3
367  val ptwl3replace = ReplacementPolicy.fromString(l2tlbParams.l3Replacer,l2tlbParams.l3nWays,l2tlbParams.l3nSets)
368  val (l3Hit, l3HitData, l3Pre, l3eccError) = {
369    val ridx = genPtwL3SetIdx(vpn_search)
370    l3.io.r.req.valid := stageReq.fire
371    l3.io.r.req.bits.apply(setIdx = ridx)
372    val vVec_req = getl3vSet(vpn_search)
373    val hVec_req = getl3hSet(vpn_search)
374
375    // delay one cycle after sram read
376    val delay_vpn = stageDelay(0).bits.req_info.vpn
377    val delay_h = MuxLookup(stageDelay(0).bits.req_info.s2xlate, noS2xlate)(Seq(
378      allStage -> onlyStage1,
379      onlyStage1 -> onlyStage1,
380      onlyStage2 -> onlyStage2
381    ))
382    val data_resp = DataHoldBypass(l3.io.r.resp.data, stageDelay_valid_1cycle)
383    val vVec_delay = RegEnable(vVec_req, stageReq.fire)
384    val hVec_delay = RegEnable(hVec_req, stageReq.fire)
385    val hitVec_delay = VecInit(data_resp.zip(vVec_delay.asBools).zip(hVec_delay).map { case ((wayData, v), h) =>
386      wayData.entries.hit(delay_vpn, io.csr_dup(2).satp.asid, io.csr_dup(2).vsatp.asid, io.csr_dup(2).hgatp.asid, s2xlate = delay_h =/= noS2xlate) && v && (delay_h === h)})
387
388    // check hit and ecc
389    val check_vpn = stageCheck(0).bits.req_info.vpn
390    val ramDatas = RegEnable(data_resp, stageDelay(1).fire)
391    val vVec = RegEnable(vVec_delay, stageDelay(1).fire).asBools
392
393    val hitVec = RegEnable(hitVec_delay, stageDelay(1).fire)
394    val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas)
395    val hitWayData = hitWayEntry.entries
396    val hitWayEcc = hitWayEntry.ecc
397    val hit = ParallelOR(hitVec)
398    val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l3nWays).map(_.U(log2Up(l2tlbParams.l3nWays).W)))
399    val eccError = WireInit(false.B)
400    if (l2tlbParams.enablePTWECC) {
401      eccError := hitWayEntry.decode()
402    } else {
403      eccError := false.B
404    }
405
406    when (hit && stageCheck_valid_1cycle) { ptwl3replace.access(genPtwL3SetIdx(check_vpn), hitWay) }
407
408    l3AccessPerf.zip(hitVec).map{ case (l, h) => l := h && stageCheck_valid_1cycle }
409    XSDebug(stageReq.fire, p"[l3] ridx:0x${Hexadecimal(ridx)}\n")
410    for (i <- 0 until l2tlbParams.l3nWays) {
411      XSDebug(stageCheck_valid_1cycle, p"[l3] ramDatas(${i.U}) ${ramDatas(i)}  l3v:${vVec(i)}  hit:${hitVec(i)}\n")
412    }
413    XSDebug(stageCheck_valid_1cycle, p"[l3] l3Hit:${hit} l3HitData:${hitWayData} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} v:${vVec}\n")
414
415    ridx.suggestName(s"l3_ridx")
416    ramDatas.suggestName(s"l3_ramDatas")
417    hitVec.suggestName(s"l3_hitVec")
418    hitWay.suggestName(s"l3_hitWay")
419
420    (hit, hitWayData, hitWayData.prefetch, eccError)
421  }
422  val l3HitPPN = l3HitData.ppns
423  val l3HitPerm = l3HitData.perms.getOrElse(0.U.asTypeOf(Vec(PtwL3SectorSize, new PtePermBundle)))
424  val l3HitValid = l3HitData.vs
425
426  // super page
427  val spreplace = ReplacementPolicy.fromString(l2tlbParams.spReplacer, l2tlbParams.spSize)
428  val (spHit, spHitData, spPre, spValid) = {
429    val hitVecT = sp.zipWithIndex.map { case (e, i) => e.hit(vpn_search, io.csr_dup(0).satp.asid, io.csr_dup(0).vsatp.asid, io.csr_dup(0).hgatp.asid, s2xlate = h_search =/= noS2xlate) && spv(i) && (sph(i) === h_search) }
430    val hitVec = hitVecT.map(RegEnable(_, stageReq.fire))
431    val hitData = ParallelPriorityMux(hitVec zip sp)
432    val hit = ParallelOR(hitVec)
433
434    when (hit && stageDelay_valid_1cycle) { spreplace.access(OHToUInt(hitVec)) }
435
436    spAccessPerf.zip(hitVec).map{ case (s, h) => s := h && stageDelay_valid_1cycle }
437    for (i <- 0 until l2tlbParams.spSize) {
438      XSDebug(stageReq.fire, p"[sp] sp(${i.U}) ${sp(i)} hit:${sp(i).hit(vpn_search, io.csr_dup(0).satp.asid, io.csr_dup(0).vsatp.asid, io.csr_dup(0).hgatp.asid, s2xlate = h_search =/= noS2xlate)} spv:${spv(i)}\n")
439    }
440    XSDebug(stageDelay_valid_1cycle, p"[sp] spHit:${hit} spHitData:${hitData} hitVec:${Binary(VecInit(hitVec).asUInt)}\n")
441
442    VecInit(hitVecT).suggestName(s"sp_hitVecT")
443    VecInit(hitVec).suggestName(s"sp_hitVec")
444
445    (RegEnable(hit, stageDelay(1).fire),
446     RegEnable(hitData, stageDelay(1).fire),
447     RegEnable(hitData.prefetch, stageDelay(1).fire),
448     RegEnable(hitData.v, stageDelay(1).fire))
449  }
450  val spHitPerm = spHitData.perm.getOrElse(0.U.asTypeOf(new PtePermBundle))
451  val spHitLevel = spHitData.level.getOrElse(0.U)
452
453  val check_res = Wire(new PageCacheRespBundle)
454  check_res.l1.apply(l1Hit, l1Pre, l1HitPPN)
455  check_res.l2.apply(l2Hit, l2Pre, l2HitPPN, ecc = l2eccError)
456  check_res.l3.apply(l3Hit, l3Pre, l3HitPPN, l3HitPerm, l3eccError, valid = l3HitValid)
457  check_res.sp.apply(spHit, spPre, spHitData.ppn, spHitPerm, false.B, spHitLevel, spValid)
458
459  val resp_res = Reg(new PageCacheRespBundle)
460  when (stageCheck(1).fire) { resp_res := check_res }
461
462  // stageResp bypass
463  val bypassed = Wire(Vec(3, Bool()))
464  bypassed.indices.foreach(i =>
465    bypassed(i) := stageResp.bits.bypassed(i) ||
466      ValidHoldBypass(refill_bypass(stageResp.bits.req_info.vpn, i, stageResp.bits.req_info.s2xlate),
467        OneCycleValid(stageCheck(1).fire, false.B) || io.refill.valid)
468  )
469
470  // stageResp bypass to hptw
471  val hptw_bypassed = Wire(Vec(3, Bool()))
472  hptw_bypassed.indices.foreach(i =>
473    hptw_bypassed(i) := stageResp.bits.bypassed(i) ||
474      ValidHoldBypass(refill_bypass(stageResp.bits.req_info.vpn, i, stageResp.bits.req_info.s2xlate),
475        io.resp.fire)
476  )
477
478  val isAllStage = stageResp.bits.req_info.s2xlate === allStage
479  val isOnlyStage2 = stageResp.bits.req_info.s2xlate === onlyStage2
480  val stage1Hit = (resp_res.l3.hit || resp_res.sp.hit) && isAllStage
481  io.resp.bits.req_info   := stageResp.bits.req_info
482  io.resp.bits.isFirst  := stageResp.bits.isFirst
483  io.resp.bits.hit      := (resp_res.l3.hit || resp_res.sp.hit) && !isAllStage
484  io.resp.bits.bypassed := (bypassed(2) || (bypassed(1) && !resp_res.l2.hit) || (bypassed(0) && !resp_res.l1.hit)) && !isAllStage
485  io.resp.bits.prefetch := resp_res.l3.pre && resp_res.l3.hit || resp_res.sp.pre && resp_res.sp.hit
486  io.resp.bits.toFsm.l1Hit := resp_res.l1.hit && !stage1Hit && !isOnlyStage2 && !stageResp.bits.isHptwReq
487  io.resp.bits.toFsm.l2Hit := resp_res.l2.hit && !stage1Hit && !isOnlyStage2 && !stageResp.bits.isHptwReq
488  io.resp.bits.toFsm.ppn   := Mux(resp_res.l2.hit, resp_res.l2.ppn, resp_res.l1.ppn)
489  io.resp.bits.toFsm.stage1Hit := stage1Hit
490
491  io.resp.bits.isHptwReq := stageResp.bits.isHptwReq
492  io.resp.bits.toHptw.bypassed := (hptw_bypassed(2) || (hptw_bypassed(1) && !resp_res.l2.hit) || (hptw_bypassed(0) && !resp_res.l1.hit)) && stageResp.bits.isHptwReq
493  io.resp.bits.toHptw.id := stageResp.bits.hptwId
494  io.resp.bits.toHptw.l1Hit := resp_res.l1.hit && stageResp.bits.isHptwReq
495  io.resp.bits.toHptw.l2Hit := resp_res.l2.hit && stageResp.bits.isHptwReq
496  io.resp.bits.toHptw.ppn := Mux(resp_res.l2.hit, resp_res.l2.ppn, resp_res.l1.ppn)(ppnLen - 1, 0)
497  val idx = stageResp.bits.req_info.vpn(2, 0)
498  io.resp.bits.toHptw.resp.entry.tag := stageResp.bits.req_info.vpn
499  io.resp.bits.toHptw.resp.entry.asid := DontCare
500  io.resp.bits.toHptw.resp.entry.vmid.map(_ := io.csr_dup(0).hgatp.asid)
501  io.resp.bits.toHptw.resp.entry.level.map(_ := Mux(resp_res.l3.hit, 2.U, resp_res.sp.level))
502  io.resp.bits.toHptw.resp.entry.prefetch := from_pre(stageResp.bits.req_info.source)
503  io.resp.bits.toHptw.resp.entry.ppn := Mux(resp_res.l3.hit, resp_res.l3.ppn(idx), resp_res.sp.ppn)(ppnLen - 1, 0)
504  io.resp.bits.toHptw.resp.entry.perm.map(_ := Mux(resp_res.l3.hit, resp_res.l3.perm(idx), resp_res.sp.perm))
505  io.resp.bits.toHptw.resp.entry.v := Mux(resp_res.l3.hit, resp_res.l3.v(idx), resp_res.sp.v)
506  io.resp.bits.toHptw.resp.gpf := !io.resp.bits.toHptw.resp.entry.v
507  io.resp.bits.toHptw.resp.gaf := false.B
508
509  io.resp.bits.toTlb.entry.map(_.tag := stageResp.bits.req_info.vpn(vpnLen - 1, 3))
510  io.resp.bits.toTlb.entry.map(_.asid := Mux(stageResp.bits.req_info.hasS2xlate(), io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid)) // DontCare
511  io.resp.bits.toTlb.entry.map(_.vmid.map(_ := io.csr_dup(0).hgatp.asid))
512  io.resp.bits.toTlb.entry.map(_.level.map(_ := Mux(resp_res.l3.hit, 2.U, resp_res.sp.level)))
513  io.resp.bits.toTlb.entry.map(_.prefetch := from_pre(stageResp.bits.req_info.source))
514  for (i <- 0 until tlbcontiguous) {
515    io.resp.bits.toTlb.entry(i).ppn := Mux(resp_res.l3.hit, resp_res.l3.ppn(i)(gvpnLen - 1, sectortlbwidth), resp_res.sp.ppn(gvpnLen - 1, sectortlbwidth))
516    io.resp.bits.toTlb.entry(i).ppn_low := Mux(resp_res.l3.hit, resp_res.l3.ppn(i)(sectortlbwidth - 1, 0), resp_res.sp.ppn(sectortlbwidth - 1, 0))
517    io.resp.bits.toTlb.entry(i).perm.map(_ := Mux(resp_res.l3.hit, resp_res.l3.perm(i), resp_res.sp.perm))
518    io.resp.bits.toTlb.entry(i).v := Mux(resp_res.l3.hit, resp_res.l3.v(i), resp_res.sp.v)
519    io.resp.bits.toTlb.entry(i).pf := !io.resp.bits.toTlb.entry(i).v
520    io.resp.bits.toTlb.entry(i).af := false.B
521  }
522  io.resp.bits.toTlb.pteidx := UIntToOH(stageResp.bits.req_info.vpn(2, 0)).asBools
523  io.resp.bits.toTlb.not_super := Mux(resp_res.l3.hit, true.B, false.B)
524  io.resp.valid := stageResp.valid
525  XSError(stageResp.valid && resp_res.l3.hit && resp_res.sp.hit, "normal page and super page both hit")
526  XSError(stageResp.valid && io.resp.bits.hit && bypassed(2), "page cache, bypassed but hit")
527
528  // refill Perf
529  val l1RefillPerf = Wire(Vec(l2tlbParams.l1Size, Bool()))
530  val l2RefillPerf = Wire(Vec(l2tlbParams.l2nWays, Bool()))
531  val l3RefillPerf = Wire(Vec(l2tlbParams.l3nWays, Bool()))
532  val spRefillPerf = Wire(Vec(l2tlbParams.spSize, Bool()))
533  l1RefillPerf.map(_ := false.B)
534  l2RefillPerf.map(_ := false.B)
535  l3RefillPerf.map(_ := false.B)
536  spRefillPerf.map(_ := false.B)
537
538  // refill
539  l2.io.w.req <> DontCare
540  l3.io.w.req <> DontCare
541  l2.io.w.req.valid := false.B
542  l3.io.w.req.valid := false.B
543
544  val memRdata = refill.ptes
545  val memPtes = (0 until (l2tlbParams.blockBytes/(XLEN/8))).map(i => memRdata((i+1)*XLEN-1, i*XLEN).asTypeOf(new PteBundle))
546  val memSelData = io.refill.bits.sel_pte_dup
547  val memPte = memSelData.map(a => a.asTypeOf(new PteBundle))
548
549  // TODO: handle sfenceLatch outsize
550  when (!flush_dup(0) && refill.levelOH.l1 && !memPte(0).isLeaf() && !memPte(0).isPf(refill.level_dup(0)) && !memPte(0).isAf()) {
551    // val refillIdx = LFSR64()(log2Up(l2tlbParams.l1Size)-1,0) // TODO: may be LRU
552    val refillIdx = replaceWrapper(l1v, ptwl1replace.way)
553    refillIdx.suggestName(s"PtwL1RefillIdx")
554    val rfOH = UIntToOH(refillIdx)
555    l1(refillIdx).refill(
556      refill.req_info_dup(0).vpn,
557      Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid),
558      io.csr_dup(0).hgatp.asid,
559      memSelData(0),
560      0.U,
561      refill_prefetch_dup(0)
562    )
563    ptwl1replace.access(refillIdx)
564    l1v := l1v | rfOH
565    l1g := (l1g & ~rfOH) | Mux(memPte(0).perm.g, rfOH, 0.U)
566    l1h(refillIdx) := refill.req_info_dup(0).s2xlate
567
568    for (i <- 0 until l2tlbParams.l1Size) {
569      l1RefillPerf(i) := i.U === refillIdx
570    }
571
572    XSDebug(p"[l1 refill] refillIdx:${refillIdx} refillEntry:${l1(refillIdx).genPtwEntry(refill.req_info_dup(0).vpn, Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid), memSelData(0), 0.U, prefetch = refill_prefetch_dup(0))}\n")
573    XSDebug(p"[l1 refill] l1v:${Binary(l1v)}->${Binary(l1v | rfOH)} l1g:${Binary(l1g)}->${Binary((l1g & ~rfOH) | Mux(memPte(0).perm.g, rfOH, 0.U))}\n")
574
575    refillIdx.suggestName(s"l1_refillIdx")
576    rfOH.suggestName(s"l1_rfOH")
577  }
578
579  when (!flush_dup(1) && refill.levelOH.l2 && !memPte(1).isLeaf() && !memPte(1).isPf(refill.level_dup(1)) && !memPte(1).isAf()) {
580    val refillIdx = genPtwL2SetIdx(refill.req_info_dup(1).vpn)
581    val victimWay = replaceWrapper(getl2vSet(refill.req_info_dup(1).vpn), ptwl2replace.way(refillIdx))
582    val victimWayOH = UIntToOH(victimWay)
583    val rfvOH = UIntToOH(Cat(refillIdx, victimWay))
584    val wdata = Wire(l2EntryType)
585    wdata.gen(
586      vpn = refill.req_info_dup(1).vpn,
587      asid = Mux(refill.req_info_dup(1).s2xlate =/= noS2xlate, io.csr_dup(1).vsatp.asid, io.csr_dup(1).satp.asid),
588      vmid = io.csr_dup(1).hgatp.asid,
589      data = memRdata,
590      levelUInt = 1.U,
591      refill_prefetch_dup(1)
592    )
593    l2.io.w.apply(
594      valid = true.B,
595      setIdx = refillIdx,
596      data = wdata,
597      waymask = victimWayOH
598    )
599    ptwl2replace.access(refillIdx, victimWay)
600    l2v := l2v | rfvOH
601    l2g := l2g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U)
602    l2h(refillIdx)(victimWay) := refill.req_info_dup(1).s2xlate
603
604    for (i <- 0 until l2tlbParams.l2nWays) {
605      l2RefillPerf(i) := i.U === victimWay
606    }
607
608    XSDebug(p"[l2 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n")
609    XSDebug(p"[l2 refill] refilldata:0x${wdata}\n")
610    XSDebug(p"[l2 refill] l2v:${Binary(l2v)} -> ${Binary(l2v | rfvOH)}\n")
611    XSDebug(p"[l2 refill] l2g:${Binary(l2g)} -> ${Binary(l2g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n")
612
613    refillIdx.suggestName(s"l2_refillIdx")
614    victimWay.suggestName(s"l2_victimWay")
615    victimWayOH.suggestName(s"l2_victimWayOH")
616    rfvOH.suggestName(s"l2_rfvOH")
617  }
618
619  when (!flush_dup(2) && refill.levelOH.l3) {
620    val refillIdx = genPtwL3SetIdx(refill.req_info_dup(2).vpn)
621    val victimWay = replaceWrapper(getl3vSet(refill.req_info_dup(2).vpn), ptwl3replace.way(refillIdx))
622    val victimWayOH = UIntToOH(victimWay)
623    val rfvOH = UIntToOH(Cat(refillIdx, victimWay))
624    val wdata = Wire(l3EntryType)
625    wdata.gen(
626      vpn =  refill.req_info_dup(2).vpn,
627      asid = Mux(refill.req_info_dup(2).s2xlate =/= noS2xlate, io.csr_dup(2).vsatp.asid, io.csr_dup(2).satp.asid),
628      vmid = io.csr_dup(2).hgatp.asid,
629      data = memRdata,
630      levelUInt = 2.U,
631      refill_prefetch_dup(2)
632    )
633    l3.io.w.apply(
634      valid = true.B,
635      setIdx = refillIdx,
636      data = wdata,
637      waymask = victimWayOH
638    )
639    ptwl3replace.access(refillIdx, victimWay)
640    l3v := l3v | rfvOH
641    l3g := l3g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U)
642    l3h(refillIdx)(victimWay) := refill.req_info_dup(2).s2xlate
643
644    for (i <- 0 until l2tlbParams.l3nWays) {
645      l3RefillPerf(i) := i.U === victimWay
646    }
647
648    XSDebug(p"[l3 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n")
649    XSDebug(p"[l3 refill] refilldata:0x${wdata}\n")
650    XSDebug(p"[l3 refill] l3v:${Binary(l3v)} -> ${Binary(l3v | rfvOH)}\n")
651    XSDebug(p"[l3 refill] l3g:${Binary(l3g)} -> ${Binary(l3g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n")
652
653    refillIdx.suggestName(s"l3_refillIdx")
654    victimWay.suggestName(s"l3_victimWay")
655    victimWayOH.suggestName(s"l3_victimWayOH")
656    rfvOH.suggestName(s"l3_rfvOH")
657  }
658
659
660  // misc entries: super & invalid
661  when (!flush_dup(0) && refill.levelOH.sp && (memPte(0).isLeaf() || memPte(0).isPf(refill.level_dup(0))) && !memPte(0).isAf()) {
662    val refillIdx = spreplace.way// LFSR64()(log2Up(l2tlbParams.spSize)-1,0) // TODO: may be LRU
663    val rfOH = UIntToOH(refillIdx)
664    sp(refillIdx).refill(
665      refill.req_info_dup(0).vpn,
666      Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid),
667      io.csr_dup(0).hgatp.asid,
668      memSelData(0),
669      refill.level_dup(2),
670      refill_prefetch_dup(0),
671      !memPte(0).isPf(refill.level_dup(0)),
672    )
673    spreplace.access(refillIdx)
674    spv := spv | rfOH
675    spg := spg & ~rfOH | Mux(memPte(0).perm.g, rfOH, 0.U)
676    sph(refillIdx) := refill.req_info_dup(0).s2xlate
677
678    for (i <- 0 until l2tlbParams.spSize) {
679      spRefillPerf(i) := i.U === refillIdx
680    }
681
682    XSDebug(p"[sp refill] refillIdx:${refillIdx} refillEntry:${sp(refillIdx).genPtwEntry(refill.req_info_dup(0).vpn, Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid), memSelData(0), refill.level_dup(0), refill_prefetch_dup(0))}\n")
683    XSDebug(p"[sp refill] spv:${Binary(spv)}->${Binary(spv | rfOH)} spg:${Binary(spg)}->${Binary(spg & ~rfOH | Mux(memPte(0).perm.g, rfOH, 0.U))}\n")
684
685    refillIdx.suggestName(s"sp_refillIdx")
686    rfOH.suggestName(s"sp_rfOH")
687  }
688
689  val l2eccFlush = resp_res.l2.ecc && stageResp_valid_1cycle_dup(0) // RegNext(l2eccError, init = false.B)
690  val l3eccFlush = resp_res.l3.ecc && stageResp_valid_1cycle_dup(1) // RegNext(l3eccError, init = false.B)
691  val eccVpn = stageResp.bits.req_info.vpn
692
693  XSError(l2eccFlush, "l2tlb.cache.l2 ecc error. Should not happen at sim stage")
694  XSError(l3eccFlush, "l2tlb.cache.l3 ecc error. Should not happen at sim stage")
695  when (l2eccFlush) {
696    val flushSetIdxOH = UIntToOH(genPtwL2SetIdx(eccVpn))
697    val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l2nWays, a.asUInt) }).asUInt
698    l2v := l2v & ~flushMask
699    l2g := l2g & ~flushMask
700  }
701
702  when (l3eccFlush) {
703    val flushSetIdxOH = UIntToOH(genPtwL3SetIdx(eccVpn))
704    val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l3nWays, a.asUInt) }).asUInt
705    l3v := l3v & ~flushMask
706    l3g := l3g & ~flushMask
707  }
708
709  // sfence for l3
710  val sfence_valid_l3 = sfence_dup(3).valid && !sfence_dup(3).bits.hg && !sfence_dup(3).bits.hv
711  when (sfence_valid_l3) {
712    val l3hhit = VecInit(l3h.flatMap(_.map{a => io.csr_dup(0).priv.virt && a === onlyStage1 || !io.csr_dup(0).priv.virt && a === noS2xlate})).asUInt
713    val sfence_vpn = sfence_dup(3).bits.addr(sfence_dup(3).bits.addr.getWidth-1, offLen)
714    when (sfence_dup(3).bits.rs1/*va*/) {
715      when (sfence_dup(3).bits.rs2) {
716        // all va && all asid
717        l3v := l3v & ~l3hhit
718      } .otherwise {
719        // all va && specific asid except global
720        l3v := l3v & (l3g | ~l3hhit)
721      }
722    } .otherwise {
723      // val flushMask = UIntToOH(genTlbL2Idx(sfence.bits.addr(sfence.bits.addr.getWidth-1, offLen)))
724      val flushSetIdxOH = UIntToOH(genPtwL3SetIdx(sfence_vpn))
725      // val flushMask = VecInit(flushSetIdxOH.asBools.map(Fill(l2tlbParams.l3nWays, _.asUInt))).asUInt
726      val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l3nWays, a.asUInt) }).asUInt
727      flushSetIdxOH.suggestName(s"sfence_nrs1_flushSetIdxOH")
728      flushMask.suggestName(s"sfence_nrs1_flushMask")
729
730      when (sfence_dup(3).bits.rs2) {
731        // specific leaf of addr && all asid
732        l3v := l3v & ~flushMask & ~l3hhit
733      } .otherwise {
734        // specific leaf of addr && specific asid
735        l3v := l3v & (~flushMask | l3g | ~l3hhit)
736      }
737    }
738  }
739
740  // hfencev, simple implementation for l3
741  val hfencev_valid_l3 = sfence_dup(3).valid && sfence_dup(3).bits.hv
742  when(hfencev_valid_l3) {
743    val flushMask = VecInit(l3h.flatMap(_.map(_  === onlyStage1))).asUInt
744    l3v := l3v & ~flushMask // all VS-stage l3 pte
745  }
746
747  // hfenceg, simple implementation for l3
748  val hfenceg_valid_l3 = sfence_dup(3).valid && sfence_dup(3).bits.hg
749  when(hfenceg_valid_l3) {
750    val flushMask = VecInit(l3h.flatMap(_.map(_ === onlyStage2))).asUInt
751    l3v := l3v & ~flushMask // all G-stage l3 pte
752  }
753
754
755  val l1asidhit = VecInit(l1asids.map(_ === sfence_dup(0).bits.id)).asUInt
756  val spasidhit = VecInit(spasids.map(_ === sfence_dup(0).bits.id)).asUInt
757  val sfence_valid = sfence_dup(0).valid && !sfence_dup(0).bits.hg && !sfence_dup(0).bits.hv
758  when (sfence_valid) {
759    val l1vmidhit = VecInit(l1vmids.map(_.getOrElse(0.U) === io.csr_dup(0).hgatp.asid)).asUInt
760    val spvmidhit = VecInit(spvmids.map(_.getOrElse(0.U) === io.csr_dup(0).hgatp.asid)).asUInt
761    val l1hhit = VecInit(l1h.map{a => io.csr_dup(0).priv.virt && a === onlyStage1 || !io.csr_dup(0).priv.virt && a === noS2xlate}).asUInt
762    val sphhit = VecInit(sph.map{a => io.csr_dup(0).priv.virt && a === onlyStage1 || !io.csr_dup(0).priv.virt && a === noS2xlate}).asUInt
763    val l2hhit = VecInit(l2h.flatMap(_.map{a => io.csr_dup(0).priv.virt && a === onlyStage1 || !io.csr_dup(0).priv.virt && a === noS2xlate})).asUInt
764    val sfence_vpn = sfence_dup(0).bits.addr(sfence_dup(0).bits.addr.getWidth-1, offLen)
765
766    when (sfence_dup(0).bits.rs1/*va*/) {
767      when (sfence_dup(0).bits.rs2) {
768        // all va && all asid
769        l2v := l2v & ~l2hhit
770        l1v := l1v & ~(l1hhit & VecInit(l1vmidhit.asBools.map{a => io.csr_dup(0).priv.virt && a || !io.csr_dup(0).priv.virt}).asUInt)
771        spv := spv & ~(sphhit & VecInit(spvmidhit.asBools.map{a => io.csr_dup(0).priv.virt && a || !io.csr_dup(0).priv.virt}).asUInt)
772      } .otherwise {
773        // all va && specific asid except global
774        l2v := l2v & (l2g | ~l2hhit)
775        l1v := l1v & ~(~l1g & l1hhit & l1asidhit & VecInit(l1vmidhit.asBools.map{a => io.csr_dup(0).priv.virt && a || !io.csr_dup(0).priv.virt}).asUInt)
776        spv := spv & ~(~spg & sphhit & spasidhit & VecInit(spvmidhit.asBools.map{a => io.csr_dup(0).priv.virt && a || !io.csr_dup(0).priv.virt}).asUInt)
777      }
778    } .otherwise {
779      when (sfence_dup(0).bits.rs2) {
780        // specific leaf of addr && all asid
781        spv := spv & ~(sphhit & VecInit(sp.map(_.hit(sfence_vpn, sfence_dup(0).bits.id, sfence_dup(0).bits.id, io.csr_dup(0).hgatp.asid, ignoreAsid = true, s2xlate = io.csr_dup(0).priv.virt))).asUInt)
782      } .otherwise {
783        // specific leaf of addr && specific asid
784        spv := spv & ~(~spg & sphhit & VecInit(sp.map(_.hit(sfence_vpn, sfence_dup(0).bits.id, sfence_dup(0).bits.id, io.csr_dup(0).hgatp.asid, s2xlate = io.csr_dup(0).priv.virt))).asUInt)
785      }
786    }
787  }
788
789  val hfencev_valid = sfence_dup(0).valid && sfence_dup(0).bits.hv
790  when (hfencev_valid) {
791    val l1vmidhit = VecInit(l1vmids.map(_.getOrElse(0.U) === io.csr_dup(0).hgatp.asid)).asUInt
792    val spvmidhit = VecInit(spvmids.map(_.getOrElse(0.U) === io.csr_dup(0).hgatp.asid)).asUInt
793    val l1hhit = VecInit(l1h.map(_ === onlyStage1)).asUInt
794    val sphhit = VecInit(sph.map(_ === onlyStage1)).asUInt
795    val l2hhit = VecInit(l2h.flatMap(_.map(_ === onlyStage1))).asUInt
796    val hfencev_vpn = sfence_dup(0).bits.addr(sfence_dup(0).bits.addr.getWidth-1, offLen)
797    when(sfence_dup(0).bits.rs1) {
798      when(sfence_dup(0).bits.rs2) {
799        l2v := l2v & ~l2hhit
800        l1v := l1v & ~(l1hhit & l1vmidhit)
801        spv := spv & ~(sphhit & spvmidhit)
802      }.otherwise {
803        l2v := l2v & (l2g | ~l2hhit)
804        l1v := l1v & ~(~l1g & l1hhit & l1asidhit & l1vmidhit)
805        spv := spv & ~(~spg & sphhit & spasidhit & spvmidhit)
806      }
807    }.otherwise {
808      when(sfence_dup(0).bits.rs2) {
809        spv := spv & ~(sphhit & VecInit(sp.map(_.hit(hfencev_vpn, sfence_dup(0).bits.id, sfence_dup(0).bits.id, io.csr_dup(0).hgatp.asid, ignoreAsid = true, s2xlate = true.B))).asUInt)
810      }.otherwise {
811        spv := spv & ~(~spg & sphhit & VecInit(sp.map(_.hit(hfencev_vpn, sfence_dup(0).bits.id, sfence_dup(0).bits.id, io.csr_dup(0).hgatp.asid, s2xlate = true.B))).asUInt)
812      }
813    }
814  }
815
816
817  val hfenceg_valid = sfence_dup(0).valid && sfence_dup(0).bits.hg
818  when(hfenceg_valid) {
819    val l1vmidhit = VecInit(l1vmids.map(_.getOrElse(0.U) === sfence_dup(0).bits.id)).asUInt
820    val spvmidhit = VecInit(spvmids.map(_.getOrElse(0.U) === sfence_dup(0).bits.id)).asUInt
821    val l1hhit = VecInit(l1h.map(_ === onlyStage2)).asUInt
822    val sphhit = VecInit(sph.map(_ === onlyStage2)).asUInt
823    val l2hhit = VecInit(l2h.flatMap(_.map(_ === onlyStage2))).asUInt
824    val hfenceg_gvpn = (sfence_dup(0).bits.addr << 2)(sfence_dup(0).bits.addr.getWidth - 1, offLen)
825    when(sfence_dup(0).bits.rs1) {
826      when(sfence_dup(0).bits.rs2) {
827        l2v := l2v & ~l2hhit
828        l1v := l1v & ~l1hhit
829        spv := spv & ~sphhit
830      }.otherwise {
831        l2v := l2v & ~l2hhit
832        l1v := l1v & ~(l1hhit & l1vmidhit)
833        spv := spv & ~(sphhit & spvmidhit)
834      }
835    }.otherwise {
836      when(sfence_dup(0).bits.rs2) {
837        spv := spv & ~(sphhit & VecInit(sp.map(_.hit(hfenceg_gvpn, 0.U, 0.U, sfence_dup(0).bits.id, ignoreAsid = true, s2xlate = false.B))).asUInt)
838      }.otherwise {
839        spv := spv & ~(~spg & sphhit & VecInit(sp.map(_.hit(hfenceg_gvpn, 0.U, 0.U, sfence_dup(0).bits.id, ignoreAsid = true, s2xlate = true.B))).asUInt)
840      }
841    }
842  }
843
844  def InsideStageConnect(in: DecoupledIO[PtwCacheReq], out: DecoupledIO[PtwCacheReq], inFire: Bool): Unit = {
845    in.ready := !in.valid || out.ready
846    out.valid := in.valid
847    out.bits := in.bits
848    out.bits.bypassed.zip(in.bits.bypassed).zipWithIndex.map{ case (b, i) =>
849      val bypassed_reg = Reg(Bool())
850      val bypassed_wire = refill_bypass(in.bits.req_info.vpn, i, in.bits.req_info.s2xlate) && io.refill.valid
851      when (inFire) { bypassed_reg := bypassed_wire }
852      .elsewhen (io.refill.valid) { bypassed_reg := bypassed_reg || bypassed_wire }
853
854      b._1 := b._2 || (bypassed_wire || (bypassed_reg && !inFire))
855    }
856  }
857
858  // Perf Count
859  val resp_l3 = resp_res.l3.hit
860  val resp_sp = resp_res.sp.hit
861  val resp_l1_pre = resp_res.l1.pre
862  val resp_l2_pre = resp_res.l2.pre
863  val resp_l3_pre = resp_res.l3.pre
864  val resp_sp_pre = resp_res.sp.pre
865  val base_valid_access_0 = !from_pre(io.resp.bits.req_info.source) && io.resp.fire
866  XSPerfAccumulate("access", base_valid_access_0)
867  XSPerfAccumulate("l1_hit", base_valid_access_0 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
868  XSPerfAccumulate("l2_hit", base_valid_access_0 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
869  XSPerfAccumulate("l3_hit", base_valid_access_0 && resp_l3)
870  XSPerfAccumulate("sp_hit", base_valid_access_0 && resp_sp)
871  XSPerfAccumulate("pte_hit",base_valid_access_0 && io.resp.bits.hit)
872
873  XSPerfAccumulate("l1_hit_pre", base_valid_access_0 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
874  XSPerfAccumulate("l2_hit_pre", base_valid_access_0 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
875  XSPerfAccumulate("l3_hit_pre", base_valid_access_0 && resp_l3_pre && resp_l3)
876  XSPerfAccumulate("sp_hit_pre", base_valid_access_0 && resp_sp_pre && resp_sp)
877  XSPerfAccumulate("pte_hit_pre",base_valid_access_0 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit)
878
879  val base_valid_access_1 = from_pre(io.resp.bits.req_info.source) && io.resp.fire
880  XSPerfAccumulate("pre_access", base_valid_access_1)
881  XSPerfAccumulate("pre_l1_hit", base_valid_access_1 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
882  XSPerfAccumulate("pre_l2_hit", base_valid_access_1 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
883  XSPerfAccumulate("pre_l3_hit", base_valid_access_1 && resp_l3)
884  XSPerfAccumulate("pre_sp_hit", base_valid_access_1 && resp_sp)
885  XSPerfAccumulate("pre_pte_hit",base_valid_access_1 && io.resp.bits.hit)
886
887  XSPerfAccumulate("pre_l1_hit_pre", base_valid_access_1 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
888  XSPerfAccumulate("pre_l2_hit_pre", base_valid_access_1 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
889  XSPerfAccumulate("pre_l3_hit_pre", base_valid_access_1 && resp_l3_pre && resp_l3)
890  XSPerfAccumulate("pre_sp_hit_pre", base_valid_access_1 && resp_sp_pre && resp_sp)
891  XSPerfAccumulate("pre_pte_hit_pre",base_valid_access_1 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit)
892
893  val base_valid_access_2 = stageResp.bits.isFirst && !from_pre(io.resp.bits.req_info.source) && io.resp.fire
894  XSPerfAccumulate("access_first", base_valid_access_2)
895  XSPerfAccumulate("l1_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
896  XSPerfAccumulate("l2_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
897  XSPerfAccumulate("l3_hit_first", base_valid_access_2 && resp_l3)
898  XSPerfAccumulate("sp_hit_first", base_valid_access_2 && resp_sp)
899  XSPerfAccumulate("pte_hit_first",base_valid_access_2 && io.resp.bits.hit)
900
901  XSPerfAccumulate("l1_hit_pre_first", base_valid_access_2 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
902  XSPerfAccumulate("l2_hit_pre_first", base_valid_access_2 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
903  XSPerfAccumulate("l3_hit_pre_first", base_valid_access_2 && resp_l3_pre && resp_l3)
904  XSPerfAccumulate("sp_hit_pre_first", base_valid_access_2 && resp_sp_pre && resp_sp)
905  XSPerfAccumulate("pte_hit_pre_first",base_valid_access_2 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit)
906
907  val base_valid_access_3 = stageResp.bits.isFirst && from_pre(io.resp.bits.req_info.source) && io.resp.fire
908  XSPerfAccumulate("pre_access_first", base_valid_access_3)
909  XSPerfAccumulate("pre_l1_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
910  XSPerfAccumulate("pre_l2_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
911  XSPerfAccumulate("pre_l3_hit_first", base_valid_access_3 && resp_l3)
912  XSPerfAccumulate("pre_sp_hit_first", base_valid_access_3 && resp_sp)
913  XSPerfAccumulate("pre_pte_hit_first", base_valid_access_3 && io.resp.bits.hit)
914
915  XSPerfAccumulate("pre_l1_hit_pre_first", base_valid_access_3 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
916  XSPerfAccumulate("pre_l2_hit_pre_first", base_valid_access_3 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit)
917  XSPerfAccumulate("pre_l3_hit_pre_first", base_valid_access_3 && resp_l3_pre && resp_l3)
918  XSPerfAccumulate("pre_sp_hit_pre_first", base_valid_access_3 && resp_sp_pre && resp_sp)
919  XSPerfAccumulate("pre_pte_hit_pre_first",base_valid_access_3 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit)
920
921  XSPerfAccumulate("rwHarzad", io.req.valid && !io.req.ready)
922  XSPerfAccumulate("out_blocked", io.resp.valid && !io.resp.ready)
923  l1AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L1AccessIndex${i}", l) }
924  l2AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L2AccessIndex${i}", l) }
925  l3AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L3AccessIndex${i}", l) }
926  spAccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPAccessIndex${i}", l) }
927  l1RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L1RefillIndex${i}", l) }
928  l2RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L2RefillIndex${i}", l) }
929  l3RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L3RefillIndex${i}", l) }
930  spRefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPRefillIndex${i}", l) }
931
932  XSPerfAccumulate("l1Refill", Cat(l1RefillPerf).orR)
933  XSPerfAccumulate("l2Refill", Cat(l2RefillPerf).orR)
934  XSPerfAccumulate("l3Refill", Cat(l3RefillPerf).orR)
935  XSPerfAccumulate("spRefill", Cat(spRefillPerf).orR)
936  XSPerfAccumulate("l1Refill_pre", Cat(l1RefillPerf).orR && refill_prefetch_dup(0))
937  XSPerfAccumulate("l2Refill_pre", Cat(l2RefillPerf).orR && refill_prefetch_dup(0))
938  XSPerfAccumulate("l3Refill_pre", Cat(l3RefillPerf).orR && refill_prefetch_dup(0))
939  XSPerfAccumulate("spRefill_pre", Cat(spRefillPerf).orR && refill_prefetch_dup(0))
940
941  // debug
942  XSDebug(sfence_dup(0).valid, p"[sfence] original v and g vector:\n")
943  XSDebug(sfence_dup(0).valid, p"[sfence] l1v:${Binary(l1v)}\n")
944  XSDebug(sfence_dup(0).valid, p"[sfence] l2v:${Binary(l2v)}\n")
945  XSDebug(sfence_dup(0).valid, p"[sfence] l3v:${Binary(l3v)}\n")
946  XSDebug(sfence_dup(0).valid, p"[sfence] l3g:${Binary(l3g)}\n")
947  XSDebug(sfence_dup(0).valid, p"[sfence] spv:${Binary(spv)}\n")
948  XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] new v and g vector:\n")
949  XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l1v:${Binary(l1v)}\n")
950  XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l2v:${Binary(l2v)}\n")
951  XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l3v:${Binary(l3v)}\n")
952  XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] l3g:${Binary(l3g)}\n")
953  XSDebug(RegNext(sfence_dup(0).valid), p"[sfence] spv:${Binary(spv)}\n")
954
955  val perfEvents = Seq(
956    ("access           ", base_valid_access_0             ),
957    ("l1_hit           ", l1Hit                           ),
958    ("l2_hit           ", l2Hit                           ),
959    ("l3_hit           ", l3Hit                           ),
960    ("sp_hit           ", spHit                           ),
961    ("pte_hit          ", l3Hit || spHit                  ),
962    ("rwHarzad         ",  io.req.valid && !io.req.ready  ),
963    ("out_blocked      ",  io.resp.valid && !io.resp.ready),
964  )
965  generatePerfEvent()
966}
967