1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 26import freechips.rocketchip.tilelink._ 27 28 29case class TLBParameters 30( 31 name: String = "none", 32 fetchi: Boolean = false, // TODO: remove it 33 fenceDelay: Int = 2, 34 useDmode: Boolean = true, 35 normalNSets: Int = 1, // when da or sa 36 normalNWays: Int = 8, // when fa or sa 37 superNSets: Int = 1, 38 superNWays: Int = 2, 39 normalReplacer: Option[String] = Some("random"), 40 superReplacer: Option[String] = Some("plru"), 41 normalAssociative: String = "fa", // "fa", "sa", "da", "sa" is not supported 42 superAssociative: String = "fa", // must be fa 43 normalAsVictim: Boolean = false, // when get replace from fa, store it into sram 44 outReplace: Boolean = false, 45 partialStaticPMP: Boolean = false, // partial static pmp result stored in entries 46 outsideRecvFlush: Boolean = false, // if outside moudle waiting for tlb recv flush pipe 47 saveLevel: Boolean = false 48) 49 50case class L2TLBParameters 51( 52 name: String = "l2tlb", 53 // l1 54 l1Size: Int = 16, 55 l1Associative: String = "fa", 56 l1Replacer: Option[String] = Some("plru"), 57 // l2 58 l2nSets: Int = 32, 59 l2nWays: Int = 2, 60 l2Replacer: Option[String] = Some("setplru"), 61 // l3 62 l3nSets: Int = 128, 63 l3nWays: Int = 4, 64 l3Replacer: Option[String] = Some("setplru"), 65 // sp 66 spSize: Int = 16, 67 spReplacer: Option[String] = Some("plru"), 68 // filter 69 ifilterSize: Int = 4, 70 dfilterSize: Int = 8, 71 // miss queue, add more entries than 'must require' 72 // 0 for easier bug trigger, please set as big as u can, 8 maybe 73 missqueueExtendSize: Int = 0, 74 // llptw 75 llptwsize: Int = 6, 76 // way size 77 blockBytes: Int = 64, 78 // prefetch 79 enablePrefetch: Boolean = true, 80 // ecc 81 ecc: Option[String] = Some("secded") 82) 83 84trait HasTlbConst extends HasXSParameter { 85 val Level = 3 86 87 val offLen = 12 88 val ppnLen = PAddrBits - offLen 89 val vpnnLen = 9 90 val vpnLen = VAddrBits - offLen 91 val flagLen = 8 92 val pteResLen = XLEN - ppnLen - 2 - flagLen 93 94 val sramSinglePort = true 95 96 val timeOutThreshold = 10000 97 98 def get_pn(addr: UInt) = { 99 require(addr.getWidth > offLen) 100 addr(addr.getWidth-1, offLen) 101 } 102 def get_off(addr: UInt) = { 103 require(addr.getWidth > offLen) 104 addr(offLen-1, 0) 105 } 106 107 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 108 require(nSets >= 1) 109 vpn(log2Up(nSets)-1, 0) 110 } 111 112 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 113 require(nSets >= 1) 114 require(vpn.getWidth > log2Ceil(nSets)) 115 vpn(vpn.getWidth-1, log2Ceil(nSets)) 116 } 117 118 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 119 require(nSets >= 1) 120 require(vpn1.getWidth == vpn2.getWidth) 121 if (vpn1.getWidth <= log2Ceil(nSets)) { 122 true.B 123 } else { 124 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 125 } 126 } 127 128 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 129 val width = v.getWidth 130 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U))) 131 val full = Cat(v).andR 132 Mux(full, lruIdx, emptyIdx) 133 } 134 135 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 136 replaceWrapper(VecInit(v).asUInt, lruIdx) 137 } 138 139 implicit def ptwresp_to_tlbprem(ptwResp: PtwResp): TlbPermBundle = { 140 val tp = Wire(new TlbPermBundle) 141 val ptePerm = ptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 142 tp.pf := ptwResp.pf 143 tp.af := ptwResp.af 144 tp.d := ptePerm.d 145 tp.a := ptePerm.a 146 tp.g := ptePerm.g 147 tp.u := ptePerm.u 148 tp.x := ptePerm.x 149 tp.w := ptePerm.w 150 tp.r := ptePerm.r 151 tp.pm := DontCare 152 tp 153 } 154} 155 156trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 157 val PtwWidth = 2 158 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 159 val prefetchID = PtwWidth 160 161 val blockBits = l2tlbParams.blockBytes * 8 162 163 val bPtwWidth = log2Up(PtwWidth) 164 val bSourceWidth = log2Up(sourceWidth) 165 // ptwl1: fully-associated 166 val PtwL1TagLen = vpnnLen 167 168 /* +-------+----------+-------------+ 169 * | Tag | SetIdx | SectorIdx | 170 * +-------+----------+-------------+ 171 */ 172 // ptwl2: 8-way group-associated 173 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 174 val PtwL2SetNum = l2tlbParams.l2nSets 175 val PtwL2SectorSize = blockBits /XLEN 176 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 177 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 178 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 179 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen 180 181 // ptwl3: 16-way group-associated 182 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 183 val PtwL3SetNum = l2tlbParams.l3nSets 184 val PtwL3SectorSize = blockBits / XLEN 185 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 186 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 187 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 188 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen 189 190 // super page, including 1GB and 2MB page 191 val SPTagLen = vpnnLen * 2 192 193 // miss queue 194 val MissQueueSize = l2tlbParams.ifilterSize + l2tlbParams.dfilterSize 195 val MemReqWidth = l2tlbParams.llptwsize + 1 196 val FsmReqID = l2tlbParams.llptwsize 197 val bMemID = log2Up(MemReqWidth) 198 199 def genPtwL2Idx(vpn: UInt) = { 200 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 201 } 202 203 def genPtwL2SectorIdx(vpn: UInt) = { 204 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 205 } 206 207 def genPtwL2SetIdx(vpn: UInt) = { 208 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 209 } 210 211 def genPtwL3Idx(vpn: UInt) = { 212 vpn(PtwL3IdxLen - 1, 0) 213 } 214 215 def genPtwL3SectorIdx(vpn: UInt) = { 216 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 217 } 218 219 def dropL3SectorBits(vpn: UInt) = { 220 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 221 } 222 223 def genPtwL3SetIdx(vpn: UInt) = { 224 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 225 } 226 227 def MakeAddr(ppn: UInt, off: UInt) = { 228 require(off.getWidth == 9) 229 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 230 } 231 232 def getVpnn(vpn: UInt, idx: Int): UInt = { 233 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 234 } 235 236 def getVpnClip(vpn: UInt, level: Int) = { 237 // level 0 /* vpnn2 */ 238 // level 1 /* vpnn2 * vpnn1 */ 239 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 240 vpn(vpnLen - 1, (2 - level) * vpnnLen) 241 } 242 243 def get_next_line(vpn: UInt) = { 244 Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W)) 245 } 246 247 def same_l2entry(vpn1: UInt, vpn2: UInt) = { 248 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 249 } 250 251 def from_pre(source: UInt) = { 252 (source === prefetchID.U) 253 } 254 255 def printVec[T <: Data](x: Seq[T]): Printable = { 256 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 257 } 258} 259