1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 26import freechips.rocketchip.tilelink._ 27 28case class TLBParameters 29( 30 name: String = "none", 31 fetchi: Boolean = false, // TODO: remove it 32 useDmode: Boolean = true, 33 sameCycle: Boolean = false, 34 missSameCycle: Boolean = false, 35 normalNSets: Int = 1, // when da or sa 36 normalNWays: Int = 8, // when fa or sa 37 superNSets: Int = 1, 38 superNWays: Int = 2, 39 normalReplacer: Option[String] = Some("random"), 40 superReplacer: Option[String] = Some("plru"), 41 normalAssociative: String = "fa", // "fa", "sa", "da", "sa" is not supported 42 superAssociative: String = "fa", // must be fa 43 normalAsVictim: Boolean = false, // when get replace from fa, store it into sram 44 outReplace: Boolean = false, 45 shouldBlock: Boolean = false // only for perf, not support for io 46) 47 48case class L2TLBParameters 49( 50 name: String = "l2tlb", 51 // l1 52 l1Size: Int = 16, 53 l1Associative: String = "fa", 54 l1Replacer: Option[String] = Some("plru"), 55 // l2 56 l2nSets: Int = 32, 57 l2nWays: Int = 2, 58 l2Replacer: Option[String] = Some("setplru"), 59 // l3 60 l3nSets: Int = 128, 61 l3nWays: Int = 4, 62 l3Replacer: Option[String] = Some("setplru"), 63 // sp 64 spSize: Int = 16, 65 spReplacer: Option[String] = Some("plru"), 66 // dtlb filter 67 filterSize: Int = 8, 68 // miss queue, add more entries than 'must require' 69 // 0 for easier bug trigger, please set as big as u can, 8 maybe 70 missqueueExtendSize: Int = 0, 71 // way size 72 blockBytes: Int = 64, 73 // prefetch 74 enablePrefetch: Boolean = true, 75 // ecc 76 ecc: Option[String] = Some("secded") 77) 78 79trait HasTlbConst extends HasXSParameter { 80 val Level = 3 81 82 val offLen = 12 83 val ppnLen = PAddrBits - offLen 84 val vpnnLen = 9 85 val vpnLen = VAddrBits - offLen 86 val flagLen = 8 87 val pteResLen = XLEN - ppnLen - 2 - flagLen 88 89 val sramSinglePort = true 90 91 val timeOutThreshold = 5000 92 93 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 94 require(nSets >= 1) 95 vpn(log2Up(nSets)-1, 0) 96 } 97 98 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 99 require(nSets >= 1) 100 require(vpn.getWidth > log2Ceil(nSets)) 101 vpn(vpn.getWidth-1, log2Ceil(nSets)) 102 } 103 104 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 105 require(nSets >= 1) 106 require(vpn1.getWidth == vpn2.getWidth) 107 if (vpn1.getWidth <= log2Ceil(nSets)) { 108 true.B 109 } else { 110 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 111 } 112 } 113 114 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 115 val width = v.getWidth 116 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U))) 117 val full = Cat(v).andR 118 Mux(full, lruIdx, emptyIdx) 119 } 120 121 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 122 replaceWrapper(VecInit(v).asUInt, lruIdx) 123 } 124 125} 126 127trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 128 val PtwWidth = 2 129 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 130 val prefetchID = PtwWidth 131 val maxPrefetchNum = l2tlbParams.filterSize 132 133 val blockBits = l2tlbParams.blockBytes * 8 134 135 val bPtwWidth = log2Up(PtwWidth) 136 val bSourceWidth = log2Up(sourceWidth) 137 // ptwl1: fully-associated 138 val PtwL1TagLen = vpnnLen 139 140 /* +-------+----------+-------------+ 141 * | Tag | SetIdx | SectorIdx | 142 * +-------+----------+-------------+ 143 */ 144 // ptwl2: 8-way group-associated 145 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 146 val PtwL2SetNum = l2tlbParams.l2nSets 147 val PtwL2SectorSize = blockBits /XLEN 148 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 149 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 150 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 151 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen 152 153 // ptwl3: 16-way group-associated 154 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 155 val PtwL3SetNum = l2tlbParams.l3nSets 156 val PtwL3SectorSize = blockBits / XLEN 157 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 158 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 159 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 160 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen 161 162 // super page, including 1GB and 2MB page 163 val SPTagLen = vpnnLen * 2 164 165 // miss queue 166 val MSHRBaseSize = 1 + l2tlbParams.filterSize + l2tlbParams.missqueueExtendSize 167 val MSHRSize = { if (l2tlbParams.enablePrefetch) (MSHRBaseSize + 1) else MSHRBaseSize } 168 val MemReqWidth = MSHRSize + 1 169 val FsmReqID = MSHRSize 170 val bMemID = log2Up(MSHRSize + 1) 171 172 def genPtwL2Idx(vpn: UInt) = { 173 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 174 } 175 176 def genPtwL2SectorIdx(vpn: UInt) = { 177 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 178 } 179 180 def genPtwL2SetIdx(vpn: UInt) = { 181 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 182 } 183 184 def genPtwL3Idx(vpn: UInt) = { 185 vpn(PtwL3IdxLen - 1, 0) 186 } 187 188 def genPtwL3SectorIdx(vpn: UInt) = { 189 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 190 } 191 192 def dropL3SectorBits(vpn: UInt) = { 193 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 194 } 195 196 def genPtwL3SetIdx(vpn: UInt) = { 197 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 198 } 199 200 def MakeAddr(ppn: UInt, off: UInt) = { 201 require(off.getWidth == 9) 202 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 203 } 204 205 def getVpnn(vpn: UInt, idx: Int): UInt = { 206 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 207 } 208 209 def getVpnClip(vpn: UInt, level: Int) = { 210 // level 0 /* vpnn2 */ 211 // level 1 /* vpnn2 * vpnn1 */ 212 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 213 vpn(vpnLen - 1, (2 - level) * vpnnLen) 214 } 215 216 def get_next_line(vpn: UInt) = { 217 Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W)) 218 } 219 220 def same_l2entry(vpn1: UInt, vpn2: UInt) = { 221 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 222 } 223 224 def from_pre(source: UInt) = { 225 (source === prefetchID.U) 226 } 227 228 def printVec[T <: Data](x: Seq[T]): Printable = { 229 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 230 } 231} 232