xref: /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala (revision e9092fe204a3f857582a32c9b027543ad538d964)
16d5ddbceSLemover/***************************************************************************************
26d5ddbceSLemover* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3f320e0f0SYinan Xu* Copyright (c) 2020-2021 Peng Cheng Laboratory
46d5ddbceSLemover*
56d5ddbceSLemover* XiangShan is licensed under Mulan PSL v2.
66d5ddbceSLemover* You can use this software according to the terms and conditions of the Mulan PSL v2.
76d5ddbceSLemover* You may obtain a copy of Mulan PSL v2 at:
86d5ddbceSLemover*          http://license.coscl.org.cn/MulanPSL2
96d5ddbceSLemover*
106d5ddbceSLemover* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
116d5ddbceSLemover* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
126d5ddbceSLemover* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
136d5ddbceSLemover*
146d5ddbceSLemover* See the Mulan PSL v2 for more details.
156d5ddbceSLemover***************************************************************************************/
166d5ddbceSLemover
176d5ddbceSLemoverpackage xiangshan.cache.mmu
186d5ddbceSLemover
196d5ddbceSLemoverimport chipsalliance.rocketchip.config.Parameters
206d5ddbceSLemoverimport chisel3._
216d5ddbceSLemoverimport chisel3.util._
226d5ddbceSLemoverimport xiangshan._
236d5ddbceSLemoverimport xiangshan.cache.{HasDCacheParameters, MemoryOpConstants}
246d5ddbceSLemoverimport utils._
256d5ddbceSLemoverimport freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
266d5ddbceSLemoverimport freechips.rocketchip.tilelink._
276d5ddbceSLemover
28a0301c0dSLemovercase class TLBParameters
29a0301c0dSLemover(
30a0301c0dSLemover  name: String = "none",
31a0301c0dSLemover  fetchi: Boolean = false, // TODO: remove it
32a0301c0dSLemover  useDmode: Boolean = true,
33a0301c0dSLemover  sameCycle: Boolean = false,
34fb90f54dSLemover  missSameCycle: Boolean = false,
35a0301c0dSLemover  normalNSets: Int = 1, // when da or sa
36a0301c0dSLemover  normalNWays: Int = 8, // when fa or sa
37a0301c0dSLemover  superNSets: Int = 1,
38a0301c0dSLemover  superNWays: Int = 2,
39a0301c0dSLemover  normalReplacer: Option[String] = Some("random"),
40a0301c0dSLemover  superReplacer: Option[String] = Some("plru"),
41a0301c0dSLemover  normalAssociative: String = "fa", // "fa", "sa", "da", "sa" is not supported
42a0301c0dSLemover  superAssociative: String = "fa", // must be fa
43a0301c0dSLemover  normalAsVictim: Boolean = false, // when get replace from fa, store it into sram
44a0301c0dSLemover  outReplace: Boolean = false,
45a0301c0dSLemover  shouldBlock: Boolean = false // only for perf, not support for io
46a0301c0dSLemover)
47a0301c0dSLemover
485854c1edSLemovercase class L2TLBParameters
495854c1edSLemover(
505854c1edSLemover  name: String = "l2tlb",
515854c1edSLemover  // l1
525854c1edSLemover  l1Size: Int = 16,
535854c1edSLemover  l1Associative: String = "fa",
545854c1edSLemover  l1Replacer: Option[String] = Some("plru"),
555854c1edSLemover  // l2
56ecf1a4b8SLemover  l2nSets: Int = 32,
57ecf1a4b8SLemover  l2nWays: Int = 2,
585854c1edSLemover  l2Replacer: Option[String] = Some("setplru"),
595854c1edSLemover  // l3
60fa086d5eSLemover  l3nSets: Int = 128,
61fa086d5eSLemover  l3nWays: Int = 4,
625854c1edSLemover  l3Replacer: Option[String] = Some("setplru"),
635854c1edSLemover  // sp
645854c1edSLemover  spSize: Int = 16,
655854c1edSLemover  spReplacer: Option[String] = Some("plru"),
66bc063562SLemover  // dtlb filter
67bc063562SLemover  filterSize: Int = 8,
68d74a7bd3SLemover  // miss queue, add more entries than 'must require'
69d74a7bd3SLemover  // 0 for easier bug trigger, please set as big as u can, 8 maybe
70d74a7bd3SLemover  missqueueExtendSize: Int = 0,
715854c1edSLemover  // way size
727196f5a2SLemover  blockBytes: Int = 64,
73bc063562SLemover  // prefetch
74bc063562SLemover  enablePrefetch: Boolean = true,
757196f5a2SLemover  // ecc
767196f5a2SLemover  ecc: Option[String] = Some("secded")
775854c1edSLemover)
785854c1edSLemover
796d5ddbceSLemovertrait HasTlbConst extends HasXSParameter {
806d5ddbceSLemover  val Level = 3
816d5ddbceSLemover
826d5ddbceSLemover  val offLen  = 12
836d5ddbceSLemover  val ppnLen  = PAddrBits - offLen
846d5ddbceSLemover  val vpnnLen = 9
856d5ddbceSLemover  val vpnLen  = VAddrBits - offLen
866d5ddbceSLemover  val flagLen = 8
876d5ddbceSLemover  val pteResLen = XLEN - ppnLen - 2 - flagLen
886d5ddbceSLemover
89a0301c0dSLemover  val sramSinglePort = true
90a0301c0dSLemover
91a79fef67Swakafa  val timeOutThreshold = 5000
929bd9cdfaSLemover
933889e11eSLemover  def get_set_idx(vpn: UInt, nSets: Int): UInt = {
94*e9092fe2SLemover    require(nSets >= 1)
95a0301c0dSLemover    vpn(log2Up(nSets)-1, 0)
966d5ddbceSLemover  }
976d5ddbceSLemover
98*e9092fe2SLemover  def drop_set_idx(vpn: UInt, nSets: Int): UInt = {
99*e9092fe2SLemover    require(nSets >= 1)
100*e9092fe2SLemover    require(vpn.getWidth > log2Ceil(nSets))
101*e9092fe2SLemover    vpn(vpn.getWidth-1, log2Ceil(nSets))
102*e9092fe2SLemover  }
103*e9092fe2SLemover
104*e9092fe2SLemover  def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = {
105*e9092fe2SLemover    require(nSets >= 1)
106*e9092fe2SLemover    require(vpn1.getWidth == vpn2.getWidth)
107*e9092fe2SLemover    if (vpn1.getWidth <= log2Ceil(nSets)) {
108*e9092fe2SLemover      true.B
109*e9092fe2SLemover    } else {
110*e9092fe2SLemover      drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets)
111*e9092fe2SLemover    }
112*e9092fe2SLemover  }
113*e9092fe2SLemover
1146d5ddbceSLemover  def replaceWrapper(v: UInt, lruIdx: UInt): UInt = {
1156d5ddbceSLemover    val width = v.getWidth
1166d5ddbceSLemover    val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U)))
1176d5ddbceSLemover    val full = Cat(v).andR
1186d5ddbceSLemover    Mux(full, lruIdx, emptyIdx)
1196d5ddbceSLemover  }
1206d5ddbceSLemover
1216d5ddbceSLemover  def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = {
1226d5ddbceSLemover    replaceWrapper(VecInit(v).asUInt, lruIdx)
1236d5ddbceSLemover  }
124a0301c0dSLemover
1256d5ddbceSLemover}
1266d5ddbceSLemover
1276d5ddbceSLemovertrait HasPtwConst extends HasTlbConst with MemoryOpConstants{
1286d5ddbceSLemover  val PtwWidth = 2
129bc063562SLemover  val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth}
130bc063562SLemover  val prefetchID = PtwWidth
131bc063562SLemover  val maxPrefetchNum = l2tlbParams.filterSize
132bc063562SLemover
1335854c1edSLemover  val blockBits = l2tlbParams.blockBytes * 8
1346d5ddbceSLemover
1356d5ddbceSLemover  val bPtwWidth = log2Up(PtwWidth)
136bc063562SLemover  val bSourceWidth = log2Up(sourceWidth)
1376d5ddbceSLemover  // ptwl1: fully-associated
1386d5ddbceSLemover  val PtwL1TagLen = vpnnLen
1396d5ddbceSLemover
1406d5ddbceSLemover  /* +-------+----------+-------------+
1416d5ddbceSLemover   * |  Tag  |  SetIdx  |  SectorIdx  |
1426d5ddbceSLemover   * +-------+----------+-------------+
1436d5ddbceSLemover   */
1446d5ddbceSLemover  // ptwl2: 8-way group-associated
1455854c1edSLemover  val l2tlbParams.l2nWays = l2tlbParams.l2nWays
1465854c1edSLemover  val PtwL2SetNum = l2tlbParams.l2nSets
1475854c1edSLemover  val PtwL2SectorSize = blockBits /XLEN
1485854c1edSLemover  val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize)
1496d5ddbceSLemover  val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize)
1505854c1edSLemover  val PtwL2SetIdxLen = log2Up(PtwL2SetNum)
1516d5ddbceSLemover  val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen
1526d5ddbceSLemover
1536d5ddbceSLemover  // ptwl3: 16-way group-associated
1545854c1edSLemover  val l2tlbParams.l3nWays = l2tlbParams.l3nWays
1555854c1edSLemover  val PtwL3SetNum = l2tlbParams.l3nSets
1565854c1edSLemover  val PtwL3SectorSize =  blockBits / XLEN
1575854c1edSLemover  val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize)
1586d5ddbceSLemover  val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize)
1595854c1edSLemover  val PtwL3SetIdxLen = log2Up(PtwL3SetNum)
1606d5ddbceSLemover  val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen
1616d5ddbceSLemover
1626d5ddbceSLemover  // super page, including 1GB and 2MB page
1636d5ddbceSLemover  val SPTagLen = vpnnLen * 2
1646d5ddbceSLemover
165d74a7bd3SLemover  // miss queue
166d74a7bd3SLemover  val MSHRBaseSize = 1 + l2tlbParams.filterSize + l2tlbParams.missqueueExtendSize
167d74a7bd3SLemover  val MSHRSize =  { if (l2tlbParams.enablePrefetch) (MSHRBaseSize + 1) else MSHRBaseSize }
168b848eea5SLemover  val MemReqWidth = MSHRSize + 1
169bc063562SLemover  val FsmReqID = MSHRSize
170b848eea5SLemover  val bMemID = log2Up(MSHRSize + 1)
1716d5ddbceSLemover
1726d5ddbceSLemover  def genPtwL2Idx(vpn: UInt) = {
1736d5ddbceSLemover    (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0)
1746d5ddbceSLemover  }
1756d5ddbceSLemover
1766d5ddbceSLemover  def genPtwL2SectorIdx(vpn: UInt) = {
1776d5ddbceSLemover    genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0)
1786d5ddbceSLemover  }
1796d5ddbceSLemover
1806d5ddbceSLemover  def genPtwL2SetIdx(vpn: UInt) = {
1816d5ddbceSLemover    genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen)
1826d5ddbceSLemover  }
1836d5ddbceSLemover
1846d5ddbceSLemover  def genPtwL3Idx(vpn: UInt) = {
1856d5ddbceSLemover    vpn(PtwL3IdxLen - 1, 0)
1866d5ddbceSLemover  }
1876d5ddbceSLemover
1886d5ddbceSLemover  def genPtwL3SectorIdx(vpn: UInt) = {
1896d5ddbceSLemover    genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0)
1906d5ddbceSLemover  }
1916d5ddbceSLemover
192cc5a5f22SLemover  def dropL3SectorBits(vpn: UInt) = {
193cc5a5f22SLemover    vpn(vpn.getWidth-1, PtwL3SectorIdxLen)
194cc5a5f22SLemover  }
195cc5a5f22SLemover
1966d5ddbceSLemover  def genPtwL3SetIdx(vpn: UInt) = {
1976d5ddbceSLemover    genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen)
1986d5ddbceSLemover  }
1996d5ddbceSLemover
2006d5ddbceSLemover  def MakeAddr(ppn: UInt, off: UInt) = {
2016d5ddbceSLemover    require(off.getWidth == 9)
2026d5ddbceSLemover    Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0)
2036d5ddbceSLemover  }
2046d5ddbceSLemover
205b848eea5SLemover  def getVpnn(vpn: UInt, idx: Int): UInt = {
2066d5ddbceSLemover    vpn(vpnnLen*(idx+1)-1, vpnnLen*idx)
2076d5ddbceSLemover  }
2086d5ddbceSLemover
2096d5ddbceSLemover  def getVpnClip(vpn: UInt, level: Int) = {
2106d5ddbceSLemover    // level 0  /* vpnn2 */
2116d5ddbceSLemover    // level 1  /* vpnn2 * vpnn1 */
2126d5ddbceSLemover    // level 2  /* vpnn2 * vpnn1 * vpnn0*/
2136d5ddbceSLemover    vpn(vpnLen - 1, (2 - level) * vpnnLen)
2146d5ddbceSLemover  }
2156d5ddbceSLemover
216bc063562SLemover  def get_next_line(vpn: UInt) = {
217bc063562SLemover    Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W))
218bc063562SLemover  }
219bc063562SLemover
220bc063562SLemover  def same_l2entry(vpn1: UInt, vpn2: UInt) = {
221bc063562SLemover    vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen)
222bc063562SLemover  }
223bc063562SLemover
224bc063562SLemover  def from_pre(source: UInt) = {
225bc063562SLemover    (source === prefetchID.U)
226bc063562SLemover  }
227bc063562SLemover
2286d5ddbceSLemover  def printVec[T <: Data](x: Seq[T]): Printable = {
2296d5ddbceSLemover    (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_)
2306d5ddbceSLemover  }
2316d5ddbceSLemover}
232