1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16package xiangshan.cache.mmu 17 18import chisel3._ 19import chisel3.util._ 20import chipsalliance.rocketchip.config.Parameters 21import xiangshan.{SfenceBundle, XSModule} 22import utils._ 23 24class L2TlbPrefetchIO(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 25 val in = Flipped(ValidIO(new Bundle { 26 val vpn = UInt(vpnLen.W) 27 })) 28 val out = DecoupledIO(new Bundle { 29 val vpn = UInt(vpnLen.W) 30 val source = UInt(bSourceWidth.W) 31 }) 32} 33 34class L2TlbPrefetch(implicit p: Parameters) extends XSModule with HasPtwConst { 35 val io = IO(new L2TlbPrefetchIO()) 36 37 val flush = io.sfence.valid || io.csr.satp.changed 38 val next_line = RegEnable(get_next_line(io.in.bits.vpn), io.in.valid) 39 val v = ValidHold(io.in.valid && !flush, io.out.fire(), flush) 40 41 io.out.valid := v 42 io.out.bits.vpn := next_line 43 io.out.bits.source := prefetchID.U 44} 45