fix(L2TlbPrefetch): fix flush condition of L2 TLB Prefetch (#4541)

All components within the L2 TLB should use the same flush condition to
avoid potential issues.

RVH: fix some bugs about missqueue after llptw was connected to missqueue

RVH: add the way from llptw to missqueue if llptw is full

RVH_L2TLB: connect hptw to missqueue to deal with hptw bypass

RVH: fix some bugs in compilation

RVH: finish the desigh of H extention

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

MMU: Add ChiselDB and Fake PTW (#1858)

* L2TLB: Fix a bug of Prefetcher

* MMU: Add ChiselDB

* MMU: Add Fake PTW

* MMU: Fix ChiselDB for dual core

l2tlb: add dup register & add blockhelper & llptw mem resp select timing optimization (#1752)

This commit includes:
1. timimg optimization: add dup register and optimize llptw mem resp select relat

l2tlb: add dup register & add blockhelper & llptw mem resp select timing optimization (#1752)

This commit includes:
1. timimg optimization: add dup register and optimize llptw mem resp select relative logic
2. l2tlb more fifo: add a blockhelper to help l2tlb behave more like a fifo to l1tlb. And fix some cases that cause page cache s has dupliacate entries (not cover all cases).

* l2tlb: add duplicate reg for better fanout (#1725)

page cache has large fanout:
1. addr_low -> sel data
2. level
3. sfence
4. ecc error flush

solution, add duplicate reg:
1. sfence/csr reg
2. ecc error reg
3. memSelData
4. one hot level code

* l2tlb: fix bug that wrongle chosen req info from llptw

* l2tlb.cache: move hitCheck into StageDelay

* l2tlb: optimize mem resp data selection to ptw

* l2tlb.llptw: optimize timing for pmp check of llptw

* l2tlb.cache: move v-bits select into stageReq

* l2tlb.llptw: req that miss mem should re-access cache

* l2tlb.llptw: fix bug that mix mem_ptr and cache_ptr

* l2tlb.llptw: fix bug that lost a case for merge

* l2tlb.llptw: fix bug of state change priority

* l2tlb.prefetch: add filter buffer and perf counter

* mmu: change TimeOutThreshold to 3000

* l2tlb: ptw has highest priority to enq llptw

* l2tlb.cache: fix bug of bypassed logic

* l2tlb.llptw: fix bug that flush failed to flush pmp check

* l2tlb: add blockhelper to make l2tlb more fifo

* mmu: change TimeOutThreshold to 5000

* l2tlb: new l1tlb doesn't enter ptw directly

a corner case complement to:
commit(3158ab8): "l2tlb: add blockhelper to make l2tlb more fifo"

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asid: add asid, mainly work when hit check, not in sfence.vma (#1090)

add mmu's asid support.
1. put asid inside sram (if the entry is sram), or it will take too many sources.
2. when sfence, just

asid: add asid, mainly work when hit check, not in sfence.vma (#1090)

add mmu's asid support.
1. put asid inside sram (if the entry is sram), or it will take too many sources.
2. when sfence, just flush it all, don't care asid.
3. when hit check, check asid.
4. when asid changed, flush all the inflight ptw req for safety
5. simple asid unit test:
asid 1 write, asid 2 read and check, asid 2 write, asid 1 read and check. same va, different pa

* ASID: make satp's asid bits configurable to RW
* use AsidLength to control it

* ASID: implement asid refilling and hit checking
* TODO: sfence flush with asid

* ASID: implement sfence with asid
* TODO: extract asid from SRAMTemplate

* ASID: extract asid from SRAMTemplate
* all is down
* TODO: test

* fix write to asid

* Sfence: support rs2 of sfence and fix Fence Unit
* rs2 of Sfence should be Reg and pass it to Fence Unit
* judge the value of reg instead of the index in Fence Unit

* mmu: re-write asid

now, asid is stored inside sram, so sfence just flush it
it's a complex job to handle the problem that asid is changed but
no sfence.vma is executed. when asid is changed, all the inflight
mmu reqs are flushed but entries in storage is not influenced.
so the inflight reqs do not need to record asid, just use satp.asid

* tlb: fix bug of refill mask

* ci: add asid unit test

Co-authored-by: ZhangZifei <[email protected]>

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l2tlb: optimize l2tlb prefetcher, able to across 2MB (#1129)

l2tlb: add next-line prefetcher (#1108)

预取时机：

或者 发生miss时
或者 发生hit，但是hit的entry是预取上来的
当 页表2MB的level命中
当 预取项不跨2MB项对应的4KB page frame

前面两个限制是为了限制预取的数量

后面两个限制是限制预取请求只会访问最后一级页表

l2tlb: add next-line prefetcher (#1108)

预取时机：

或者 发生miss时
或者 发生hit，但是hit的entry是预取上来的
当 页表2MB的level命中
当 预取项不跨2MB项对应的4KB page frame

前面两个限制是为了限制预取的数量

后面两个限制是限制预取请求只会访问最后一级页表 -› 不占用FSM & （几乎）不会重新访问cache，造成卡死。

=============
some workloads: gcc(5.4%), wrf(13.6%),milc(9.2%)'s ipc increase.
some workloads decrease: namd(-2.5%).
but l2tlb's perf counters are better.
So I think it is worthy to adding the simple next-line prefetch.

The workloads are of ci and in cold-start state, so prefetch may seems to be much better than it should be.
But l2tlb's memory access ability is much better than what it needs, so the prefetch can be added.
=============

* mmu.l2tlb: add params filterSize

* mmu.l2tlb: add prefetch,dont work well

* mmu.l2tlb: add prefetch relative perf counter

* l2tlb: prefetch recv miss req and 'hit but pre-fetched' req

* l2tlb: fix some perf counter about prefetch

* l2tlb: prefetch not cross 2MB && not recv when 2MB level miss

* ci: when error, copy emu and SimTop.v to WAVE_HOME

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