xref: /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala (revision 6d4041f79d979c964d875e9511b462658d1b9fe6)
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 *          http://license.coscl.org.cn/MulanPSL2
9 *
10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13 *
14 * See the Mulan PSL v2 for more details.
15 ***************************************************************************************/
16
17package xiangshan.backend.rob
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3.{Mem, Mux, Vec, _}
21import chisel3.util._
22import difftest._
23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
24import utility._
25import utils._
26import xiangshan._
27import xiangshan.backend.BackendParams
28import xiangshan.backend.Bundles.{DynInst, ExceptionInfo, ExuOutput}
29import xiangshan.backend.fu.{FuConfig, FuType}
30import xiangshan.frontend.FtqPtr
31import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr}
32import xiangshan.backend.Bundles.{DynInst, ExceptionInfo, ExuOutput}
33import xiangshan.backend.ctrlblock.{DebugLSIO, DebugLsInfo, LsTopdownInfo}
34import xiangshan.backend.fu.vector.Bundles.VType
35import xiangshan.backend.rename.SnapshotGenerator
36
37import scala.collection.immutable.Nil
38
39
40
41object RobBundles extends HasCircularQueuePtrHelper {
42
43  class RobEntryBundle(implicit p: Parameters) extends XSBundle {
44
45    // data begin
46    val vls = Bool()
47    // some instructions are not allowed to trigger interrupts
48    // They have side effects on the states of the processor before they write back
49    val interrupt_safe = Bool()
50    val fpWen = Bool()
51    val rfWen = Bool()
52    val wflags = Bool()
53    val commitType = CommitType()
54    val ftqIdx = new FtqPtr
55    val ftqOffset = UInt(log2Up(PredictWidth).W)
56    val isRVC = Bool()
57    val isVset = Bool()
58    val isHls = Bool()
59    val instrSize = UInt(log2Ceil(RenameWidth + 1).W)
60    val loadWaitBit = Bool()    // for perfEvents
61    val eliminatedMove = Bool() // for perfEvents
62    // data end
63
64    // status begin
65    val valid = Bool()
66    val fflags = UInt(5.W)
67    val mmio = Bool()
68    // store will be commited if both sta & std have been writebacked
69    val stdWritebacked = Bool()
70    val vxsat = Bool()
71    val realDestSize = UInt(log2Up(MaxUopSize + 1).W)
72    val uopNum = UInt(log2Up(MaxUopSize + 1).W)
73    val commitTrigger = Bool()
74    // status end
75
76    // debug_begin
77    val debug_pc = OptionWrapper(backendParams.debugEn, UInt(VAddrBits.W))
78    val debug_instr = OptionWrapper(backendParams.debugEn, UInt(32.W))
79    val debug_ldest = OptionWrapper(backendParams.debugEn, UInt(6.W))
80    val debug_pdest = OptionWrapper(backendParams.debugEn, UInt(PhyRegIdxWidth.W))
81    val debug_fuType = OptionWrapper(backendParams.debugEn, FuType())
82    // debug_end
83
84    def isWritebacked: Bool = !uopNum.orR && stdWritebacked
85    def isUopWritebacked: Bool = !uopNum.orR
86
87  }
88
89  class RobCommitEntryBundle(implicit p: Parameters) extends XSBundle {
90    val walk_v = Bool()
91    val commit_v = Bool()
92    val commit_w = Bool()
93    val realDestSize = UInt(log2Up(MaxUopSize + 1).W)
94    val interrupt_safe = Bool()
95    val wflags = Bool()
96    val fflags = UInt(5.W)
97    val vxsat = Bool()
98    val isRVC = Bool()
99    val isVset = Bool()
100    val isHls = Bool()
101    val commitType = CommitType()
102    val ftqIdx = new FtqPtr
103    val ftqOffset = UInt(log2Up(PredictWidth).W)
104    val instrSize = UInt(log2Ceil(RenameWidth + 1).W)
105    val fpWen = Bool()
106    val rfWen = Bool()
107    val loadWaitBit = Bool() // for perfEvents
108    val isMove = Bool()      // for perfEvents
109    // debug_begin
110    val debug_pc = OptionWrapper(backendParams.debugEn, UInt(VAddrBits.W))
111    val debug_instr = OptionWrapper(backendParams.debugEn, UInt(32.W))
112    val debug_ldest = OptionWrapper(backendParams.debugEn, UInt(6.W))
113    val debug_pdest = OptionWrapper(backendParams.debugEn, UInt(PhyRegIdxWidth.W))
114    val debug_fuType = OptionWrapper(backendParams.debugEn, FuType())
115    // debug_end
116    def dirtyFs = fpWen
117  }
118
119  def connectEnq(robEntry: RobEntryBundle, robEnq: DynInst): Unit = {
120    robEntry.wflags := robEnq.wfflags
121    robEntry.commitType := robEnq.commitType
122    robEntry.ftqIdx := robEnq.ftqPtr
123    robEntry.ftqOffset := robEnq.ftqOffset
124    robEntry.isRVC := robEnq.preDecodeInfo.isRVC
125    robEntry.isVset := robEnq.isVset
126    robEntry.isHls := robEnq.isHls
127    robEntry.instrSize := robEnq.instrSize
128    robEntry.rfWen := robEnq.rfWen
129    robEntry.fpWen := robEnq.dirtyFs
130    robEntry.loadWaitBit := robEnq.loadWaitBit
131    robEntry.eliminatedMove := robEnq.eliminatedMove
132    robEntry.debug_pc.foreach(_ := robEnq.pc)
133    robEntry.debug_instr.foreach(_ := robEnq.instr)
134    robEntry.debug_ldest.foreach(_ := robEnq.ldest)
135    robEntry.debug_pdest.foreach(_ := robEnq.pdest)
136    robEntry.debug_fuType.foreach(_ := robEnq.fuType)
137  }
138
139  def connectCommitEntry(robCommitEntry: RobCommitEntryBundle, robEntry: RobEntryBundle): Unit = {
140    robCommitEntry.walk_v := robEntry.valid
141    robCommitEntry.commit_v := robEntry.valid
142    robCommitEntry.commit_w := (robEntry.uopNum === 0.U) && (robEntry.stdWritebacked === true.B)
143    robCommitEntry.realDestSize := robEntry.realDestSize
144    robCommitEntry.interrupt_safe := robEntry.interrupt_safe
145    robCommitEntry.rfWen := robEntry.rfWen
146    robCommitEntry.fpWen := robEntry.fpWen
147    robCommitEntry.fflags := robEntry.fflags
148    robCommitEntry.wflags := robEntry.wflags
149    robCommitEntry.vxsat := robEntry.vxsat
150    robCommitEntry.isRVC := robEntry.isRVC
151    robCommitEntry.isVset := robEntry.isVset
152    robCommitEntry.isHls := robEntry.isHls
153    robCommitEntry.ftqIdx := robEntry.ftqIdx
154    robCommitEntry.ftqOffset := robEntry.ftqOffset
155    robCommitEntry.commitType := robEntry.commitType
156    robCommitEntry.instrSize := robEntry.instrSize
157    robCommitEntry.loadWaitBit := robEntry.loadWaitBit
158    robCommitEntry.isMove := robEntry.eliminatedMove
159    robCommitEntry.debug_pc.foreach(_ := robEntry.debug_pc.get)
160    robCommitEntry.debug_instr.foreach(_ := robEntry.debug_instr.get)
161    robCommitEntry.debug_ldest.foreach(_ := robEntry.debug_ldest.get)
162    robCommitEntry.debug_pdest.foreach(_ := robEntry.debug_pdest.get)
163    robCommitEntry.debug_fuType.foreach(_ := robEntry.debug_fuType.get)
164  }
165}
166
167import RobBundles._
168
169class RobPtr(entries: Int) extends CircularQueuePtr[RobPtr](
170  entries
171) with HasCircularQueuePtrHelper {
172
173  def this()(implicit p: Parameters) = this(p(XSCoreParamsKey).RobSize)
174
175  def needFlush(redirect: Valid[Redirect]): Bool = {
176    val flushItself = redirect.bits.flushItself() && this === redirect.bits.robIdx
177    redirect.valid && (flushItself || isAfter(this, redirect.bits.robIdx))
178  }
179
180  def needFlush(redirect: Seq[Valid[Redirect]]): Bool = VecInit(redirect.map(needFlush)).asUInt.orR
181
182  def lineHeadPtr()(implicit p: Parameters): RobPtr = {
183    val CommitWidth = p(XSCoreParamsKey).CommitWidth
184    val out = Wire(new RobPtr)
185    out.flag := this.flag
186    out.value := Cat(this.value(this.PTR_WIDTH-1, log2Up(CommitWidth)), 0.U(log2Up(CommitWidth).W))
187    out
188  }
189
190}
191
192object RobPtr {
193  def apply(f: Bool, v: UInt)(implicit p: Parameters): RobPtr = {
194    val ptr = Wire(new RobPtr)
195    ptr.flag := f
196    ptr.value := v
197    ptr
198  }
199}
200
201class RobCSRIO(implicit p: Parameters) extends XSBundle {
202  val intrBitSet = Input(Bool())
203  val trapTarget = Input(UInt(VAddrBits.W))
204  val isXRet     = Input(Bool())
205  val wfiEvent   = Input(Bool())
206
207  val fflags     = Output(Valid(UInt(5.W)))
208  val vxsat      = Output(Valid(Bool()))
209  val vstart     = Output(Valid(UInt(XLEN.W)))
210  val dirty_fs   = Output(Bool())
211  val perfinfo   = new Bundle {
212    val retiredInstr = Output(UInt(3.W))
213  }
214
215  val vcsrFlag   = Output(Bool())
216}
217
218class RobLsqIO(implicit p: Parameters) extends XSBundle {
219  val lcommit = Output(UInt(log2Up(CommitWidth + 1).W))
220  val scommit = Output(UInt(log2Up(CommitWidth + 1).W))
221  val pendingld = Output(Bool())
222  val pendingst = Output(Bool())
223  val commit = Output(Bool())
224  val pendingPtr = Output(new RobPtr)
225  val pendingPtrNext = Output(new RobPtr)
226
227  val mmio = Input(Vec(LoadPipelineWidth, Bool()))
228  // Todo: what's this?
229  val uop = Input(Vec(LoadPipelineWidth, new DynInst))
230}
231
232class RobEnqIO(implicit p: Parameters) extends XSBundle {
233  val canAccept = Output(Bool())
234  val isEmpty = Output(Bool())
235  // valid vector, for robIdx gen and walk
236  val needAlloc = Vec(RenameWidth, Input(Bool()))
237  val req = Vec(RenameWidth, Flipped(ValidIO(new DynInst)))
238  val resp = Vec(RenameWidth, Output(new RobPtr))
239}
240
241class RobCoreTopDownIO(implicit p: Parameters) extends XSBundle {
242  val robHeadVaddr = Valid(UInt(VAddrBits.W))
243  val robHeadPaddr = Valid(UInt(PAddrBits.W))
244}
245
246class RobDispatchTopDownIO extends Bundle {
247  val robTrueCommit = Output(UInt(64.W))
248  val robHeadLsIssue = Output(Bool())
249}
250
251class RobDebugRollingIO extends Bundle {
252  val robTrueCommit = Output(UInt(64.W))
253}
254
255class RobExceptionInfo(implicit p: Parameters) extends XSBundle {
256  // val valid = Bool()
257  val robIdx = new RobPtr
258  val ftqPtr = new FtqPtr
259  val ftqOffset = UInt(log2Up(PredictWidth).W)
260  val exceptionVec = ExceptionVec()
261  val flushPipe = Bool()
262  val isVset = Bool()
263  val replayInst = Bool() // redirect to that inst itself
264  val singleStep = Bool() // TODO add frontend hit beneath
265  val crossPageIPFFix = Bool()
266  val trigger = new TriggerCf
267  val vstartEn = Bool()
268  val vstart = UInt(XLEN.W)
269
270  def has_exception = exceptionVec.asUInt.orR || flushPipe || singleStep || replayInst || trigger.canFire
271  def not_commit = exceptionVec.asUInt.orR || singleStep || replayInst || trigger.canFire
272  // only exceptions are allowed to writeback when enqueue
273  def can_writeback = exceptionVec.asUInt.orR || singleStep || trigger.canFire
274}
275
276class RobFlushInfo(implicit p: Parameters) extends XSBundle {
277  val ftqIdx = new FtqPtr
278  val robIdx = new RobPtr
279  val ftqOffset = UInt(log2Up(PredictWidth).W)
280  val replayInst = Bool()
281}
282