feat(Difftest): add multi-core vector load check (#4361)

Currently, we implement the multi core vector load check in difftest.
We modified difftest and NEMU and added related content in XiangShan.

timing(Rob): modify selection from robentries to robDeqGroup (#4067)

timing(rob): enqRob pipe for better timing

fix(trace): remove traceTrap & tracePriv from trace pipeline

feat(trace): add trace buffer.

feat(NCld): support WMO access for NC ld

* feat(LDU): add support for NC in LoadUnit

* feat(LQ,UB): add support for NC in load queue and uncache buffer

* chore(pbmt): add xsperf for nc ld statistic

fix(dcsr): debug support critical error state

* support nmip, cetrig, extcause fileds in dcsr.
* critical error state enter dmode when dcsr.cetrig assert.

area(Rob): remove RobEntryBundle's parameters related to perfCount (#3833)

fix(VecExcp): use `isEnqExcp` to distinguish pc and mem trigger (#3755)

Futher fix after #3722.

fix(csr): fix width of instruction commit (#3734)

Due to the rob compression mechanism, the number of instructions
committed per cycle may be greater than 7.
And the source signal `retiredInstr` s

fix(csr): fix width of instruction commit (#3734)

Due to the rob compression mechanism, the number of instructions
committed per cycle may be greater than 7.
And the source signal `retiredInstr` sent by rob to the csr module has a
bit width of 3, while the sink signal `instNum` has a bit width of 7,
causing the low bits to be truncated when any cycle the number of commit
instructions is greater than 7, making the minstret update inaccurate.

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feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merg

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merge will be handled first, and then the registers needed to move will be handled later.
* The need merge vdIdx can be until 8, so 4 bits reg is needed.
* If the instruction is indexed, the eew of vd is sew from vtype. Otherwise, the eew of vd is encoded in instruction.
* Use ivemulNoLessThanM1 and dvemulNoLessThanM1 to produce vemul_i_d to avoid either demul or iemul is less than M1.
* For whole register load, need handle NF(nf + 1) dest regs.
* Use data EMUL to calculate number of dest reg.
* GetE8OffsetInVreg will return the n-th 8bit which idx mapped to.
* Since xs will flush pipe, when vstart is not 0 and execute vector mem inst, the value of vstart in CSR is the
first element of this vector instruction. When exception occurs, the vstart in writeback bundle is the new one,
So writebacked vstart should never be used as the beginning of vector mem operation.
* Non-seg indexed load use non-sequential vd.
* When "index emul" / "data emul" equals 2,
the old vd is located in vuopidx 0, 2, 4, 6,
the new vd is located in vuopidx 1, 3, 5, 7.
* Make rename's input not ready until VecExcpMod not busy.
* Delay trap passed to difftest until VecExcpMod not busy.
* Rab commit to VecExcpMod as it commit to Rat, and select real load reg maps in VecExcpMod.
* Use isDstMask to distinguish vlm and other vle.
* When isWhole, vd regs are sequential.

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feat(VLSU): set vstart when the support vector accesses anomalies

feat(Rob): support vld exception write vstart

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs f

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs for
physical design to be verified.

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fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

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Rob: fix bug of rob commit. (#3418)

In this PR, the main goal is to fix the bug encountered during ROB
commit. However, resolving this issue requires information about
`iretire` and `ilastsize`, w

Rob: fix bug of rob commit. (#3418)

In this PR, the main goal is to fix the bug encountered during ROB
commit. However, resolving this issue requires information about
`iretire` and `ilastsize`, which need be collected by the trace.
Therefore, I have also included the trace interface in this PR.

The specific changes are as follows:
* When rob commit, update the ftqIdx and ftqOffset to correctly notify
the frontend which instructions have been committed.
* In each robentry, the ftqIdx and ftqOffset belong to the first
instruction that was compressed, that is Necessary when exceptions
happen.
* Add trace Interface in hart.
* Add trace parameter in parameter.scala.
* Collect trace infomation in backend pipeline.

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Trigger: refactor trigger information in pipeline. (#3403)

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

--

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

---------

Co-authored-by: xiaofeibao <[email protected]>

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Rob: set dirtyFS when fpwen or wflags is high

ROB: clear flushPipe when the enq uop has exception (#3281)

build: purge chisel 3 and add deprecation check (#3250)

NewCSR: executing vecOPF inst will set FS=Dirty

Rob: fix bug of exception (#3161)

1.when writeback exception, rob may commit next cycle. 2.when fulshOut,
rob commit info to ftq may 4 cycle after redirect but redirect info to
ftq need 5 cycle.

RenameTable: fix width of rename table addr ports (#3128)

Different rename table has different numbers of entries, leading to
differences in the width of read/write ports. In the code we see the
w

RenameTable: fix width of rename table addr ports (#3128)

Different rename table has different numbers of entries, leading to
differences in the width of read/write ports. In the code we see the
widths of all read/write ports were set to 6, which works well but is
not parameterized. Now these widths are modified to be controlled by
parameters.

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vl: assign vl in csr to the value store in vl regfiles