xref: /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala (revision f7063a43ab34da917ba6c670d21871314340c550) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.{HasCircularQueuePtrHelper, GatedValidRegNext}
7import utils.{MathUtils, OptionWrapper}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.fu.FuType
11import xiangshan.backend.datapath.DataSource
12import xiangshan.backend.rob.RobPtr
13import xiangshan.backend.issue.EntryBundles._
14import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
15
16
17class OthersEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
18  //input
19  val commonIn        = new CommonInBundle
20  //output
21  val commonOut       = new CommonOutBundle
22
23  def wakeup          = commonIn.wakeUpFromWB ++ commonIn.wakeUpFromIQ
24}
25
26class OthersEntry(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
27  val io = IO(new OthersEntryIO)
28
29  val common          = Wire(new CommonWireBundle)
30  val entryUpdate     = Wire(new EntryBundle)
31  val entryRegNext    = Wire(new EntryBundle)
32  val hasWakeupIQ     = OptionWrapper(params.hasIQWakeUp, Wire(new CommonIQWakeupBundle))
33
34  //Reg
35  val validReg = GatedValidRegNext(common.validRegNext, false.B)
36  val entryReg = RegEnable(entryRegNext, validReg || common.validRegNext)
37
38  //Wire
39  CommonWireConnect(common, hasWakeupIQ, validReg, entryReg.status, io.commonIn, false)
40
41  if (params.hasIQWakeUp) {
42    ShiftLoadDependency(hasWakeupIQ.get)
43    CommonIQWakeupConnect(common, hasWakeupIQ.get, validReg, entryReg.status, io.commonIn, false)
44  }
45
46  when(io.commonIn.enq.valid) {
47    assert(common.enqReady, "Entry is not ready when enq is valid\n")
48  }
49
50  when(io.commonIn.enq.valid) {
51    entryRegNext := io.commonIn.enq.bits
52  }.otherwise {
53    entryRegNext := entryUpdate
54  }
55
56  EntryRegCommonConnect(common, hasWakeupIQ, validReg, entryUpdate, entryReg, entryReg.status, io.commonIn, false)
57
58  //output
59  CommonOutConnect(io.commonOut, common, hasWakeupIQ, validReg, entryUpdate, entryReg, entryReg.status, io.commonIn, false, isComp)
60}
61
62class OthersEntryVecMem(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends OthersEntry(isComp)
63  with HasCircularQueuePtrHelper {
64
65  require(params.isVecMemIQ, "OthersEntryVecMem can only be instance of VecMem IQ")
66
67  EntryVecMemConnect(io.commonIn, common, validReg, entryReg, entryRegNext, entryUpdate)
68}
69
70object OthersEntry {
71  def apply(isComp: Boolean)(implicit p: Parameters, iqParams: IssueBlockParams): OthersEntry = {
72    iqParams.schdType match {
73      case IntScheduler() => new OthersEntry(isComp)
74      case MemScheduler() =>
75        if (iqParams.isVecMemIQ) new OthersEntryVecMem(isComp)
76        else new OthersEntry(isComp)
77      case VfScheduler() => new OthersEntry(isComp)
78      case _ => null
79    }
80  }
81}