xref: /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala (revision 99944b791905d63476e6e29037786d4ed716a81d) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.HasCircularQueuePtrHelper
7import utils.{MathUtils, OptionWrapper}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.fu.FuType
11import xiangshan.backend.datapath.DataSource
12import xiangshan.backend.rob.RobPtr
13import xiangshan.backend.issue.EntryBundles._
14import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
15
16
17class OthersEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
18  //input
19  val commonIn        = new CommonInBundle
20  //output
21  val commonOut       = new CommonOutBundle
22
23  def wakeup          = commonIn.wakeUpFromWB ++ commonIn.wakeUpFromIQ
24}
25
26class OthersEntry(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
27  val io = IO(new OthersEntryIO)
28
29  val validReg        = RegInit(false.B)
30  val entryReg        = Reg(new EntryBundle)
31
32  val common          = Wire(new CommonWireBundle)
33  val entryUpdate     = Wire(new EntryBundle)
34  val entryRegNext    = Wire(new EntryBundle)
35  val hasWakeupIQ     = OptionWrapper(params.hasIQWakeUp, Wire(new CommonIQWakeupBundle))
36
37  //Reg
38  validReg := common.validRegNext
39  entryReg := entryRegNext
40
41  //Wire
42  CommonWireConnect(common, hasWakeupIQ, validReg, entryReg.status, io.commonIn, false)
43
44  if (params.hasIQWakeUp) {
45    ShiftLoadDependency(hasWakeupIQ.get)
46    CommonIQWakeupConnect(common, hasWakeupIQ.get, validReg, entryReg.status, io.commonIn, false)
47  }
48
49  when(io.commonIn.enq.valid) {
50    assert(common.enqReady, "Entry is not ready when enq is valid\n")
51  }
52
53  when(io.commonIn.enq.valid) {
54    entryRegNext := io.commonIn.enq.bits
55  }.otherwise {
56    entryRegNext := entryUpdate
57  }
58
59  EntryRegCommonConnect(common, hasWakeupIQ, validReg, entryUpdate, entryReg, entryReg.status, io.commonIn, false)
60
61  //output
62  CommonOutConnect(io.commonOut, common, hasWakeupIQ, validReg, entryUpdate, entryReg, entryReg.status, io.commonIn, false, isComp)
63}
64
65class OthersEntryMem(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends OthersEntry(isComp)
66  with HasCircularQueuePtrHelper {
67  EntryMemConnect(io.commonIn, common, validReg, entryReg, entryRegNext, entryUpdate, false)
68}
69
70class OthersEntryVecMemAddr(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends OthersEntryMem(isComp) {
71
72  require(params.isVecMemAddrIQ, "OthersEntryVecMemAddr can only be instance of VecMemAddr IQ")
73
74  EntryVecMemConnect(io.commonIn, common, validReg, entryReg, entryRegNext, entryUpdate, false, true)
75}
76
77class OthersEntryVecMemData(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends OthersEntry(isComp)
78  with HasCircularQueuePtrHelper {
79
80  require(params.isVecStDataIQ, "OthersEntryVecMemData can only be instance of VecMemData IQ")
81
82  EntryVecMemConnect(io.commonIn, common, validReg, entryReg, entryRegNext, entryUpdate, false, false)
83}
84
85object OthersEntry {
86  def apply(isComp: Boolean)(implicit p: Parameters, iqParams: IssueBlockParams): OthersEntry = {
87    iqParams.schdType match {
88      case IntScheduler() => new OthersEntry(isComp)
89      case MemScheduler() =>
90        if (iqParams.isLdAddrIQ || iqParams.isStAddrIQ || iqParams.isHyAddrIQ) new OthersEntryMem(isComp)
91        else if (iqParams.isVecMemAddrIQ) new OthersEntryVecMemAddr(isComp)
92        else if (iqParams.isVecStDataIQ) new OthersEntryVecMemData(isComp)
93        else new OthersEntry(isComp)
94      case VfScheduler() => new OthersEntry(isComp)
95      case _ => null
96    }
97  }
98}