xref: /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala (revision 7cbafe1adaecee49ce5b5f5ec3ef941f3a71360b) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.HasCircularQueuePtrHelper
7import utils.{MathUtils, OptionWrapper}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.fu.FuType
11import xiangshan.backend.datapath.DataSource
12import xiangshan.backend.rob.RobPtr
13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
14
15
16class OthersEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
17  //input
18  val enq = Flipped(ValidIO(new EntryBundle))
19  val flush = Flipped(ValidIO(new Redirect))
20  val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
21  val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
22  val og0Cancel = Input(ExuOH(backendParams.numExu))
23  val og1Cancel = Input(ExuOH(backendParams.numExu))
24  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
25  val deqSel = Input(Bool())
26  val transSel = Input(Bool())
27  val issueResp = Flipped(ValidIO(new EntryDeqRespBundle))
28  val deqPortIdxWrite = Input(UInt(1.W))
29  //output
30  val valid = Output(Bool())
31  val canIssue = Output(Bool())
32  val clear = Output(Bool())
33  val fuType = Output(FuType())
34  val dataSource = Output(Vec(params.numRegSrc, DataSource()))
35  val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, ExuOH())))
36  val srcTimer = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, UInt(3.W))))
37  val isFirstIssue = Output(Bool())
38  val entry = ValidIO(new EntryBundle)
39  val robIdx = Output(new RobPtr)
40  val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx()))
41  val deqPortIdxRead = Output(UInt(1.W))
42  val issueTimerRead = Output(UInt(2.W))
43  // mem only
44  val fromMem = if(params.isMemAddrIQ) Some(new Bundle {
45    val stIssuePtr = Input(new SqPtr)
46    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
47  }) else None
48  // vector mem only
49  val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle {
50    val sqDeqPtr = Input(new SqPtr)
51    val lqDeqPtr = Input(new LqPtr)
52  })
53  // debug
54  val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool()))
55
56  def wakeup = wakeUpFromWB ++ wakeUpFromIQ
57}
58
59class OthersEntry(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
60  val io = IO(new OthersEntryIO)
61
62  val validReg = RegInit(false.B)
63  val entryReg = Reg(new EntryBundle)
64
65  val validRegNext = Wire(Bool())
66  val entryRegNext = Wire(new EntryBundle)
67  val flushed = Wire(Bool())
68  val clear = Wire(Bool())
69  val deqSuccess = Wire(Bool())
70  val srcWakeUp = Wire(Vec(params.numRegSrc, Bool()))
71  val srcWakeUpByWB = Wire(Vec(params.numRegSrc, Bool()))
72  val srcCancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
73  val srcLoadCancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
74  val srcWakeUpByIQVec = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
75  val srcWakeUpByIQWithoutCancel = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
76  val srcWakeUpL1ExuOHOut = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, ExuOH())))
77  val srcLoadDependencyOut = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W)))))
78  val srcWakeUpButCancel = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
79  val wakeupLoadDependencyByIQVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
80  val shiftedWakeupLoadDependencyByIQVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
81  val shiftedWakeupLoadDependencyByIQBypassVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
82  val cancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
83
84  //Reg
85  validReg := validRegNext
86  entryReg := entryRegNext
87
88  //Wire
89  flushed := entryReg.status.robIdx.needFlush(io.flush)
90  clear := flushed || deqSuccess
91  deqSuccess := io.issueResp.valid && io.issueResp.bits.respType === RSFeedbackType.fuIdle && !srcLoadCancelVec.map(_.reduce(_ || _)).getOrElse(false.B)
92  srcWakeUpByWB := io.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(entryReg.status.psrc zip entryReg.status.srcType, bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq
93  srcWakeUp := srcWakeUpByWB.zip(srcWakeUpByIQVec).map { case (x, y) => x || y.asUInt.orR }
94
95  shiftedWakeupLoadDependencyByIQVec
96    .zip(wakeupLoadDependencyByIQVec)
97    .zip(params.wakeUpInExuSources.map(_.name)).foreach {
98    case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach {
99      case ((dep, originalDep), deqPortIdx) =>
100        if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
101          dep := (originalDep << 2).asUInt | 2.U
102        else
103          dep := originalDep << 1
104    }
105  }
106  shiftedWakeupLoadDependencyByIQBypassVec
107    .zip(wakeupLoadDependencyByIQVec)
108    .zip(params.wakeUpInExuSources.map(_.name)).foreach {
109    case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach {
110      case ((dep, originalDep), deqPortIdx) =>
111        if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
112          dep := (originalDep << 2).asUInt | 2.U
113        else
114          dep := originalDep << 1
115    }
116  }
117
118  when(io.enq.valid && io.transSel) {
119    validRegNext := true.B
120  }.elsewhen(clear) {
121    validRegNext := false.B
122  }.otherwise {
123    validRegNext := validReg
124  }
125
126  if (params.hasIQWakeUp) {
127    srcCancelVec.get.zip(srcLoadCancelVec.get).zip(srcWakeUpByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) =>
128      val ldTransCancel = Mux1H(wakeUpByIQVec, wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), io.ldCancel)))
129      srcLoadCancel := LoadShouldCancel(entryReg.status.srcLoadDependency.map(_(srcIdx)), io.ldCancel)
130      srcCancel := srcLoadCancel || ldTransCancel
131    }
132    cancelVec.get.foreach(_ := false.B)
133  }
134
135  if (io.wakeUpFromIQ.isEmpty) {
136    srcWakeUpByIQVec := 0.U.asTypeOf(srcWakeUpByIQVec)
137    wakeupLoadDependencyByIQVec := 0.U.asTypeOf(wakeupLoadDependencyByIQVec)
138  } else {
139    val wakeupVec: Seq[Seq[Bool]] = io.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) =>
140      bundle.bits.wakeUp(entryReg.status.psrc zip entryReg.status.srcType, bundle.valid)
141    ).toSeq.transpose
142    val cancelSel = io.wakeUpFromIQ.map(x => x.bits.exuIdx).map(x => io.og0Cancel(x))
143    srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel }))
144    srcWakeUpButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel }))
145    srcWakeUpByIQWithoutCancel := wakeupVec.map(x => VecInit(x))
146    wakeupLoadDependencyByIQVec := io.wakeUpFromIQ.map(_.bits.loadDependency).toSeq
147  }
148
149  when(io.enq.valid && io.transSel) {
150    entryRegNext := io.enq.bits
151  }.otherwise {
152    //update status
153    entryRegNext.status.srcState.zip(entryReg.status.srcState).zip(srcWakeUp).zipWithIndex.foreach { case (((stateNext, state), wakeup), srcIdx) =>
154      val cancel = srcCancelVec.map(_ (srcIdx)).getOrElse(false.B)
155      stateNext := Mux(cancel, false.B, wakeup | state)
156      if (params.hasIQWakeUp) {
157        cancelVec.get(srcIdx) := cancel
158      }
159    }
160    entryRegNext.status.dataSources.zip(entryReg.status.dataSources).zip(srcWakeUpByIQVec).foreach {
161      case ((dataSourceNext: DataSource, dataSource: DataSource), wakeUpByIQOH: Vec[Bool]) =>
162        when(wakeUpByIQOH.asUInt.orR) {
163          dataSourceNext.value := DataSource.bypass
164        }.otherwise {
165          dataSourceNext.value := DataSource.reg
166        }
167    }
168    if (params.hasIQWakeUp) {
169      entryRegNext.status.srcWakeUpL1ExuOH.get.zip(srcWakeUpByIQVec).zip(srcWakeUp).zipWithIndex.foreach {
170        case (((exuOH: UInt, wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) =>
171          when(wakeUpByIQOH.asUInt.orR) {
172            exuOH := Mux1H(wakeUpByIQOH, io.wakeUpFromIQ.toSeq.map(x => MathUtils.IntToOH(x.bits.exuIdx).U(backendParams.numExu.W)))
173          }.elsewhen(wakeUp) {
174            exuOH := 0.U.asTypeOf(exuOH)
175          }.otherwise {
176            exuOH := entryReg.status.srcWakeUpL1ExuOH.get(srcIdx)
177          }
178      }
179      entryRegNext.status.srcTimer.get.zip(entryReg.status.srcTimer.get).zip(srcWakeUpByIQVec).zipWithIndex.foreach {
180        case (((srcIssuedTimerNext, srcIssuedTimer), wakeUpByIQOH: Vec[Bool]), srcIdx) =>
181          srcIssuedTimerNext := MuxCase(3.U, Seq(
182            // T0: waked up by IQ, T1: reset timer as 1
183            wakeUpByIQOH.asUInt.orR -> 2.U,
184            // do not overflow
185            srcIssuedTimer.andR -> srcIssuedTimer,
186            // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq
187            (validReg && SrcState.isReady(entryReg.status.srcState(srcIdx)) && entryReg.status.srcWakeUpL1ExuOH.get.asUInt.orR) -> (srcIssuedTimer + 1.U)
188          ))
189      }
190      entryRegNext.status.srcLoadDependency.get.zip(entryReg.status.srcLoadDependency.get).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
191        case (((loadDependencyNext, loadDependency), wakeUpByIQVec), wakeup) =>
192          loadDependencyNext :=
193            Mux(wakeup,
194              Mux1H(wakeUpByIQVec, shiftedWakeupLoadDependencyByIQVec),
195              Mux(validReg && loadDependency.asUInt.orR, VecInit(loadDependency.map(i => i(i.getWidth - 2, 0) << 1)), loadDependency)
196            )
197      }
198    }
199    entryRegNext.status.issueTimer := "b10".U //otherwise
200    entryRegNext.status.deqPortIdx := 0.U //otherwise
201    when(io.deqSel){
202      entryRegNext.status.issueTimer := 0.U
203      entryRegNext.status.deqPortIdx := io.deqPortIdxWrite
204    }.elsewhen(entryReg.status.issued){
205      entryRegNext.status.issueTimer := entryReg.status.issueTimer + 1.U
206      entryRegNext.status.deqPortIdx := entryReg.status.deqPortIdx
207    }.otherwise {
208      entryRegNext.status.issueTimer := "b10".U
209      entryRegNext.status.deqPortIdx := 0.U
210    }
211    entryRegNext.status.psrc := entryReg.status.psrc
212    entryRegNext.status.srcType := entryReg.status.srcType
213    entryRegNext.status.fuType := entryReg.status.fuType
214    entryRegNext.status.robIdx := entryReg.status.robIdx
215    entryRegNext.status.uopIdx.foreach(_ := entryReg.status.uopIdx.get)
216    when(srcLoadCancelVec.map(_.reduce(_ || _)).getOrElse(false.B) || srcWakeUpButCancel.map(_.fold(false.B)(_ || _)).fold(false.B)(_ || _)) {
217      entryRegNext.status.issued := false.B
218    }.elsewhen(io.deqSel) {
219      entryRegNext.status.issued := true.B
220    }.elsewhen(io.issueResp.valid && RSFeedbackType.isBlocked(io.issueResp.bits.respType)) {
221      entryRegNext.status.issued := false.B
222    }.elsewhen(!entryReg.status.srcReady) {
223      entryRegNext.status.issued := false.B
224    }.otherwise {
225      entryRegNext.status.issued := entryReg.status.issued
226    }
227    entryRegNext.status.firstIssue := io.deqSel || entryReg.status.firstIssue
228    entryRegNext.status.blocked := false.B //todo
229    //remain imm and payload
230    entryRegNext.imm.foreach(_ := entryReg.imm.get)
231    entryRegNext.payload := entryReg.payload
232  }
233
234  //output
235  val canIssue = entryReg.status.canIssue && validReg && !srcCancelVec.getOrElse(false.B).asUInt.orR
236  val canIssueBypass = validReg && !entryReg.status.issued && !entryReg.status.blocked &&
237    VecInit(entryReg.status.srcState.zip(srcWakeUpByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) =>
238      val cancel = srcCancelVec.map(_ (srcIdx)).getOrElse(false.B)
239      Mux(cancel, false.B, wakeupVec.asUInt.orR | state)
240    }).asUInt.andR
241  io.dataSource.zip(entryReg.status.dataSources).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
242    case (((dataSourceOut: DataSource, dataSource: DataSource), wakeUpByIQOH: Vec[Bool]), wakeUpAll) =>
243      when(wakeUpByIQOH.asUInt.orR) {
244        dataSourceOut.value := DataSource.forward
245      }.otherwise {
246        dataSourceOut.value := dataSource.value
247      }
248  }
249  if (params.hasIQWakeUp) {
250    srcWakeUpL1ExuOHOut.get.zip(srcWakeUpByIQWithoutCancel).zip(srcWakeUp).zipWithIndex.foreach {
251      case (((exuOH: UInt, wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) =>
252        when(wakeUpByIQOH.asUInt.orR) {
253          exuOH := Mux1H(wakeUpByIQOH, io.wakeUpFromIQ.map(x => MathUtils.IntToOH(x.bits.exuIdx).U(backendParams.numExu.W)).toSeq)
254        }.otherwise {
255          exuOH := entryReg.status.srcWakeUpL1ExuOH.get(srcIdx)
256        }
257    }
258    srcLoadDependencyOut.get.zip(entryReg.status.srcLoadDependency.get).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
259      case (((loadDependencyOut, loadDependency), wakeUpByIQVec), wakeup) =>
260        loadDependencyOut := Mux1H(wakeUpByIQVec, shiftedWakeupLoadDependencyByIQBypassVec)
261    }
262    io.srcTimer.get.zip(entryReg.status.srcTimer.get).zip(srcWakeUpByIQWithoutCancel).zip(srcWakeUp).foreach {
263      case (((srcTimerOut, srcTimer), wakeUpByIQOH: Vec[Bool]), wakeUpAll) =>
264        when(wakeUpByIQOH.asUInt.orR) {
265          srcTimerOut := 1.U
266        }.otherwise {
267          srcTimerOut := srcTimer
268        }
269    }
270    io.srcWakeUpL1ExuOH.get := Mux(canIssueBypass && !canIssue, srcWakeUpL1ExuOHOut.get, entryReg.status.srcWakeUpL1ExuOH.get)
271  }
272  io.canIssue := (canIssue || canIssueBypass) && !flushed
273  io.clear := clear
274  io.fuType := entryReg.status.fuType
275  io.valid := validReg
276  io.isFirstIssue := !entryReg.status.firstIssue
277  io.entry.valid := validReg
278  io.entry.bits := entryReg
279  io.entry.bits.status.srcLoadDependency.foreach(_ := Mux(canIssueBypass && !canIssue, srcLoadDependencyOut.get, entryReg.status.srcLoadDependency.get))
280  io.robIdx := entryReg.status.robIdx
281  io.uopIdx.foreach(_ := entryReg.status.uopIdx.get)
282  io.issueTimerRead := entryReg.status.issueTimer
283  io.deqPortIdxRead := entryReg.status.deqPortIdx
284  io.cancel.foreach(_ := cancelVec.get.asUInt.orR)
285}
286
287class OthersEntryMem()(implicit p: Parameters, params: IssueBlockParams) extends OthersEntry
288  with HasCircularQueuePtrHelper {
289
290  val fromMem = io.fromMem.get
291
292  val memStatus = entryReg.status.mem.get
293  val memStatusNext = entryRegNext.status.mem.get
294  // load cannot be issued before older store, unless meet some condition
295  val blockedByOlderStore = isAfter(memStatusNext.sqIdx, fromMem.stIssuePtr)
296
297  val deqFailedForStdInvalid = io.issueResp.valid && io.issueResp.bits.respType === RSFeedbackType.dataInvalid
298
299  val staWaitedReleased = Cat(
300    fromMem.memWaitUpdateReq.robIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForRobIdx.value)
301  ).orR
302  val stdWaitedReleased = Cat(
303    fromMem.memWaitUpdateReq.sqIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForSqIdx.value)
304  ).orR
305  val olderStaNotViolate = staWaitedReleased && !memStatusNext.strictWait
306  val olderStdReady = stdWaitedReleased && memStatusNext.waitForStd
307  val waitStd = !olderStdReady
308  val waitSta = !olderStaNotViolate
309
310  when(io.enq.valid && io.transSel) {
311    memStatusNext.waitForSqIdx := io.enq.bits.status.mem.get.waitForSqIdx
312    // update by lfst at dispatch stage
313    memStatusNext.waitForRobIdx := io.enq.bits.status.mem.get.waitForRobIdx
314    // new load inst don't known if it is blocked by store data ahead of it
315    memStatusNext.waitForStd := false.B
316    // update by ssit at rename stage
317    memStatusNext.strictWait := io.enq.bits.status.mem.get.strictWait
318    memStatusNext.sqIdx := io.enq.bits.status.mem.get.sqIdx
319  }.elsewhen(deqFailedForStdInvalid) {
320    // Todo: check if need assign statusNext.block
321    memStatusNext.waitForSqIdx := io.issueResp.bits.dataInvalidSqIdx
322    memStatusNext.waitForRobIdx := memStatus.waitForRobIdx
323    memStatusNext.waitForStd := true.B
324    memStatusNext.strictWait := memStatus.strictWait
325    memStatusNext.sqIdx := memStatus.sqIdx
326  }.otherwise {
327    memStatusNext := memStatus
328  }
329
330  val shouldBlock = Mux(io.enq.valid && io.transSel, io.enq.bits.status.blocked, entryReg.status.blocked)
331  val blockNotReleased = waitStd || waitSta
332  val respBlock = deqFailedForStdInvalid
333  entryRegNext.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock
334}
335
336class OthersEntryVecMemAddr()(implicit p: Parameters, params: IssueBlockParams) extends OthersEntryMem {
337
338  require(params.isVecMemAddrIQ, "OthersEntryVecMemAddr can only be instance of VecMemAddr IQ")
339
340  val vecMemStatus = entryReg.status.vecMem.get
341  val vecMemStatusNext = entryRegNext.status.vecMem.get
342  val fromLsq = io.fromLsq.get
343
344  when(io.enq.valid && io.transSel) {
345    vecMemStatusNext.sqIdx := io.enq.bits.status.vecMem.get.sqIdx
346    vecMemStatusNext.lqIdx := io.enq.bits.status.vecMem.get.lqIdx
347  }.otherwise {
348    vecMemStatusNext := vecMemStatus
349  }
350
351  val isLsqHead = {
352    // if (params.isVecLdAddrIQ)
353      entryRegNext.status.vecMem.get.lqIdx <= fromLsq.lqDeqPtr &&
354    // else
355      entryRegNext.status.vecMem.get.sqIdx <= fromLsq.sqDeqPtr
356  }
357  dontTouch(shouldBlock)
358  dontTouch(blockNotReleased)
359  dontTouch(blockedByOlderStore)
360  dontTouch(respBlock)
361  dontTouch(isLsqHead)
362  dontTouch(waitStd)
363  dontTouch(waitSta)
364  dontTouch(memStatusNext)
365  dontTouch(fromMem)
366  dontTouch(io.issueResp)
367  dontTouch(isLsqHead)
368
369  entryRegNext.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock || !isLsqHead
370}
371
372class OthersEntryVecMemData()(implicit p: Parameters, params: IssueBlockParams) extends OthersEntry
373  with HasCircularQueuePtrHelper {
374
375  require(params.isVecStDataIQ, "OthersEntryVecMemData can only be instance of VecMemData IQ")
376
377  val vecMemStatus = entryReg.status.vecMem.get
378  val vecMemStatusNext = entryRegNext.status.vecMem.get
379  val fromLsq = io.fromLsq.get
380
381  when(io.enq.valid && io.transSel) {
382    vecMemStatusNext.sqIdx := io.enq.bits.status.vecMem.get.sqIdx
383    vecMemStatusNext.lqIdx := io.enq.bits.status.vecMem.get.lqIdx
384  }.otherwise {
385    vecMemStatusNext := vecMemStatus
386  }
387
388  val isLsqHead = entryRegNext.status.vecMem.get.sqIdx.value === fromLsq.sqDeqPtr.value
389
390  entryRegNext.status.blocked := !isLsqHead
391}
392
393object OthersEntry {
394  def apply(implicit p: Parameters, iqParams: IssueBlockParams): OthersEntry = {
395    iqParams.schdType match {
396      case IntScheduler() => new OthersEntry()
397      case MemScheduler() =>
398        if (iqParams.isLdAddrIQ || iqParams.isStAddrIQ || iqParams.isHyAddrIQ) new OthersEntryMem()
399        else if (iqParams.isVecMemAddrIQ) new OthersEntryVecMemAddr()
400        else if (iqParams.isVecStDataIQ) new OthersEntryVecMemData()
401        else new OthersEntry()
402      case VfScheduler() => new OthersEntry()
403      case _ => null
404    }
405  }
406}