xref: /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala (revision 3e7f92e5afe557e26f13d426f28179ee096d54b5) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.HasCircularQueuePtrHelper
7import utils.{MathUtils, OptionWrapper}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.fu.FuType
11import xiangshan.backend.datapath.DataSource
12import xiangshan.backend.rob.RobPtr
13import xiangshan.backend.issue.EntryBundles._
14import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
15
16
17class OthersEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
18  //input
19  val commonIn        = new CommonInBundle
20  //output
21  val commonOut       = new CommonOutBundle
22
23  def wakeup          = commonIn.wakeUpFromWB ++ commonIn.wakeUpFromIQ
24}
25
26class OthersEntry(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
27  val io = IO(new OthersEntryIO)
28
29  val validReg        = RegInit(false.B)
30
31  val common          = Wire(new CommonWireBundle)
32  val entryUpdate     = Wire(new EntryBundle)
33  val entryRegNext    = Wire(new EntryBundle)
34  val hasWakeupIQ     = OptionWrapper(params.hasIQWakeUp, Wire(new CommonIQWakeupBundle))
35
36  //Reg
37  val entryReg = RegEnable(entryRegNext, validReg || common.validRegNext)
38  validReg := common.validRegNext
39
40  //Wire
41  CommonWireConnect(common, hasWakeupIQ, validReg, entryReg.status, io.commonIn, false)
42
43  if (params.hasIQWakeUp) {
44    ShiftLoadDependency(hasWakeupIQ.get)
45    CommonIQWakeupConnect(common, hasWakeupIQ.get, validReg, entryReg.status, io.commonIn, false)
46  }
47
48  when(io.commonIn.enq.valid) {
49    assert(common.enqReady, "Entry is not ready when enq is valid\n")
50  }
51
52  when(io.commonIn.enq.valid) {
53    entryRegNext := io.commonIn.enq.bits
54  }.otherwise {
55    entryRegNext := entryUpdate
56  }
57
58  EntryRegCommonConnect(common, hasWakeupIQ, validReg, entryUpdate, entryReg, entryReg.status, io.commonIn, false)
59
60  //output
61  CommonOutConnect(io.commonOut, common, hasWakeupIQ, validReg, entryUpdate, entryReg, entryReg.status, io.commonIn, false, isComp)
62}
63
64class OthersEntryVecMem(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends OthersEntry(isComp)
65  with HasCircularQueuePtrHelper {
66
67  require(params.isVecMemIQ, "OthersEntryVecMem can only be instance of VecMem IQ")
68
69  EntryVecMemConnect(io.commonIn, common, validReg, entryReg, entryRegNext, entryUpdate)
70}
71
72object OthersEntry {
73  def apply(isComp: Boolean)(implicit p: Parameters, iqParams: IssueBlockParams): OthersEntry = {
74    iqParams.schdType match {
75      case IntScheduler() => new OthersEntry(isComp)
76      case MemScheduler() =>
77        if (iqParams.isVecMemIQ) new OthersEntryVecMem(isComp)
78        else new OthersEntry(isComp)
79      case VfScheduler() => new OthersEntry(isComp)
80      case _ => null
81    }
82  }
83}