1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig.PregWB 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14 15case class IssueBlockParams( 16 // top down 17 private val exuParams: Seq[ExeUnitParams], 18 numEntries : Int, 19 numEnq : Int, 20 numDeqOutside : Int = 0, 21 numWakeupFromOthers : Int = 0, 22 XLEN : Int = 64, 23 VLEN : Int = 128, 24 vaddrBits : Int = 39, 25 // calculate in scheduler 26 var idxInSchBlk : Int = 0, 27)( 28 implicit 29 val schdType: SchedulerType, 30) { 31 var backendParam: BackendParams = null 32 33 val exuBlockParams: Seq[ExeUnitParams] = exuParams.filterNot(_.fakeUnit) 34 35 val allExuParams = exuParams 36 37 def updateIdx(idx: Int): Unit = { 38 this.idxInSchBlk = idx 39 } 40 41 def inMemSchd: Boolean = schdType == MemScheduler() 42 43 def inIntSchd: Boolean = schdType == IntScheduler() 44 45 def inVfSchd: Boolean = schdType == VfScheduler() 46 47 def isMemAddrIQ: Boolean = inMemSchd && (LduCnt > 0 || StaCnt > 0 || VlduCnt > 0 || VstaCnt > 0 || HyuCnt > 0) 48 49 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 50 51 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 52 53 def isHyAddrIQ: Boolean = inMemSchd && HyuCnt > 0 54 55 def isVecMemAddrIQ: Boolean = inMemSchd && (VlduCnt > 0 || VstaCnt > 0) 56 57 def isVecLdAddrIQ: Boolean = inMemSchd && VlduCnt > 0 58 59 def isVecStAddrIQ: Boolean = inMemSchd && VstaCnt > 0 60 61 def isVecStDataIQ: Boolean = inMemSchd && VstdCnt > 0 62 63 def isVecMemIQ: Boolean = (isVecLdAddrIQ || isVecStAddrIQ || isVecStDataIQ) 64 65 def numExu: Int = exuBlockParams.count(!_.fakeUnit) 66 67 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 68 69 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 70 71 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 72 73 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 74 75 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 76 77 def numSrc: Int = exuBlockParams.map(_.numSrc).max 78 79 def readIntRf: Boolean = numIntSrc > 0 80 81 def readFpRf: Boolean = numFpSrc > 0 82 83 def readVecRf: Boolean = numVecSrc > 0 84 85 def readVfRf: Boolean = numVfSrc > 0 86 87 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 88 89 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 90 91 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 92 93 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 94 95 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 96 97 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 98 99 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 100 101 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 102 103 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 104 105 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 106 107 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 108 109 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 110 111 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 112 113 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 114 115 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 116 117 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 118 119 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 120 121 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 122 123 def numDeq: Int = numDeqOutside + exuBlockParams.length 124 125 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 126 127 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 128 129 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 130 131 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 132 133 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 134 135 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 136 137 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 138 139 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 140 141 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 142 143 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 144 145 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 146 147 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 148 149 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 150 151 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 152 153 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 154 155 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 156 157 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 158 159 def HyuCnt: Int = exuBlockParams.count(_.hasHyldaFu) // only count hylda, since it equals to hysta 160 161 def LdExuCnt = LduCnt + HyuCnt 162 163 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 164 165 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 166 167 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 168 169 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 170 171 def VstaCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "vsta")).sum 172 173 def VstdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "vstd")).sum 174 175 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 176 177 /** 178 * Get the regfile type that this issue queue need to read 179 */ 180 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 181 182 /** 183 * Get the regfile type that this issue queue need to read 184 */ 185 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 186 187 /** 188 * Get the max width of psrc 189 */ 190 def rdPregIdxWidth = { 191 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 192 } 193 194 /** 195 * Get the max width of pdest 196 */ 197 def wbPregIdxWidth = { 198 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 199 } 200 201 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 202 203 /** Get exu source wake up 204 * @todo replace with 205 * exuBlockParams 206 * .flatMap(_.iqWakeUpSinkPairs) 207 * .map(_.source) 208 * .distinctBy(_.name) 209 * when xiangshan is updated to 2.13.11 210 */ 211 def wakeUpInExuSources: Seq[WakeUpSource] = { 212 SeqUtils.distinctBy( 213 exuBlockParams 214 .flatMap(_.iqWakeUpSinkPairs) 215 .map(_.source) 216 )(_.name) 217 } 218 219 def wakeUpOutExuSources: Seq[WakeUpSource] = { 220 SeqUtils.distinctBy( 221 exuBlockParams 222 .flatMap(_.iqWakeUpSourcePairs) 223 .map(_.source) 224 )(_.name) 225 } 226 227 def wakeUpToExuSinks = exuBlockParams 228 .flatMap(_.iqWakeUpSourcePairs) 229 .map(_.sink).distinct 230 231 def numWakeupFromIQ: Int = wakeUpInExuSources.size 232 233 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 234 235 def numWakeupFromWB = { 236 val pregSet = this.pregReadSet 237 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 238 } 239 240 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 && numRegSrc > 0 241 242 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 243 244 // cfgs(exuIdx)(set of exu's wb) 245 246 /** 247 * Get [[PregWB]] of this IssueBlock 248 * @return set of [[PregWB]] of [[ExeUnit]] 249 */ 250 def getWbCfgs: Seq[Set[PregWB]] = { 251 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 252 } 253 254 def canAccept(fuType: UInt): Bool = { 255 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 256 } 257 258 def bindBackendParam(param: BackendParams): Unit = { 259 backendParam = param 260 } 261 262 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 263 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 264 } 265 266 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 267 MixedVec(this.exuParams.map(x => DecoupledIO(x.genExuOutputBundle))) 268 } 269 270 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 271 MixedVec(this.exuParams.map(x => ValidIO(x.genExuOutputBundle))) 272 } 273 274 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 275 MixedVec(this.exuParams.filterNot(_.fakeUnit).map(x => ValidIO(x.genExuBypassBundle))) 276 } 277 278 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 279 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 280 } 281 282 def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 283 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 284 case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 285 case _ => Seq() 286 } 287 val vfBundle = schdType match { 288 case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 289 case _ => Seq() 290 } 291 MixedVec(intBundle ++ vfBundle) 292 } 293 294 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 295 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam)))) 296 } 297 298 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 299 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 300 } 301 302 def genOGRespBundle(implicit p: Parameters) = { 303 implicit val issueBlockParams = this 304 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 305 } 306 307 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 308 implicit val issueBlockParams = this 309 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 310 } 311 312 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 313 implicit val issueBlockParams = this 314 MixedVec(exuBlockParams.map{ x => 315 new WbFuBusyTableReadBundle(x) 316 }) 317 } 318 319 def genWbConflictBundle()(implicit p: Parameters) = { 320 implicit val issueBlockParams = this 321 MixedVec(exuBlockParams.map { x => 322 new WbConflictBundle(x) 323 }) 324 } 325 326 def getIQName = { 327 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 328 } 329} 330