1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3.util._ 5import chisel3._ 6import xiangshan.backend.Bundles.{ExuInput, ExuOutput, IssueQueueIssueBundle, OGRespBundle, WbConflictBundle, WbFuBusyTableReadBundle, WbFuBusyTableWriteBundle} 7import xiangshan.backend.datapath.WbConfig.WbConfig 8import xiangshan.backend.exu.ExeUnitParams 9import xiangshan.backend.fu.{FuConfig, FuType} 10 11case class IssueBlockParams( 12 // top down 13 exuBlockParams : Seq[ExeUnitParams], 14 numEntries : Int, 15 pregBits : Int, 16 numWakeupFromWB : Int, 17 numDeqOutside : Int = 0, 18 numWakeupFromOthers: Int = 0, 19 XLEN : Int = 64, 20 VLEN : Int = 128, 21 vaddrBits : Int = 39, 22 // calculate in scheduler 23 var idxInSchBlk : Int = 0, 24 var numEnq : Int = 0, 25 var numWakeupFromIQ: Int = 0, 26)( 27 implicit 28 // top down 29 val schdType: SchedulerType, 30) { 31 def updateIdx(idx: Int): Unit = { 32 this.idxInSchBlk = idx 33 } 34 35 def inMemSchd: Boolean = schdType == MemScheduler() 36 37 def inIntSchd: Boolean = schdType == IntScheduler() 38 39 def inVfSchd: Boolean = schdType == VfScheduler() 40 41 def isMemAddrIQ: Boolean = inMemSchd && StdCnt == 0 42 43 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 44 45 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 46 47 def numExu: Int = exuBlockParams.length 48 49 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 50 51 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 52 53 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 54 55 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 56 57 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 58 59 def numSrc: Int = exuBlockParams.map(_.numSrc).max 60 61 def readIntRf: Boolean = numIntSrc > 0 62 63 def readFpRf: Boolean = numFpSrc > 0 64 65 def readVecRf: Boolean = numVecSrc > 0 66 67 def readVfRf: Boolean = numVfSrc > 0 68 69 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 70 71 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 72 73 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 74 75 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 76 77 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 78 79 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 80 81 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 82 83 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 84 85 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 86 87 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 88 89 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 90 91 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 92 93 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 94 95 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 96 97 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 98 99 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 100 101 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 102 103 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 104 105 def numDeq: Int = numDeqOutside + exuBlockParams.length 106 107 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 108 109 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 110 111 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 112 113 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 114 115 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 116 117 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 118 119 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 120 121 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 122 123 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 124 125 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 126 127 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 128 129 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 130 131 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 132 133 def LduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "ldu")).sum 134 135 def StaCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "sta")).sum 136 137 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 138 139 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 140 141 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 142 143 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 144 145 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 146 147 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 148 149 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 150 151 def numAllWakeUp = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 152 153 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 154 155 // cfgs(exuIdx)(set of exu's wb) 156 def getWbCfgs: Seq[Set[WbConfig]] = { 157 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 158 } 159 160 def canAccept(fuType: UInt): Bool = { 161 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 162 } 163 164 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 165 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 166 } 167 168 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 169 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuOutputBundle))) 170 } 171 172 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 173 MixedVec(this.exuBlockParams.map(x => ValidIO(x.genExuOutputBundle))) 174 } 175 176 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 177 MixedVec(exuBlockParams.map(x => DecoupledIO(new IssueQueueIssueBundle(this, x, pregBits, vaddrBits)))) 178 } 179 180 def genOGRespBundle(implicit p: Parameters) = { 181 implicit val issueBlockParams = this 182 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 183 } 184 185 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 186 implicit val issueBlockParams = this 187 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 188 } 189 190 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 191 implicit val issueBlockParams = this 192 MixedVec(exuBlockParams.map{ x => 193 new WbFuBusyTableReadBundle(x) 194 }) 195 } 196 197 def genWbConflictBundle()(implicit p: Parameters) = { 198 implicit val issueBlockParams = this 199 MixedVec(exuBlockParams.map { x => 200 new WbConflictBundle(x) 201 }) 202 } 203 204 def getIQName = { 205 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 206 } 207} 208