1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14import xiangshan.SelImm 15 16case class IssueBlockParams( 17 // top down 18 private val exuParams: Seq[ExeUnitParams], 19 val numEntries : Int, 20 numEnq : Int, 21 numComp : Int, 22 numDeqOutside : Int = 0, 23 numWakeupFromOthers : Int = 0, 24 XLEN : Int = 64, 25 VLEN : Int = 128, 26 vaddrBits : Int = 39, 27 // calculate in scheduler 28 var idxInSchBlk : Int = 0, 29)( 30 implicit 31 val schdType: SchedulerType, 32) { 33 var backendParam: BackendParams = null 34 35 val exuBlockParams: Seq[ExeUnitParams] = exuParams.filterNot(_.fakeUnit) 36 37 val allExuParams = exuParams 38 39 def updateIdx(idx: Int): Unit = { 40 this.idxInSchBlk = idx 41 } 42 43 def inMemSchd: Boolean = schdType == MemScheduler() 44 45 def inIntSchd: Boolean = schdType == IntScheduler() 46 47 def inVfSchd: Boolean = schdType == VfScheduler() 48 49 def isMemAddrIQ: Boolean = inMemSchd && (LduCnt > 0 || StaCnt > 0 || VlduCnt > 0 || VstuCnt > 0 || HyuCnt > 0) 50 51 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 52 53 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 54 55 def isHyAddrIQ: Boolean = inMemSchd && HyuCnt > 0 56 57 def isVecLduIQ: Boolean = inMemSchd && VlduCnt > 0 58 59 def isVecStuIQ: Boolean = inMemSchd && VstuCnt > 0 60 61 def isVecMemIQ: Boolean = isVecLduIQ || isVecStuIQ 62 63 def numExu: Int = exuBlockParams.count(!_.fakeUnit) 64 65 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 66 67 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 68 69 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 70 71 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 72 73 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 74 75 def numSrc: Int = exuBlockParams.map(_.numSrc).max 76 77 def readIntRf: Boolean = numIntSrc > 0 78 79 def readFpRf: Boolean = numFpSrc > 0 80 81 def readVecRf: Boolean = numVecSrc > 0 82 83 def readVfRf: Boolean = numVfSrc > 0 84 85 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 86 87 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 88 89 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 90 91 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 92 93 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 94 95 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 96 97 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 98 99 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 100 101 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 102 103 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 104 105 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 106 107 def needSrcVxrm: Boolean = exuBlockParams.map(_.needSrcVxrm).reduce(_ || _) 108 109 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 110 111 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 112 113 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 114 115 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 116 117 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 118 119 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 120 121 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 122 123 def numDeq: Int = numDeqOutside + exuBlockParams.length 124 125 def numSimp: Int = numEntries - numEnq - numComp 126 127 def isAllComp: Boolean = numComp == (numEntries - numEnq) 128 129 def isAllSimp: Boolean = numComp == 0 130 131 def hasCompAndSimp: Boolean = !(isAllComp || isAllSimp) 132 133 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 134 135 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 136 137 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 138 139 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 140 141 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 142 143 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 144 145 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 146 147 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 148 149 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 150 151 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 152 153 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 154 155 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 156 157 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 158 159 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 160 161 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 162 163 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 164 165 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 166 167 def HyuCnt: Int = exuBlockParams.count(_.hasHyldaFu) // only count hylda, since it equals to hysta 168 169 def LdExuCnt = LduCnt + HyuCnt 170 171 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 172 173 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 174 175 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 176 177 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 178 179 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 180 181 /** 182 * Get the regfile type that this issue queue need to read 183 */ 184 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 185 186 /** 187 * Get the regfile type that this issue queue need to read 188 */ 189 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 190 191 /** 192 * Get the max width of psrc 193 */ 194 def rdPregIdxWidth = { 195 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 196 } 197 198 /** 199 * Get the max width of pdest 200 */ 201 def wbPregIdxWidth = { 202 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 203 } 204 205 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 206 207 /** Get exu source wake up 208 * @todo replace with 209 * exuBlockParams 210 * .flatMap(_.iqWakeUpSinkPairs) 211 * .map(_.source) 212 * .distinctBy(_.name) 213 * when xiangshan is updated to 2.13.11 214 */ 215 def wakeUpInExuSources: Seq[WakeUpSource] = { 216 SeqUtils.distinctBy( 217 exuBlockParams 218 .flatMap(_.iqWakeUpSinkPairs) 219 .map(_.source) 220 )(_.name) 221 } 222 223 def wakeUpOutExuSources: Seq[WakeUpSource] = { 224 SeqUtils.distinctBy( 225 exuBlockParams 226 .flatMap(_.iqWakeUpSourcePairs) 227 .map(_.source) 228 )(_.name) 229 } 230 231 def wakeUpToExuSinks = exuBlockParams 232 .flatMap(_.iqWakeUpSourcePairs) 233 .map(_.sink).distinct 234 235 def numWakeupToIQ: Int = wakeUpInExuSources.size 236 237 def numWakeupFromIQ: Int = wakeUpInExuSources.size 238 239 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 240 241 def numWakeupFromWB = { 242 val pregSet = this.pregReadSet 243 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 244 } 245 246 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 && numRegSrc > 0 247 248 def needWakeupFromIntWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name)).groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 249 250 def needWakeupFromVfWBPort = backendParam.allExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 251 252 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 253 254 def deqFuCfgs: Seq[Seq[FuConfig]] = exuBlockParams.map(_.fuConfigs) 255 256 def deqFuInterSect: Seq[FuConfig] = if (numDeq == 2) deqFuCfgs(0).intersect(deqFuCfgs(1)) else Seq() 257 258 def deqFuSame: Boolean = (numDeq == 2) && deqFuInterSect.length == deqFuCfgs(0).length && deqFuCfgs(0).length == deqFuCfgs(1).length 259 260 def deqFuDiff: Boolean = (numDeq == 2) && deqFuInterSect.length == 0 261 262 def deqImmTypes: Seq[UInt] = getFuCfgs.flatMap(_.immType).distinct 263 264 // set load imm to 32-bit for fused_lui_load 265 def deqImmTypesMaxLen: Int = if (isLdAddrIQ || isHyAddrIQ) 32 else deqImmTypes.map(SelImm.getImmUnion(_)).maxBy(_.len).len 266 267 def needImm: Boolean = deqImmTypes.nonEmpty 268 269 // cfgs(exuIdx)(set of exu's wb) 270 271 /** 272 * Get [[PregWB]] of this IssueBlock 273 * @return set of [[PregWB]] of [[ExeUnit]] 274 */ 275 def getWbCfgs: Seq[Set[PregWB]] = { 276 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 277 } 278 279 def canAccept(fuType: UInt): Bool = { 280 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 281 } 282 283 def bindBackendParam(param: BackendParams): Unit = { 284 backendParam = param 285 } 286 287 def wakeUpSourceExuIdx: Seq[Int] = { 288 wakeUpInExuSources.map(x => backendParam.getExuIdx(x.name)) 289 } 290 291 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 292 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 293 } 294 295 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 296 MixedVec(this.exuParams.map(x => DecoupledIO(x.genExuOutputBundle))) 297 } 298 299 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 300 MixedVec(this.exuParams.map(x => ValidIO(x.genExuOutputBundle))) 301 } 302 303 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 304 MixedVec(this.exuParams.filterNot(_.fakeUnit).map(x => ValidIO(x.genExuBypassBundle))) 305 } 306 307 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 308 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 309 } 310 311 def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 312 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 313 case IntScheduler() | MemScheduler() => needWakeupFromIntWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 314 case _ => Seq() 315 } 316 val vfBundle = schdType match { 317 case VfScheduler() | MemScheduler() => needWakeupFromVfWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 318 case _ => Seq() 319 } 320 MixedVec(intBundle ++ vfBundle) 321 } 322 323 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 324 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam, x.copyWakeupOut, x.copyNum)))) 325 } 326 327 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 328 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 329 } 330 331 def genOGRespBundle(implicit p: Parameters) = { 332 implicit val issueBlockParams = this 333 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 334 } 335 336 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 337 implicit val issueBlockParams = this 338 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 339 } 340 341 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 342 implicit val issueBlockParams = this 343 MixedVec(exuBlockParams.map{ x => 344 new WbFuBusyTableReadBundle(x) 345 }) 346 } 347 348 def genWbConflictBundle()(implicit p: Parameters) = { 349 implicit val issueBlockParams = this 350 MixedVec(exuBlockParams.map { x => 351 new WbConflictBundle(x) 352 }) 353 } 354 355 def getIQName = { 356 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 357 } 358 359 def getEntryName = { 360 "Entries" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 361 } 362} 363