1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3.util._ 5import chisel3._ 6import xiangshan.backend.Bundles.{ExuInput, ExuOutput, IssueQueueIssueBundle, OGRespBundle, WbConflictBundle, WbFuBusyTableReadBundle, WbFuBusyTableWriteBundle} 7import xiangshan.backend.datapath.WbConfig.WbConfig 8import xiangshan.backend.exu.ExeUnitParams 9import xiangshan.backend.fu.{FuConfig, FuType} 10 11case class IssueBlockParams( 12 // top down 13 exuBlockParams : Seq[ExeUnitParams], 14 numEntries : Int, 15 pregBits : Int, 16 numWakeupFromWB : Int, 17 numDeqOutside : Int = 0, 18 numWakeupFromOthers: Int = 0, 19 XLEN : Int = 64, 20 VLEN : Int = 128, 21 vaddrBits : Int = 39, 22 // calculate in scheduler 23 var numEnq : Int = 0, 24 var numWakeupFromIQ: Int = 0, 25)( 26 implicit 27 // top down 28 val schdType: SchedulerType, 29) { 30 def inMemSchd: Boolean = schdType == MemScheduler() 31 32 def inIntSchd: Boolean = schdType == IntScheduler() 33 34 def inVfSchd: Boolean = schdType == VfScheduler() 35 36 def isMemAddrIQ: Boolean = inMemSchd && StdCnt == 0 37 38 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 39 40 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 41 42 def numExu: Int = exuBlockParams.length 43 44 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 45 46 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 47 48 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 49 50 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 51 52 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 53 54 def numSrc: Int = exuBlockParams.map(_.numSrc).max 55 56 def readIntRf: Boolean = numIntSrc > 0 57 58 def readFpRf: Boolean = numFpSrc > 0 59 60 def readVecRf: Boolean = numVecSrc > 0 61 62 def readVfRf: Boolean = numVfSrc > 0 63 64 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 65 66 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 67 68 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 69 70 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 71 72 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 73 74 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 75 76 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 77 78 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 79 80 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 81 82 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 83 84 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 85 86 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 87 88 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 89 90 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 91 92 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 93 94 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 95 96 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 97 98 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 99 100 def numDeq: Int = numDeqOutside + exuBlockParams.length 101 102 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 103 104 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 105 106 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 107 108 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 109 110 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 111 112 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 113 114 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 115 116 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 117 118 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 119 120 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 121 122 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 123 124 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 125 126 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 127 128 def LduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "ldu")).sum 129 130 def StaCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "sta")).sum 131 132 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 133 134 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 135 136 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 137 138 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 139 140 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 141 142 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 143 144 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 145 146 def numAllWakeUp = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 147 148 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 149 150 // cfgs(exuIdx)(set of exu's wb) 151 def getWbCfgs: Seq[Set[WbConfig]] = { 152 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 153 } 154 155 def canAccept(fuType: UInt): Bool = { 156 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 157 } 158 159 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 160 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 161 } 162 163 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 164 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuOutputBundle))) 165 } 166 167 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 168 MixedVec(this.exuBlockParams.map(x => ValidIO(x.genExuOutputBundle))) 169 } 170 171 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 172 MixedVec(exuBlockParams.map(x => DecoupledIO(new IssueQueueIssueBundle(this, x, pregBits, vaddrBits)))) 173 } 174 175 def genOGRespBundle(implicit p: Parameters) = { 176 implicit val issueBlockParams = this 177 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 178 } 179 180 def genWbFuBusyTableWriteBundle(implicit p: Parameters) = { 181 implicit val issueBlockParams = this 182 MixedVec(exuBlockParams.map(_ => new WbFuBusyTableWriteBundle())) 183 } 184 185 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 186 implicit val issueBlockParams = this 187 MixedVec(exuBlockParams.map{ x => 188 new WbFuBusyTableReadBundle(x) 189 }) 190 } 191 192 def genWbConflictBundle()(implicit p: Parameters) = { 193 implicit val issueBlockParams = this 194 MixedVec(exuBlockParams.map { x => 195 new WbConflictBundle(x) 196 }) 197 } 198 199 def getIQName = { 200 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 201 } 202} 203