1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig.PregWB 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14 15case class IssueBlockParams( 16 // top down 17 exuBlockParams : Seq[ExeUnitParams], 18 numEntries : Int, 19 numEnq : Int, 20 numDeqOutside : Int = 0, 21 numWakeupFromOthers: Int = 0, 22 XLEN : Int = 64, 23 VLEN : Int = 128, 24 vaddrBits : Int = 39, 25 // calculate in scheduler 26 var idxInSchBlk : Int = 0, 27)( 28 implicit 29 val schdType: SchedulerType, 30) { 31 var backendParam: BackendParams = null 32 33 def updateIdx(idx: Int): Unit = { 34 this.idxInSchBlk = idx 35 } 36 37 def inMemSchd: Boolean = schdType == MemScheduler() 38 39 def inIntSchd: Boolean = schdType == IntScheduler() 40 41 def inVfSchd: Boolean = schdType == VfScheduler() 42 43 def isMemAddrIQ: Boolean = inMemSchd && StdCnt == 0 44 45 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 46 47 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 48 49 def numExu: Int = exuBlockParams.length 50 51 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 52 53 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 54 55 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 56 57 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 58 59 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 60 61 def numSrc: Int = exuBlockParams.map(_.numSrc).max 62 63 def readIntRf: Boolean = numIntSrc > 0 64 65 def readFpRf: Boolean = numFpSrc > 0 66 67 def readVecRf: Boolean = numVecSrc > 0 68 69 def readVfRf: Boolean = numVfSrc > 0 70 71 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 72 73 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 74 75 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 76 77 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 78 79 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 80 81 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 82 83 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 84 85 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 86 87 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 88 89 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 90 91 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 92 93 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 94 95 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 96 97 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 98 99 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 100 101 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 102 103 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 104 105 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 106 107 def numDeq: Int = numDeqOutside + exuBlockParams.length 108 109 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 110 111 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 112 113 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 114 115 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 116 117 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 118 119 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 120 121 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 122 123 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 124 125 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 126 127 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 128 129 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 130 131 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 132 133 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 134 135 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 136 137 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 138 139 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 140 141 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 142 143 def HyuCnt: Int = exuBlockParams.count(_.hasHybridAddrFu) 144 145 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 146 147 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 148 149 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 150 151 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 152 153 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 154 155 /** 156 * Get the regfile type that this issue queue need to read 157 */ 158 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 159 160 /** 161 * Get the regfile type that this issue queue need to read 162 */ 163 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 164 165 /** 166 * Get the max width of psrc 167 */ 168 def rdPregIdxWidth = { 169 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 170 } 171 172 /** 173 * Get the max width of pdest 174 */ 175 def wbPregIdxWidth = { 176 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 177 } 178 179 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 180 181 /** Get exu source wake up 182 * @todo replace with 183 * exuBlockParams 184 * .flatMap(_.iqWakeUpSinkPairs) 185 * .map(_.source) 186 * .distinctBy(_.name) 187 * when xiangshan is updated to 2.13.11 188 */ 189 def wakeUpInExuSources: Seq[WakeUpSource] = { 190 SeqUtils.distinctBy( 191 exuBlockParams 192 .flatMap(_.iqWakeUpSinkPairs) 193 .map(_.source) 194 )(_.name) 195 } 196 197 def wakeUpOutExuSources: Seq[WakeUpSource] = { 198 SeqUtils.distinctBy( 199 exuBlockParams 200 .flatMap(_.iqWakeUpSourcePairs) 201 .map(_.source) 202 )(_.name) 203 } 204 205 def wakeUpToExuSinks = exuBlockParams 206 .flatMap(_.iqWakeUpSourcePairs) 207 .map(_.sink).distinct 208 209 def numWakeupFromIQ: Int = wakeUpInExuSources.size 210 211 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 212 213 def numWakeupFromWB = { 214 val pregSet = this.pregReadSet 215 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 216 } 217 218 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 219 220 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 221 222 // cfgs(exuIdx)(set of exu's wb) 223 224 /** 225 * Get [[PregWB]] of this IssueBlock 226 * @return set of [[PregWB]] of [[ExeUnit]] 227 */ 228 def getWbCfgs: Seq[Set[PregWB]] = { 229 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 230 } 231 232 def canAccept(fuType: UInt): Bool = { 233 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 234 } 235 236 def bindBackendParam(param: BackendParams): Unit = { 237 backendParam = param 238 } 239 240 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 241 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 242 } 243 244 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 245 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuOutputBundle))) 246 } 247 248 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 249 MixedVec(this.exuBlockParams.map(x => ValidIO(x.genExuOutputBundle))) 250 } 251 252 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 253 MixedVec(this.exuBlockParams.map(x => ValidIO(x.genExuBypassBundle))) 254 } 255 256 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 257 MixedVec(exuBlockParams.map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 258 } 259 260 def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 261 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 262 case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 263 case _ => Seq() 264 } 265 val vfBundle = schdType match { 266 case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 267 case _ => Seq() 268 } 269 MixedVec(intBundle ++ vfBundle) 270 } 271 272 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 273 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam)))) 274 } 275 276 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 277 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 278 } 279 280 def genOGRespBundle(implicit p: Parameters) = { 281 implicit val issueBlockParams = this 282 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 283 } 284 285 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 286 implicit val issueBlockParams = this 287 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 288 } 289 290 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 291 implicit val issueBlockParams = this 292 MixedVec(exuBlockParams.map{ x => 293 new WbFuBusyTableReadBundle(x) 294 }) 295 } 296 297 def genWbConflictBundle()(implicit p: Parameters) = { 298 implicit val issueBlockParams = this 299 MixedVec(exuBlockParams.map { x => 300 new WbConflictBundle(x) 301 }) 302 } 303 304 def getIQName = { 305 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 306 } 307} 308