1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig._ 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14import xiangshan.SelImm 15import xiangshan.backend.issue.EntryBundles.EntryDeqRespBundle 16 17case class IssueBlockParams( 18 // top down 19 private val exuParams: Seq[ExeUnitParams], 20 val numEntries : Int, 21 numEnq : Int, 22 numComp : Int, 23 numDeqOutside : Int = 0, 24 numWakeupFromOthers : Int = 0, 25 XLEN : Int = 64, 26 VLEN : Int = 128, 27 vaddrBits : Int = 39, 28 // calculate in scheduler 29 var idxInSchBlk : Int = 0, 30)( 31 implicit 32 val schdType: SchedulerType, 33) { 34 var backendParam: BackendParams = null 35 36 val exuBlockParams: Seq[ExeUnitParams] = exuParams.filterNot(_.fakeUnit) 37 38 val allExuParams = exuParams 39 40 def updateIdx(idx: Int): Unit = { 41 this.idxInSchBlk = idx 42 } 43 44 def inMemSchd: Boolean = schdType == MemScheduler() 45 46 def inIntSchd: Boolean = schdType == IntScheduler() 47 48 def inVfSchd: Boolean = schdType == VfScheduler() 49 50 def isMemAddrIQ: Boolean = inMemSchd && (LduCnt > 0 || StaCnt > 0 || VlduCnt > 0 || VstuCnt > 0 || HyuCnt > 0) 51 52 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 53 54 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 55 56 def isHyAddrIQ: Boolean = inMemSchd && HyuCnt > 0 57 58 def isVecLduIQ: Boolean = inMemSchd && VlduCnt > 0 59 60 def isVecStuIQ: Boolean = inMemSchd && VstuCnt > 0 61 62 def isVecMemIQ: Boolean = isVecLduIQ || isVecStuIQ 63 64 def numExu: Int = exuBlockParams.count(!_.fakeUnit) 65 66 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 67 68 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 69 70 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 71 72 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 73 74 def numV0Src: Int = exuBlockParams.map(_.numV0Src).max 75 76 def numVlSrc: Int = exuBlockParams.map(_.numVlSrc).max 77 78 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 79 80 def numSrc: Int = exuBlockParams.map(_.numSrc).max 81 82 def readIntRf: Boolean = numIntSrc > 0 83 84 def readFpRf: Boolean = numFpSrc > 0 85 86 def readVecRf: Boolean = numVecSrc > 0 87 88 def readVfRf: Boolean = numVfSrc > 0 89 90 def readV0Rf: Boolean = numV0Src > 0 91 92 def readVlRf: Boolean = numVlSrc > 0 93 94 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 95 96 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 97 98 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 99 100 def writeV0Rf: Boolean = exuBlockParams.map(_.writeV0Rf).reduce(_ || _) 101 102 def writeVlRf: Boolean = exuBlockParams.map(_.writeVlRf).reduce(_ || _) 103 104 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 105 106 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 107 108 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 109 110 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 111 112 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 113 114 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 115 116 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 117 118 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 119 120 def needSrcVxrm: Boolean = exuBlockParams.map(_.needSrcVxrm).reduce(_ || _) 121 122 def writeVConfig: Boolean = exuBlockParams.map(_.writeVConfig).reduce(_ || _) 123 124 def writeVType: Boolean = exuBlockParams.map(_.writeVType).reduce(_ || _) 125 126 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 127 128 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 129 130 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 131 132 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 133 134 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 135 136 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 137 138 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 139 140 def numDeq: Int = numDeqOutside + exuBlockParams.length 141 142 def numSimp: Int = numEntries - numEnq - numComp 143 144 def isAllComp: Boolean = numComp == (numEntries - numEnq) 145 146 def isAllSimp: Boolean = numComp == 0 147 148 def hasCompAndSimp: Boolean = !(isAllComp || isAllSimp) 149 150 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 151 152 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 153 154 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 155 156 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 157 158 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 159 160 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 161 162 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 163 164 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 165 166 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 167 168 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 169 170 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 171 172 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 173 174 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 175 176 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 177 178 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 179 180 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 181 182 def HyuCnt: Int = exuBlockParams.count(_.hasHyldaFu) // only count hylda, since it equals to hysta 183 184 def LdExuCnt = LduCnt + HyuCnt 185 186 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 187 188 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 189 190 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 191 192 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 193 194 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 195 196 /** 197 * Get the regfile type that this issue queue need to read 198 */ 199 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 200 201 /** 202 * Get the regfile type that this issue queue need to read 203 */ 204 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 205 206 /** 207 * Get the max width of psrc 208 */ 209 def rdPregIdxWidth = { 210 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 211 } 212 213 /** 214 * Get the max width of pdest 215 */ 216 def wbPregIdxWidth = { 217 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 218 } 219 220 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 221 222 /** Get exu source wake up 223 * @todo replace with 224 * exuBlockParams 225 * .flatMap(_.iqWakeUpSinkPairs) 226 * .map(_.source) 227 * .distinctBy(_.name) 228 * when xiangshan is updated to 2.13.11 229 */ 230 def wakeUpInExuSources: Seq[WakeUpSource] = { 231 SeqUtils.distinctBy( 232 exuBlockParams 233 .flatMap(_.iqWakeUpSinkPairs) 234 .map(_.source) 235 )(_.name) 236 } 237 238 def wakeUpOutExuSources: Seq[WakeUpSource] = { 239 SeqUtils.distinctBy( 240 exuBlockParams 241 .flatMap(_.iqWakeUpSourcePairs) 242 .map(_.source) 243 )(_.name) 244 } 245 246 def wakeUpToExuSinks = exuBlockParams 247 .flatMap(_.iqWakeUpSourcePairs) 248 .map(_.sink).distinct 249 250 def numWakeupToIQ: Int = wakeUpInExuSources.size 251 252 def numWakeupFromIQ: Int = wakeUpInExuSources.size 253 254 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 255 256 def numWakeupFromWB = { 257 val pregSet = this.pregReadSet 258 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 259 } 260 261 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 && numRegSrc > 0 262 263 def needWakeupFromIntWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readIntRf).groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 264 265 def needWakeupFromFpWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readFpRf).groupBy(x => x.getFpWBPort.getOrElse(FpWB(port = -1)).port).filter(_._1 != -1) 266 267 def needWakeupFromVfWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readVecRf).groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 268 269 def needWakeupFromV0WBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readV0Rf).groupBy(x => x.getV0WBPort.getOrElse(V0WB(port = -1)).port).filter(_._1 != -1) 270 271 def needWakeupFromVlWBPort = backendParam.allExuParams.filter(x => !wakeUpInExuSources.map(_.name).contains(x.name) && this.readVlRf).groupBy(x => x.getVlWBPort.getOrElse(VlWB(port = -1)).port).filter(_._1 != -1) 272 273 def hasWakeupFromMem: Boolean = backendParam.allExuParams.filter(x => wakeUpInExuSources.map(_.name).contains(x.name)).map(_.isMemExeUnit).fold(false)(_ | _) 274 275 def hasWakeupFromVf: Boolean = backendParam.allExuParams.filter(x => wakeUpInExuSources.map(_.name).contains(x.name)).map(_.isVfExeUnit).fold(false)(_ | _) 276 277 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 278 279 def deqFuCfgs: Seq[Seq[FuConfig]] = exuBlockParams.map(_.fuConfigs) 280 281 def deqFuInterSect: Seq[FuConfig] = if (numDeq == 2) deqFuCfgs(0).intersect(deqFuCfgs(1)) else Seq() 282 283 def deqFuSame: Boolean = (numDeq == 2) && deqFuInterSect.length == deqFuCfgs(0).length && deqFuCfgs(0).length == deqFuCfgs(1).length 284 285 def deqFuDiff: Boolean = (numDeq == 2) && deqFuInterSect.length == 0 286 287 def deqImmTypes: Seq[UInt] = getFuCfgs.flatMap(_.immType).distinct 288 289 // set load imm to 32-bit for fused_lui_load 290 def deqImmTypesMaxLen: Int = if (isLdAddrIQ || isHyAddrIQ) 32 else deqImmTypes.map(SelImm.getImmUnion(_)).maxBy(_.len).len 291 292 def needImm: Boolean = deqImmTypes.nonEmpty 293 294 // cfgs(exuIdx)(set of exu's wb) 295 296 /** 297 * Get [[PregWB]] of this IssueBlock 298 * @return set of [[PregWB]] of [[ExeUnit]] 299 */ 300 def getWbCfgs: Seq[Set[PregWB]] = { 301 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 302 } 303 304 def canAccept(fuType: UInt): Bool = { 305 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 306 } 307 308 def bindBackendParam(param: BackendParams): Unit = { 309 backendParam = param 310 } 311 312 def wakeUpSourceExuIdx: Seq[Int] = { 313 wakeUpInExuSources.map(x => backendParam.getExuIdx(x.name)) 314 } 315 316 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 317 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 318 } 319 320 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 321 MixedVec(this.exuParams.map(x => DecoupledIO(x.genExuOutputBundle))) 322 } 323 324 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 325 MixedVec(this.exuParams.map(x => ValidIO(x.genExuOutputBundle))) 326 } 327 328 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 329 MixedVec(this.exuParams.filterNot(_.fakeUnit).map(x => ValidIO(x.genExuBypassBundle))) 330 } 331 332 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 333 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 334 } 335 336 def genWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 337 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 338 case IntScheduler() | MemScheduler() => needWakeupFromIntWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 339 case _ => Seq() 340 } 341 val fpBundle = schdType match { 342 case FpScheduler() | MemScheduler() => needWakeupFromFpWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 343 case _ => Seq() 344 } 345 val vfBundle = schdType match { 346 case VfScheduler() | MemScheduler() => needWakeupFromVfWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 347 case _ => Seq() 348 } 349 val v0Bundle = schdType match { 350 case VfScheduler() | MemScheduler() => needWakeupFromV0WBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 351 case _ => Seq() 352 } 353 val vlBundle = schdType match { 354 case VfScheduler() | MemScheduler() => needWakeupFromVlWBPort.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 355 case _ => Seq() 356 } 357 MixedVec(intBundle ++ fpBundle ++ vfBundle ++ v0Bundle ++ vlBundle) 358 } 359 360 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 361 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam, x.copyWakeupOut, x.copyNum)))) 362 } 363 364 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 365 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 366 } 367 368 def genOGRespBundle(implicit p: Parameters) = { 369 implicit val issueBlockParams = this 370 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 371 } 372 373 def genOG2RespBundle(implicit p: Parameters) = { 374 implicit val issueBlockParams = this 375 MixedVec(exuBlockParams.map(_ => new Valid(new EntryDeqRespBundle))) 376 } 377 378 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 379 implicit val issueBlockParams = this 380 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 381 } 382 383 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 384 implicit val issueBlockParams = this 385 MixedVec(exuBlockParams.map{ x => 386 new WbFuBusyTableReadBundle(x) 387 }) 388 } 389 390 def genWbConflictBundle()(implicit p: Parameters) = { 391 implicit val issueBlockParams = this 392 MixedVec(exuBlockParams.map { x => 393 new WbConflictBundle(x) 394 }) 395 } 396 397 def getIQName = { 398 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 399 } 400 401 def getEntryName = { 402 "Entries" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 403 } 404} 405